Winbond W83627F Manual Download | Manualshive

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Summary of Contents for W83627F

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Page 4: ... 0 1 0 5 2 0 0 5 4 0 5 0 0 0 5 4 2 3 0 3 0 33 0 5 4 4 6 3 0 63 6 0 6 7 8 9 3 0 73 7 8 9 0 7 6 3 0 6 2 0 4 3 0 3 0 7 6 0 6 2 9 0 0 4 9 0 3 0 3 4 9 0 0 4 9 0 3 3 0 9 0 3 9 0 3 3 0 3 2 9 0 6 0 6 2 4 9 02 3 0 0 3 2 9 04 6 0 6 6 2 9 0 8 7 2 9 0 0 2 ...

Page 5: ... 0 3 2 9 0 0 1 2 9 0 7 08 0 1 7 2 2 24 2 24 2 3 8 3 2 2 2 2 2 2 2 1 0 4 2 4 4 2 4 2 3 0 1 4 2 4 2 0 4 2 3 0 3 4 2 1 4 2 2 3 1 4 2 4 1 1 4 2 0 3 0 0 1 4 2 0 3 0 0 1 4 2 A 3 0 1 42 2 1 3 0 4 2 3 4 2 3 2 2 1 2 2 0 1 1 ...

Page 6: ... 4 3 0 0 B 3 4 4 3 0 A 4 A 0 A 0 A A 0 B A 0 8 A 3 0 8 0 0 A 8 A 0 0 A 3 3 4 1 2 0 1 0 0 1 1 8 2 0 1 C 2 1 C 4 8 2 47 1 C 8 4 8 2 47 1 C 8 ...

Page 7: ...F A 8 4 4 38 3 0 A 28 4 4 0 F A 48 4 0 F A 8 4 1 F A 8 8 2 8 4 8 4 0 G 0 A 8 4 0 A 8 4 3 0 A 8 4 2 H C 0 A 38 4 4 6 3 0 A 8 4 0 8 8 9 0 A 8 4 0 A 8 4 0 A 8 8 9 4 3 0 A 28 9 4 3 0 A 48 9 2 4 38 A 8 9 4 4 0 A 8 9 4 4 1 6 3 A 8 9 4 2 1 6 3 A 8 9 4 4 1 6 3 9 A 38 9 4 1 3 0 A 8 9 4 0 8 9 4 0 A 8 9 4 7 08 0 A 8 9 4 0 A 8 9 4 3 0 0 A 8 9 ...

Page 8: ... A 8 9 4 0 A 8 9 4 3 0 0 A 8 9 4 7 7 08 0 A 8 9 2 4 7 0 A 8 9 2 4 7 08 0 A 8 9 4 4 0 A 28 9 4 4 0 A 8 4 2 1 C 1 9 0 A 8 4 4 0 A 8 9 4 3 0 A 8 9 4 0 A 8 9 4 0 A 8 9 4 0 A 28 9 4 0 A 48 8 4 7 0 A 8 9 4 7 0 A 8 9 4 7 0 A 8 9 4 2 0 A 38 9 4 4 0 A 8 9 4 1 F A 8 8 4 0 A 8 9 2 ...

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Page 10: ...bility and a processor interrupt system Both UARTs provide legacy speed with baud rate up to 115 2k bps and also advanced speed with baud rates of 230k 460k or 921k bps which support higher speed modems In addition the W83627F HF provides IR functions IrDA 1 0 SIR for 1 152K bps and TV remote IR Consumer IR supporting NEC RC 5 extended RC 5 and RECS 80 protocols The W83627F HF supports one PC comp...

Page 11: ...TURES General Meet LPC Spec 1 0 Support LDRQ LPC DMA SERIRQ serial IRQ Include all the features of Winbond I O W83977TF and W83977EF Integrate Hardware Monitor functions Compliant with Microsoft PC98 PC99 Hardware Design Guide Support DPM Device Power Management ACPI Programmable configuration settings Single 24 or 48 MHz clock input FDC Compatible with IBM PC AT disk drive systems Variable write ...

Page 12: ...0 SIR protocol with maximum baud rate up to 115 2K bps Support SHARP ASK IR protocol with maximum baud rate up to 57 600 bps Support Consumer IR Parallel Port Compatible with IBM parallel port Support PS 2 compatible bi directional parallel port Support Enhanced Parallel Port EPP Compatible with IEEE 1284 specification Support Extended Capabilities Port ECP Compatible with IEEE 1284 specification ...

Page 13: ...orts can serve as simple I O ports interrupt steering inputs watch dog timer output power LED output infrared I O pins KBC control I O pins suspend LED output RSMRST signal PWROK signal Beep output Functional in power down mode GP1 only OnNow Functions Keyboard Wake Up by programmable keys Mouse Wake Up by programmable buttons CIR Wake Up by programmable keys On Now Wake Up from all of the ACPI sl...

Page 14: ... Build in Case open detection circuit WATCHDOG comparison of all monitored values Programmable hysteresis and setting points for all monitored items Over temperature indicate output Automatic Power On voltage detection Beep Issue SMI IRQ OVT to activate system protection Intel LDCM TM Acer ADMTM compatible Package 128 pin PQFP ...

Page 15: ...8 9 8 8 8 7 8 6 8 5 8 4 8 3 8 2 8 1 8 0 7 9 7 8 7 7 7 6 7 5 7 4 7 3 7 2 7 1 7 0 6 9 6 8 6 7 6 6 6 5 GPSB1 P13 GP11 VSS GPSA1 P12 GP10 G P 2 1 G P 2 2 I R R X G P 2 5 I R T X G P 2 6 R I B D C D B V S S S O U T B S I N B D T R B R T S B D S R B C T S B V C C W D T O G P 2 4 S L P _ S X G P 3 0 P L E D G P 2 3 P W R C T L G P 3 1 SUSLED GP35 R S M R S T G P 3 3 P W R O K G P 3 2 C I R R X G P 3 4 P ...

Page 16: ...0 8 9 8 8 8 7 8 6 8 5 8 4 8 3 8 2 8 1 8 0 7 9 7 8 7 7 7 6 7 5 7 4 7 3 7 2 7 1 7 0 6 9 6 8 6 7 6 6 6 5 GPSB1 P13 GP11 VSS GPSA1 P12 GP10 FANPWM1 FANPWM2 FANIO1 FANIO2 FANIO3 S C L G P 2 1 S D A G P 2 2 I R R X G P 2 5 I R T X G P 2 6 R I B D C D B V S S S O U T B S I N B D T R B R T S B D S R B C T S B V C C W D T O G P 2 4 S L P _ S X G P 3 0 P L E D G P 2 3 P W R C T L G P 3 1 SUSLED GP35 R S M R...

Page 17: ...ain output pin with 24 mA sink capability INcs CMOS level Schmitt trigger input pin INt TTL level input pin INtd TTL level input pin with internal pull down resistor INts TTL level Schmitt trigger input pin INtsp3 3 3V TTL level Schmitt trigger input pin 1 1 LPC Interface SYMBOL PIN I O FUNCTION CLKIN 18 INt System clock input According to the input frequency 24MHz or 48MHz it is selectable throug...

Page 18: ...o 0 this pin enables disk drive A This is an open drain output MOB 7 OD24 Motor B On When set to 0 this pin enables disk drive 1 This is an open drain output DIR 8 OD24 Direction of the head step motor An open drain output Logic 1 outward motion Logic 0 inward motion STEP 9 OD24 Step output pulses This active low open drain output produces a pulse to move the head to another track WD 10 OD24 Write...

Page 19: ...tions which are controlled by CR28 and L3 CRF0 SYMBOL PIN I O FUNCTION SLCT 31 INt PRINTER MODE An active high input on this pin indicates that the printer is selected Refer to the description of the parallel port for definition of this pin in ECP and EPP mode OD12 EXTENSION FDD MODE WE2 This pin is for Extension FDD B its function is the same as the WE pin of FDC OD12 EXTENSION 2FDD MODE WE2 This...

Page 20: ...cates that the printer has received data and is ready to accept more data Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode EXTENSION FDD MODE DSB2 This pin is for the Extension FDD B its functions is the same as the DSB pin of FDC EXTENSION 2FDD MODE DSB2 This pin is for Extension FDD A and B its function is the same as the DSB pin of FDC ERR 45 INt ...

Page 21: ...r the printer initialization Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode EXTENSION FDD MODE DIR2 This pin is for Extension FDD B its function is the same as the DIR pin of FDC EXTENSION 2FDD MODE DIR2 This pin is for Extension FDD A and B its function is the same as the DIR pin of FDC AFD 46 OD12 OD12 OD12 PRINTER MODE AFD An active low output f...

Page 22: ...s for Extension FDD A and B its function is the same as the INDEX pin of FDC It is pulled high internally PD1 41 I O12t INt INt PRINTER MODE PD1 Parallel port data bus bit 1 Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode EXTENSION FDD MODE TRAK02 This pin is for Extension FDD B its function is the same as the TRAK0 pin of FDC It is pulled high inte...

Page 23: ...is pulled high internally EXTENSION 2FDD MODE DSKCHG2 This pin is for Extension FDD A and B this function of this pin is the same as the DSKCHG pin of FDC It is pulled high internally PD5 37 I O12t PRINTER MODE PD5 Parallel port data bus bit 5 Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode EXTENSION FDD MODE This pin is a tri state output EXTENSION...

Page 24: ...unicate During power on reset this pin is pulled down internally and is defined as PNPCSV which provides the power on value for CR24 bit 0 PNPCSV A 4 7 kΩ is recommended if intends to pull up clear the default value of FDC UARTs PRT Game port and MIDI port DTRB 81 I O8t UART B Data Terminal Ready An active low signal informs the modem or data set that controller is ready to communicate SINA SINB 5...

Page 25: ... from S5cold state This pin is pulse output active low PSIN 68 INtd Panel Switch Input This pin is high active with an internal pull down resistor 1 7 Hardware Monitor Interface For W83627HF only all these pins in W83627F are NC SYMBOL PIN I O FUNCTION CASEOPEN 76 INt CASE OPEN An active low input from an external device when case is opened This signal can be latched if pin VBAT is connect to batt...

Page 26: ...be programmable input or output FANPWM1 FANPWM2 116 115 O12 Fan speed control Use the Pulse Width Modulatuion PWM technic knowledge to control the Fan s RPM BEEP 118 OD12 Beep function for hardware monitor This pin is low after system reset 1 8 Game Port MIDI Port SYMBOL PIN I O FUNCTION GPSA1 GP10 128 INcs I OD12 Active low Joystick I switch input 1 Default General purpose I O port 1 bit 0 P12 I ...

Page 27: ...it 4 P16 I OD12 Alternate Function Output KBC P16 I O port GPY1 123 I OD12 Joystick I timer pin this pin connect to Y positioning variable resistors for the Josystick Default GP15 I OD12 General purpose I O port 1 bit 5 GPSB2 122 INcs Active low Joystick II switch input 2 This pin has an internal pull up resistor Default GP16 I OD12 General purpose I O port 1 bit 6 GPSA2 121 INcs Active low Joysti...

Page 28: ...OD12t I OD12ts General purpose I O port 2 bit 2 Alternate Function Serial Bus bi directional Data For W83627HF Only GP23 PLED 90 I OD24t OD24t General purpose I O port 2 bit 3 Power LED output this signal is low after system reset Default GP24 89 I OD12t General purpose I O port 2 bit 4 WDTO OD12t Watch dog timer output Default GP25 IRRX 88 I OD12t INts General purpose I O port 2 bit 5 Alternate F...

Page 29: ...s pin generates the RSMRST signal while the VSB come in Default GP34 69 I OD12t General purpose I O port 3 bit 4 CIRRX OD12t Consumer IR receiving input This pin can Wake Up system from S5cold Default GP35 64 I OD24t General purpose I O port 3 bit 5 SUSLED OD24t Suspend LED output it can program to flash when suspend state This function can work without VCC Default 1 10 POWER PINS SYMBOL PIN FUNCT...

Page 30: ...on address data and wait states MR master reset of Winbond ISA I O is replaced with a active low reset signal namely LRESET in Winbond LPC I O An additional 33 MHz PCI clock is needed in Winbond LPC I O for synchronization DMA requests are issued through LDRQ Interrupt requests are issued through SERIRQ Power management events are issued through PME Comparing to its ISA counterpart LPC implementat...

Page 31: ... register sets are a superset of the registers found in a PC AT 3 1 2 FIFO Data The FIFO is 16 bytes in size and has programmable threshold values All command parameter information and disk data transfers go through the FIFO Data transfers are governed by the RQM and DIO bits in the Main Status Register The FIFO defaults to disabled mode after any form of reset This maintains PC AT hardware compat...

Page 32: ...p is provided with a clock which is synchronized to the read data The synchronized clock called the Data Window is used to internally sample the serial data portion of the bit cell and the alternate state samples the clock portion Serial to parallel conversion logic separates the read data into clock and data bytes The Digital Data Separator DDS has three parts control logic error adjustment and s...

Page 33: ...mands Each command is initiated by a multi byte transfer from the microprocessor The result can also be a multi byte transfer back to the microprocessor Each command consists of three phases command execution and result Command The microprocessor issues all required information to the controller to perform a specific operation Execution The controller performs the specified operation Result After ...

Page 34: ...ltitrack N The number of data bytes written in a sector NCN New Cylinder Number ND Non DMA Mode OW Overwritten PCN Present Cylinder Number POLL Polling Disable PRETRK Precompensation Start Track Number R Record RCN Relative Cylinder Number R W Read Write SC Sector per cylinder SK Skip deleted data address mark SRT Step Rate Time ST0 Status Register 0 ST1 Status Register 1 ST2 Status Register 2 ST3...

Page 35: ... Command W MT MFM SK 0 1 1 0 0 Command codes W 0 0 0 0 0 HDS DS1 DS0 W W C H Sector ID information prior to command execution W W R N W W EOT GPL W DTL Execution Data transfer between the FDD and system Result R R R ST0 ST1 ST2 Status information after command execution R R R R C H R N Sector ID information after command execution ...

Page 36: ...ARKS Command W MT MFM SK 0 1 1 0 0 Command codes W 0 0 0 0 0 HDS DS1 DS0 W W C H Sector ID information prior to command execution W W R N W W EOT GPL W DTL Execution Data transfer between the FDD and system Result R R R ST0 ST1 ST2 Status information after command execution R R R R C H R N Sector ID information after command execution ...

Page 37: ...0 Command codes W 0 0 0 0 0 HDS DS1 DS0 W W C H Sector ID information prior to command execution W W R N W W EOT GPL W DTL Execution Data transfer between the FDD and system FDD reads contents of all cylinders from index hole to EOT Result R R R ST0 ST1 ST2 Status information after command execution R R R R C H R N Sector ID information after command execution ...

Page 38: ... D4 D3 D2 D1 D0 REMARKS Command W 0 MFM 0 0 1 0 1 0 Command codes W 0 0 0 0 0 HDS DS1 DS0 Execution The first correct ID information on the cylinder is stored in Data Register Result R R R ST0 ST1 ST2 Status information after command execution R R R R C H R N Disk status after the command has been completed ...

Page 39: ...1 DS0 W W C H Sector ID information prior to command execution W W R N W W EOT GPL DTL SC Execution No data transfer takes place Result R R R ST0 ST1 ST2 Status information after command execution R R R R C H R N Sector ID information after command execution 6 Version PHASE R W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS Command W 0 0 0 1 0 0 0 0 Command code Result R 1 0 0 1 0 0 0 0 Enhanced controller ...

Page 40: ...S Command W MT MFM 0 0 0 1 0 1 Command codes W 0 0 0 0 0 HDS DS1 DS0 W W C H Sector ID information prior to Command execution W W R N W W EOT GPL W DTL Execution Data transfer between the FDD and system Result R R R ST0 ST1 ST2 Status information after Command execution R R R R C H R N Sector ID information after Command execution ...

Page 41: ...MARKS Command W MT MFM 0 0 1 0 0 1 Command codes W 0 0 0 0 0 HDS DS1 DS0 W W C H W W R N Sector ID information prior to command execution W W W EOT GPL DTL Execution Data transfer between the FDD and system Result R R R ST0 ST1 ST2 Status information after command execution R R R R C H R N Sector ID information after command execution ...

Page 42: ... Bytes Sector Sectors Cylinder W W GPL D Gap 3 Filler Byte Execution for Each Sector Repeat W W W W C H R N Input Sector Parameters Result R R R ST0 ST1 ST2 Status information after command execution R R R R Undefined Undefined Undefined Undefined 10 Recalibrate PHASE R W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS Command W 0 0 0 0 0 1 1 1 Command codes W 0 0 0 0 0 0 DS1 DS0 Execution Head retracted to Track...

Page 43: ...SE R W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS Command W 0 0 0 0 0 0 1 1 Command codes W W SRT HUT HLT ND 13 Seek PHASE R W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS Command W 0 0 0 0 1 1 1 1 Command codes W 0 0 0 0 0 HDS DS1 DS0 W NCN Execution R Head positioned over proper cylinder on diskette 14 Configure PHASE R W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS Command W 0 0 0 1 0 0 1 1 Configure information W 0 0 0 0 0 0 0 0 ...

Page 44: ...ARKS Command W 0 0 0 0 1 1 1 0 Registers placed in FIFO Result R R R R R R R PCN Drive 0 PCN Drive 1 PCN Drive 2 PCN Drive 3 SRT HUT HLT ND SC EOT R LOCK 0 D3 D2 D1 D0 GAP WG R R 0 EIS EFIFO POLL FIFOTHR PRETRK 17 Perpendicular Mode PHASE R W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS Command W 0 0 0 1 0 0 1 0 Command Code W OW 0 D3 D2 D1 D0 GAP WG 18 Lock PHASE R W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS Command W ...

Page 45: ...HASE R W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS Command W 0 0 0 0 0 1 0 0 Command Code W 0 0 0 0 0 HDS DS1 DS0 Result R ST3 Status information about disk drive 20 Invalid PHASE R W D7 D6 D5 D4 D3 D2 D1 D0 REMARKS Command W Invalid Codes Invalid codes no operation FDC goes to standby state Result R ST0 ST0 80H ...

Page 46: ...GISTER DT FIFO REGISTER base address 7 DI REGISTER CC REGISTER 3 2 1 Status Register A SA Register Read base address 0 This register is used to monitor several disk interface pins in PS 2 and Model 30 modes In PS 2 mode the bit definitions for this register are as follows 1 2 3 4 5 6 7 0 WP INDEX HEAD TRAK0 STEP DRV2 INIT PENDING DIR INIT PENDING Bit 7 This bit indicates the value of the floppy di...

Page 47: ...t indicates the direction of head movement 0 outward direction 1 inward direction In PS 2 Model 30 mode the bit definitions for this register are as follows 1 2 3 4 5 6 7 0 WP INDEX HEAD TRAK0 STEP F F DRQ INIT PENDING DIR INIT PENDING Bit 7 This bit indicates the value of the floppy disk interrupt output DRQ Bit 6 This bit indicates the value of DRQ output pin STEP F F Bit 5 This bit indicates th...

Page 48: ... SB Register Read base address 1 This register is used to monitor several disk interface pins in PS 2 and Model 30 modes In PS 2 mode the bit definitions for this register are as follows 1 2 3 4 5 6 7 0 MOT EN A WE RDATA Toggle WDATA Toggle Drive SEL0 MOT EN B 1 1 Drive SEL0 Bit 5 This bit indicates the status of DO REGISTER bit 0 drive select bit 0 WDATA Toggle Bit 4 This bit changes state at eve...

Page 49: ... installed 1 A second drive has not been installed DSB Bit 6 This bit indicates the status of DSB output pin DSA Bit 5 This bit indicates the status of DSA output pin WD F F Bit 4 This bit indicates the complement of the latched WD output pin at every rising edge of the WD output pin RDATA F F Bit 3 This bit indicates the complement of the latched RDATA output pin WE F F Bit 2 This bit indicates t...

Page 50: ...en active high Motor Enable B Motor B on when active high Motor Enable C Motor C on when active high Motor Enable D Motor D on when active high 3 2 4 Tape Drive Register TD Register Read base address 3 This register is used to assign a particular drive number to the tape drive support mode of the data separator This register also holds the media ID drive type and floppy boot drive information of t...

Page 51: ... FDD 0 Busy D0B 1 FDD number 0 is in the SEEK mode FDD 1 Busy D1B 1 FDD number 1 is in the SEEK mode FDC Busy CB A read or write command is in the process when CB HIGH Non DMA mode the FDC is in the non DMA mode this bit is set only during the execution phase in non DMA mode Transition to LOW state indicates execution phase has ended DATA INPUT OUTPUT DIO If DIO HIGH then transfer is from Data Reg...

Page 52: ...ect the value of write precompensation The following tables show the precompensation values for the combination of these bits PRECOMP PRECOMPENSATION DELAY 2 1 0 250K 1 Mbps 2 Mbps Tape drive 0 0 0 Default Delays Default Delays 0 0 1 41 67 nS 20 8 nS 0 1 0 83 34 nS 41 17 nS 0 1 1 125 00 nS 62 5nS 1 0 0 166 67 nS 83 3 nS 1 0 1 208 33 nS 104 2 nS 1 1 0 250 00 nS 125 00 nS 1 1 1 0 00 nS disabled 0 00...

Page 53: ...ata bus at a time This register stores data commands and p arameters and provides diskette drive status information Data bytes are passed through the data register to program or obtain results after a command In the W83627HF this register defaults to FIFO disabled mode after reset The FIFO can change its value and enable its operation through the CONFIGURE command Status Register 0 ST0 7 6 5 4 3 2...

Page 54: ...en the FDC tries to access a sector beyond the final sector of a cylinder 0 1 2 3 4 5 6 7 Status Register 2 ST2 1 2 3 4 5 6 7 0 BC Bad Cylinder MD Missing Address Mark in Data Field 1 If the FDC cannot find a data address mark or the address mark has been deleted when reading data from the media 0 No error 1 Bad Cylinder 0 No error SN Scan Not satisfied 1 During execution of the Scan command 0 No ...

Page 55: ...controller During a read of this register these bits are in tri state DSKCHG In the PS 2 mode the bit definitions are as follows 1 2 3 4 5 6 7 0 HIGH DENS DRATE0 DRATE1 DSKCHG 1 1 1 1 DSKCHG Bit 7 This bit indicates the complement of the DSKCHG input Bit 6 3 These bits are always a logic 1 during a read DRATE1 DRATE0 Bit 2 1 These two bits select the data rate of the FDC Refer to the DR register b...

Page 56: ...ster Write base address 7 This register is used to control the data rate In the PC AT and PS 2 mode the bit definitions are as follows x x x x x x DRATE0 DRATE1 0 1 2 3 4 5 7 6 X Reserved Bit 7 2 Reserved These bits should be set to 0 DRATE1 DRATE0 Bit 1 0 These two bits select the data rate of the FDC In the PS 2 Model 30 mode the bit definitions are as follows 1 2 3 4 5 6 7 0 DRATE0 DRATE1 NOPRE...

Page 57: ... UART there are 16 byte FIFOs for both receive and transmit mode 4 2 Register Address 4 2 1 UART Control Register UCR Read Write The UART Control Register controls and defines the protocol for asynchronous data communications including data length stop bit parity and baud rate selection 1 2 3 4 5 6 7 0 Data length select bit 0 DLS0 Data length select bit 1 DLS1 Multiple stop bits enable MSBE Parit...

Page 58: ...ive Level MSB 3 UART Control Register UCR Data Length Select Bit 0 DLS0 Data Length Select Bit 1 DLS1 Multiple Stop Bits Enable MSBE Parity Bit Enable PBE Even Parity Enable EPE Parity Bit Fixed Enable PBFE Set Silence Enable SSE Baudrate Divisor Latch Access Bit BDLAB 4 Handshake Control Register HCR Data Terminal Ready DTR Request to Send RTS Loopback RI Input IRQ Enable Internal Loopback Enable...

Page 59: ...ted or received 1 If MSBE is set to a logical 0 one stop bit is sent and checked 2 If MSBE is set to a logical 1 and data length is 5 bits one and a half stop bits are sent and checked 3 If MSBE is set to a logical 1 and data length is 6 7 or 8 bits two stop bits are sent and checked Bits 0 and 1 DLS0 DLS1 These two bits define the number of data bits that are sent or checked in each serial charac...

Page 60: ...16550 mode it indicates the same condition for the data on top of the FIFO When the CPU reads USR it will clear this bit to a logical 0 Bit 3 NSER This bit is set to a logical 1 to indicate that the received data have no stop bit In 16550 mode it indicates the same condition for the data on top of the FIFO When the CPU reads USR it will clear this bit to a logical 0 Bit 2 PBER This bit is set to a...

Page 61: ...t is internally connected to the modem control input RI Bit 1 This bit controls the RTS output The value of this bit is inverted and output to RTS Bit 0 This bit controls the DTR output The value of this bit is inverted and output to DTR 4 2 4 Handshake Status Register HSR Read Write This register reflects the current state of four input pins for handshake peripherals such as a modem and records c...

Page 62: ...iver FIFO interrupt For example if the interrupt active level is set as 4 bytes once there are more than 4 data characters in the receiver FIFO the interrupt will be activated to notify the CPU to read the data from the FIFO TABLE 4 3 FIFO TRIGGER LEVEL BIT 7 BIT 6 RX FIFO INTERRUPT ACTIVE LEVEL BYTES 0 0 01 0 1 04 1 0 08 1 1 14 Bit 4 5 Reserved Bit 3 When this bit is programmed to logic 1 the DMA...

Page 63: ...below Bit 0 This bit is a logical 1 if there is no interrupt pending If one of the interrupt sources has occurred this bit will be set to a logical 0 TABLE 4 4 INTERRUPT CONTROL FUNCTION ISR INTERRUPT SET AND FUNCTION Bit 3 Bit 2 Bit 1 Bit 0 Interrupt priority Interrupt Type Interrupt Source Clear Interrupt 0 0 0 1 No Interrupt pending 0 1 1 0 First UART Receive Status 1 OER 1 2 PBER 1 3 NSER 1 4 ...

Page 64: ...egister interrupt Bit 2 EUSRI Setting this bit to a logical 1 enables the UART status register interrupt Bit 1 ETBREI Setting this bit to a logical 1 enables the TBR empty interrupt Bit 0 ERDRI Setting this bit to a logical 1 enables the RBR data ready interrupt 4 2 8 Programmable Baud Generator BLL BHL Read Write Two 8 bit registers BLL and BHL compose a programmable baud generator that uses 24 M...

Page 65: ...rror Percentage between desired and actual 50 400 650 2304 75 600 975 1536 110 880 1430 1047 0 18 134 5 1076 1478 5 857 0 099 150 1200 1950 768 300 2400 3900 384 600 4800 7800 192 1200 9600 15600 96 1800 14400 23400 64 2000 16000 26000 58 0 53 2400 19200 31200 48 3600 28800 46800 32 4800 38400 62400 24 7200 57600 93600 16 9600 76800 124800 12 19200 153600 249600 6 38400 307200 499200 3 57600 46080...

Page 66: ...interrupt 0 EN_RX_I Read Write Receiver Thershold Level Interrupt Enable 5 1 3 Bank0 Reg2 Interrupt Status Register ISR Power on default 7 0 00000000 binary Bit Name Read Write Description 7 3 Reserved Reserved 2 TMR_I Read Only Timer Interrupt Set to 1 when timer count to 0 This bit will be affected by 1 the timer registers are defined in Bank4 Reg0 and Bank1 Reg0 1 2 EN_TMR Enable Timer in Bank0...

Page 67: ...shold Level It is to determine the RXTH_I to become 1 when the Receiver FIFO Threshold Level is equal or larger than the defined value shown as follow RXFTL 1 0 00 1 byte RXFTL 1 0 01 4 bytes RXFTL 1 0 10 8 bytes RXFTL 1 0 11 14 bytes 3 TMR_TST Read Write Timer Test Write to 1 then reading the TMRL TMRH will return the programmed values of TMRL TMRH that is does not return down count counter value...

Page 68: ...quency 001 010 011 RX_FSL4 0 Min Max Min Max Min Max 00010 26 1 29 6 24 7 31 7 23 4 34 2 00011 28 2 32 0 26 7 34 3 25 3 36 9 00100 29 4 33 3 27 8 35 7 26 3 38 4 00101 30 0 34 0 28 4 36 5 26 9 39 3 00110 31 4 35 6 29 6 38 1 28 1 41 0 00111 32 1 36 4 30 3 39 0 28 7 42 0 01000 32 8 37 2 31 0 39 8 29 4 42 9 01001 33 6 38 1 31 7 40 8 30 1 44 0 01011 34 4 39 0 32 5 41 8 30 8 45 0 01100 36 2 41 0 34 2 44...

Page 69: ...tion 7 3 Reserved 2 RX_TO Read Write Set to 1 when receiver FIFO or frame status FIFO occurs time out Read this bit will be cleared 1 OV_ERR Read Write Received FIFO overrun Read to clear 0 RDR Read Write This bit is set to a logical 1 to indicate received data are ready to be read by the CPU in the RBR or FIFO After no data are left in the RBR or FIFO the bit will be reset to a logical 0 ...

Page 70: ...then no energy will be received The opposite results will be generated when the bit RXINV Bank0 Reg6 Bit0 is set to 1 5 4 LP_SL 1 0 Read Write Low pass filter source selcetion LP_SL 1 0 00 Select raw IRRX signal LP_SL 1 0 01 Select R B P signal LP_SL 1 0 10 Select D B P signal LP_SL 1 0 11 Reserved 3 2 RXDMSL 1 0 Read Write Receiver Demodulation Source Selection RXDMSL 1 0 00 select B P and L P fi...

Page 71: ...d and the receiver is de actived When this bit is set the receiver samples the IR input continuously at the programmed baud rate and transfers the data to the receiver FIFO 6 RX_PD Read Only Set to 1 whenever a pulse or pulse train modulated pulse is detected by the receiver Can be used by the sofware to detect idle condition Cleared Upon Read 5 Reserved 4 0 FOLVAL Read Only FIFO Level Value Indic...

Page 72: ... some register values shown table as follows TABLE BAUD RATE TABLE BAUD RATE USING 24 MHZ TO GENERATE 1 8461 MHZ Desired Baud Rate Decimal divisor used to generate 16X clock Percent error difference between desired and actual 50 2304 75 1536 110 1047 0 18 134 5 857 0 099 150 768 300 384 600 192 1200 96 1800 64 2000 58 0 53 2400 48 3600 32 4800 24 7200 16 9600 12 19200 6 38400 3 57600 2 115200 1 1 ...

Page 73: ...Write Description 7 0 TMRL Read Write Timer Low Byte Register This is a 12 bit timer another 4 bit is defined in Bank1 Reg5 which resolution is 1 ms that is the programmed maximum time is 2 12 1 ms The timer is a down counter The timer start down count when the bit EN_TMR Enable Timer of Bank0 Reg2 is set to 1 When the timer down count to zero and EN_TMR 1 the TMR_I is set to 1 When the counter do...

Page 74: ... information on disabling power down and on selecting the mode of operation Table 6 1 shows the pin definitions for different modes of the parallel port TABLE 6 1 1 PARALLEL PORT CONNECTOR AND PIN DEFINITIONS HOST CONNECTOR PIN NUMBER OF W83627HF PIN ATTRIBUTE SPP EPP ECP 1 36 O nSTB nWrite nSTB HostClk2 2 9 31 26 24 23 I O PD 0 7 PD 0 7 PD 0 7 10 22 I nACK Intr nACK PeriphClk2 11 21 I BUSY nWait ...

Page 75: ...B2 11 21 I BUSY OD MOB2 OD MOB2 12 19 I PE OD WD2 OD WD2 13 18 I SLCT OD WE2 OD WE2 14 35 O nAFD OD RWC2 OD RWC2 15 34 I nERR OD HEAD2 OD HEAD2 16 33 O nINIT OD DIR2 OD DIR2 17 32 O nSLIN OD STEP2 OD STEP2 6 2 Enhanced Parallel Port EPP TABLE 6 2 PRINTER MODE AND EPP REGISTER ADDRESS A2 A1 A0 REGISTER NOTE 0 0 0 Data port R W 1 0 0 1 Printer status buffer Read 1 0 1 0 Printer control latch Write 1...

Page 76: ... accept data Bit 6 This bit represents the current state of the printer s ACK signal A 0 means the printer has received a character and is ready to accept another Normally this signal will be active for approximately 5 microseconds before BUSY stops Bit 5 Logical 1 means the printer has detected the end of paper Bit 4 Logical 1 means the printer is selected Bit 3 Logical 0 means the printer has en...

Page 77: ... a logic 0 the parallel port is in output mode write This bit can be read and written In SPP mode this bit is invalid and fixed at zero Bit 4 A 1 in this position allows an interrupt to occur when ACK changes from low to high Bit 3 A 1 in this bit position selects the printer Bit 2 A 0 starts the printer 50 microsecond pulse minimum Bit 1 A 1 causes the printer to line feed after a line is printed...

Page 78: ...ata to be output to the host CPU 6 2 5 EPP Data Port 0 3 These four registers are available only in EPP mode Bit definitions of each data port are as follows 1 2 3 4 5 6 7 0 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 When accesses are made to any EPP data port the contents of DB0 DB7 are buffered non inverting and output to the ports PD0 PD7 during a write operation The leading edge of IOW causes an EPP data...

Page 79: ... Data Port 3 R W PD7 PD6 PD 5 PD4 PD3 PD2 PD1 PD0 6 2 7 EPP Pin Descriptions EPP NAME TYPE EPP DESCRIPTION nWrite O Denotes an address or data read or write operation PD 0 7 I O Bi directional EPP address and data bus Intr I Used by peripheral device to interrupt the host nWait I Inactive to acknowledge that data transfer is completed Active to indicate that the device is ready for the next transf...

Page 80: ...n the device for subsequent operations Second the host performs a series of read and or write byte operations to the selected register Four operations are supported on the EPP Address Write Data Write Address Read and Data Read All operations on the EPP device are performed asynchronously 6 2 8 2 EPP Version 1 9 Operation The EPP read write operation can be completed under the following conditions...

Page 81: ...ated Hardware support for compression is optional For more information about the ECP Protocol refer to the Extended Capabilities Port Protocol and ISA Interface Standard 6 3 1 ECP Register and Mode Definitions NAME ADDRESS I O ECP MODES FUNCTION data Base 000h R W 000 001 Data Register ecpAFifo Base 000h R W 011 ECP FIFO Address dsr Base 001h R All Status Register dcr Base 002h R W All Control Reg...

Page 82: ...ows 7 6 5 4 3 2 1 0 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 Mode 011 ECP FIFO Address RLE A data byte written to this address is placed in the FIFO and tagged as an ECP Address RLE The hardware at the ECP port transmits this byte to the peripheral automatically The operation of this register is defined only for the forward direction The bit definitions are as follows 7 6 5 4 3 2 1 0 Address or RLE Address...

Page 83: ... These two bits are logic one during a read and cannot be written Bit 5 This bit has no effect and the direction is always out if mode 000 or mode 010 Direction is valid in all other modes 0 the parallel port is in output mode 1 the parallel port is in input mode Bit 4 Interrupt request enable When this bit is set to a high level it may be used to enable interrupt requests from the parallel port t...

Page 84: ...e handshake from ECP into this FIFO Reads or DMAs from the FIFO will return bytes of ECP data to the system 6 3 7 tFifo Test FIFO Mode Mode 110 Data bytes may be read written or DMAed to or from the system to this FIFO in any direction Data in the tFIFO will not be transmitted to the parallel port lines However data in the tFIFO may be displayed on the parallel port data lines 6 3 8 cnfgA Configur...

Page 85: ...d Parallel Port mode The FIFO is reset in this mode 001 PS 2 Parallel Port mode This is the same as 000 except that direction may be used to tri state the data lines and reading the data register returns the value on the data lines and not the value in the data register 010 Parallel Port FIFO mode This is the same as 000 except that bytes are written or DMAed to the FIFO FIFO data are automaticall...

Page 86: ...bles DMA 0 Disables DMA unconditionally Bit 2 Read Write 1 Disables DMA and all of the service interrupts 0 Enables one of the following cases of interrupts When one of the service interrupts has occurred the serviceIntr bit is set to a 1 by hardware This bit must be reset to 0 to re enable the interrupts Writing a 1 to this bit will not cause an interrupt a dmaEn 1 During DMA this bit is set to a...

Page 87: ...E Address or RLE field 2 dsr nBusy nAck PError Select nFault 1 1 1 1 dcr 1 1 Directio ackIntEn SelectIn nInit autofd strobe 1 cFifo Parallel Port Data FIFO 2 ecpDFifo ECP Data FIFO 2 tFifo Test FIFO 2 cnfgA 0 0 0 1 0 0 0 0 cnfgB compress intrValue 1 1 1 1 1 1 ecr MODE nErrIntrEn dmaEn serviceIntr full empty Notes 1 These registers are available in all modes 2 All FIFOs use one common 16 byte FIFO ...

Page 88: ...ledge a change in the direction of the transfer asserted forward The peripheral drives this signal low to acknowledge nReverseRequest The host relies upon nAckReverse to determine when it is permitted to drive the data bus Select Xflag I Indicates printer on line nAutoFd HostAck O Requests a byte of data from the peripheral when it is asserted This signal indicates whether the data lines contain E...

Page 89: ...t is not in mode 000 or 001 it can only be switched into mode 000 or 001 The direction can be changed only in mode 001 When in extended forward mode the software should wait for the FIFO to be empty before switching back to mode 000 or 001 In ECP reverse mode the software waits for all the data to be read f rom the FIFO before changing back to mode 000 or 001 6 3 13 2 Command Data ECP mode allows ...

Page 90: ...H and ecpAFifo at 000H or from the ecpDFifo located at 400H or to from the tFifo at 400H The host must set the direction state dmaEn 0 and serviceIntr 0 in the programmed I O transfers The ECP requests programmed I O transfers from the host by activating the IRQ pin The programmed I O will empty or fill the FIFO using the appropriate direction and mode 6 4 Extension FDD Mode EXTFDD In this mode th...

Page 91: ... are shown in Table6 1 After the printer interface is set to EXTFDD mode the following occur 1 Pins MOA DSA MOB and DSB will be forced to inactive state 2 Pins DSKCHG RDATA WP TRAK0 and INDEX will be logically ORed with pins PD4 PD0 to serve as input signals to the FDC 3 Pins PD4 PD0 each will have an internal resistor of about 1K ohm to serve as pull up resistor for FDD open drain collector outpu...

Page 92: ...PS 2 mouse checks the parity of the data and presents the data to the system as a byte of data in its output buffer Then The controller will asserts an interrupt to the system when data are placed in its output buffer The keyboard and PS 2 mouse are required to acknowledge all data transmissions No transmission should be sent to the keyboard or PS 2 mouse until an acknowledge is received for the p...

Page 93: ... is expecting a data byte through the controller s input buffer only if the input buffer full bit in the status register is 0 7 3 Status Register The status register is an 8 bit read only register at I O address 64H Default PnP programmable I O address LD5 CR62 and LD5 CR63 that holds information about the status of the keyboard controller and interface It may be read at any time BIT BIT FUNCTION ...

Page 94: ...board Interrupt A4h Test Password Returns 0Fah if Password is loaded Returns 0F1h if Password is not loaded A5h Load Password Load Password until a 0 is received from the system A6h Enable Password Enable the checking of keystrokes for a match with the password A7h Disable Auxiliary Device Interface A8h Enable Auxiliary Device Interface A9h Interface Test BIT 04 03 02 01 00 BIT DEFINITION No Error...

Page 95: ...oard Interface C0h Read Input Port P1 and send data to the system C1h Continuously puts the lower four bits of Port1 into STATUS register C2h Continuously puts the upper four bits of Port1 into STATUS register D0h Send Port2 value to the system D1h Only set reset GateA20 line based on the system data bit 1 D2h Send data back to the system as if it came from Keyboard D3h Send data back to the syste...

Page 96: ...et A 1 on this bit selects hardware KB RESET control logic to control KBRESET signal A 0 on this bit disable hardware KB RESET control logic function When the KBC receives a data follows a D1 command the hardware control logic sets or clears GATE A20 according to the received data bit 1 Similarly the hardware control logic sets or clears KBRESET depending on the received data bit 0 When the KBC re...

Page 97: ... respective bit in selection register CRF0 0 output 1 input Invert port value by setting inversion register CRF2 0 non inverse 1 inverse Port value is read written through data register CRF1 Table 8 1 and 8 2 gives more details on GPIO s assignment In addition GPIO1 is designed to be functional even in power loss condition VCC or VSB is off Figure 8 1 shows the GP I O port s structure Right after ...

Page 98: ...R REGISTER BIT ASSIGNMENT GP I O PORT BIT 0 GP10 BIT 1 GP11 BIT 2 GP12 BIT 3 GP13 GP1 BIT 4 GP14 BIT 5 GP15 BIT 6 GP16 BIT 7 GP17 BIT 0 GP20 BIT 1 GP21 GP2 BIT 2 GP22 BIT 3 GP23 BIT 4 GP24 BIT 5 GP25 BIT 6 GP26 BIT 7 GP27 BIT 0 GP30 BIT 1 GP31 BIT 2 GP32 BIT 3 GP33 GP3 BIT 4 GP34 BIT 5 GP35 BIT 6 GP36 BIT 7 GP37 ...

Page 99: ...W83627HF F PRELIMINARY Publication Release Date November 2000 90 Revision 1 0 Figure 8 1 ...

Page 100: ...it 6 can be used to select one out of these two methods of entering the Extended Function mode as follows HEFRAS address and value 0 write 87h to the location 2Eh twice 1 write 87h to the location 4Eh twice After Power on reset the value on RTSA pin 43 is latched by HEFRAS of CR26 In Compatible PnP a specific value 87h must be written twice to the Extended Functions Enable Register I O port addres...

Page 101: ...n PC AT systems the EFDRs are read write registers with port address 2Fh or 4Fh as described in section 9 2 1 on PC AT systems 9 2 Configuration Sequence To program W83627HF configuration registers the following configuration sequence must be followed 1 Enter the extended function mode 2 Configure the configuration registers 3 Exit the extended function mode 9 2 1 Enter the extended function mode ...

Page 102: ...umes that the EFER is located at 2Eh so EFIR is located at 2Eh and EFDR is located at 2Fh If HEFRAS CR26 bit 6 is set 4Eh can be directly replaced by 4Eh and 2Fh replaced by 4Fh Enter the extended function mode interruptible double write MOV DX 2EH MOV AL 87H OUT DX AL OUT DX AL Configurate logical device 1 configuration register CRF0 MOV DX 2EH MOV AL 07H OUT DX AL point to Logical Device Number ...

Page 103: ... 0 1 0 1 2 3 45 67 8 67 1 ...

Page 104: ... 1 1 1 9 1 8 9 9 9 1 0 1 9 9 0 1 A 67 B A 3 A 1 4 9 1 C 0 80 8 0 1 D B 0 1 B 0 1 B 1 E 1 4 999 B F B 1 1 8 4 G D D D H 0 ...

Page 105: ... 0 1 2 3 4 5 6 7 2 2 7 558 6 7 2 2 3 2 3 9 0 1 2 3 4 5 6 7 2 2 7 558 6 7 2 2 3 2 3 9 ...

Page 106: ... 4 6I J H 4 4 6I J 9 6I J 9 ...

Page 107: ... ...

Page 108: ... ...

Page 109: ... ...

Page 110: ...H 1 B 9 0 1 8 4 6 B9 1 F B DB 4 1 F B 9 B 9DB 1 H 0 0 0 0 1 0 0 2 3 0 2 3 45 6 7 1 3 8 17 8 9 1 1 0 1 0 1 0 2 3 9 1 F B H E 1 6 6 2 2 1 1 B B 1 F B K B H 9 0 B FDB DB 1 DB FDB 1 1 2 D 2 1 0 B B 0 H 1 H E ...

Page 111: ...0 H 1 1 1 1 1 B6 E B 1 B B 1 1 9 B 9 DB 1 1 B B6 1 1 1 B 1 6 2 6 D 2 1 B E Ω Ω Ω B6 E B B E 9 B 1 E D B 1 H D 9 0 B98 4 1 1 1 1 H E β β β 2 2FD 2 B D B H E 9 B 1 1 B H 9DB 1 6D 2 6 D 2 H E B 9DB 1 γ γ γ 2 2FD 2 0 1 DB D B6 B γ 1 1 B 1 9DB ...

Page 112: ... 9 C 9 9 C 9 9 6I J 9 4 4 6ID J 8 4 4 6ID J 94 4 94 H 94 4 94 H F D 0 F D F F D 9 9 F 9 D 9 9 9 9 D 9DD 1 β 1 D2 1 2 D 2 B6 0 09 3 0 0F B H 6 2 B6 E 4 4 ...

Page 113: ... 0 9 3 3 1 1 3 4 17 3 9 1 0 1 0 1 E 1 8 1 H 1 1 FD DB 1 B H 1 0 6 0 1 6 6 6 1 E 1 6 G 6 4 G 4 6D0 DG 1 1 1 H 1 6 ...

Page 114: ... 0 1 1 2 3 1 2 3 D D D DD D DD D 0 0 4 3 9 7 3 4 0 0 4 3 9 7 3 4 9 9 9 0 0 4 3 A 9 3 4 0 0 4 3 B 9 43 3 3 4 A 9 C C ...

Page 115: ... 1 9 4 6D 6D4 L 9 H E 4 6D 0 0 0 1 4 8D 3 D 4 5 6 A 1 9 B H 1 6 ...

Page 116: ... 4 5 6 A 9 H H 1 6 E E E E E E 4 7 28 5 6 A H 1 8 6 1 H 1 H 1 1 H ...

Page 117: ... A 9 H 1 6 1 H 1 F 1 E E F 1 E E E E E G ...

Page 118: ... 4 7 28 5 6 19 H 6 1 H 1 H 1 1 H H 1 6 1 H 1 F 1 E E E F 1 E E E E E ...

Page 119: ... B A B B 7 28 6 4 6ID J B A H B A 1 4 6ID J B A H B A 1 H B A B A 1 B A 1 H 1 B A 1 F 1 E E E 0 E 3 H 3 ...

Page 120: ... 2 1 4 0 HD 0 B 4 6 4 6 M 4 6 1 4 8 8 1 4 1 C 1 4 8 5 HD 4 1 H HD 4 4 9 6 2 4 4 D ...

Page 121: ... 1 1 8 1 2 0 6 6 9 6 H 6 AN 6 9 N 6 H N 6 6 D 9 6 H 6 B 0 0 1 6 O P O P B 0 9B 0 4 6 O P O P B 0 Q 0 1 0 6 O P O P B 0 4 6 O P 6 4 O P 67 B A 6 O P 4 6 0 O P 6 D 9D 4 6 O P O P 6 1 O P ...

Page 122: ... 1 1 8 1 2 0 B 0 6 O P 4 O P 8 4 6 9 9 H H B 6 9 B 6 9 9 H H 6 4 D 9D 6 4 D 9D 6 4 D 9D0 ...

Page 123: ... 2 1 0 H 0 B 6 M 4 9 0 6 6 2 1 6 8 0 B 6 M 4 1 H 4 M 4 6 4 D 6 1 4 6 1 4 A 6 1 4 6 1 4 A 4 M 0 M R CC ...

Page 124: ... 2 5 1 6 8 0 B 6 M 4 H 4 H 4 D B H 4 B H 4 8 FDB H 4 8 F B H 4 8 B 6 4 H 4 8 B 6 H ...

Page 125: ... 2 4 5 1 6 8 0 B 6 M 4 9 6 1 4 D B H 4 4 H 4 8 9DB H 4 8 9 B H 4 8 F B H 2 5 6 1 6 8 0 B 6 M 4 9 ...

Page 126: ... 2 2 5 6 1 6 8 0 B 6 M 4 9 6 1 4 D9 2 1 1 4 2 1 6 8 0 B 6 M 4 1 1 4 9 6 1 ...

Page 127: ... 2 1 2 6 8 0 B O P O P B 0O P 6 M 4 9 4 D9 4 9 B 0 O P 4 6ID0 J 1 2 5 1 6 8 0 B 4 0 M 0 4 6 9 6 1 4 9 6 9 4 O P ...

Page 128: ... 2 1 2 B 6 B 6 4 F B FDB F B D D 9 B 9DB 0 1 0 1 0 1 4 4 B 6 8 1 B B F 1 B 6 8 8 1 B B 9 1 0 0 B 6 4 8 B 6 4 8 8 F B 8 F B 8 8 FDB 8 FDB 8 8 F B 8 F B 8 8 ...

Page 129: ... D D 9 B 8 9 B 8 8 9DB 8 9DB 8 8 B 8 B 8 4 4 8 0 8 8 8 0 8 8 0 0 8 0 8 8 9 9 6 1 1 1 H 1 2 A 1 6 8 0 B O P O P B 0 O P M 1 2 3 4 9 6 9 0 1 0O P 4 6 9 B 0 ...

Page 130: ... 2 5 1 6 8 0 B 6 M 0 0 4 4 9 4 HHH HHH 4 4 9 4 HHH HHH 2 4 1 6 8 4 0 B 6 M 45 0 4 45 0 4 0 4 0 4 ...

Page 131: ...D0 J 1 4 D9 0 1 OD P 9 0 D 2 M OD P 9 0 D 2 M D2 OD P 9 0 2 M D2 OD P 9 0 D 2 M D2 4 9 O P 9 82 M O P 9 0 82 M O P 9 82 M O P 9 6 1 4 9 6 1 2 1B 6 5 1 6 8 0 B 6 M 4 0 0 4 6 1 0 4 A A 9 4 D 6 1 0 4 0 1 9 B 0 B B A ...

Page 132: ... 4 0 1 9 B 0 B B A 4 1 9 B A 1 B A 1 0 4 6 1 4 6 1 2 2 0 0 C DD 1 6 8 0 0 B D 6 M 0 0 4 0 9 1 B9 F B 1 H 1 0 4 1 M M E E 0 4 4 6 1 4 D 1 4 1 1 D 4 1 4 1 1 4 1 4 1 1 ...

Page 133: ... 2 1 4 E 4 5 1 D 0 6 8 0 B 6 M 50 4 50 4 50 4 6 0 4 4 9 6 6 0 4 9 6 1 4 9 H HD G HD 4 2 7 1 0 6 8 0 B O D P D 6 M 4 D9 B 0 4 6 0 D 4 9 B 0 8 4 6 0 ...

Page 134: ... 2 7 1 4 44 2 DD 1 4 6 8 D 0 B 6 M 4 4 1 H 1 4 1 4 4 1 H 1 4 1 4 D 4 1 H 1 4 0 4 4 1 H 1 4 0 4 4 B00 FDB 4 1 H 1 0 4 4 4 F B 4 1 4 4 B 6 4 4 1 4 4 B 6 1 H 1 4 1 ...

Page 135: ... 2 DD 1 42 6 8 D 0 B 6 M 0 7 4 3 4 4 0 4 4 6 1 4 D 4 1 H 1 4 0 4 4 1 H 1 4 0 4 4 1 H 1 4 0 4 4 9DB 4 1 H 1 0 4 4 4 9 B 4 1 H 1 0 4 4 4 F B 4 1 H 1 0 4 ...

Page 136: ... 2 4 6 8 D 0 B 6 M 6 4 0 6 2 1 1 4 6 8 D 0 B O P O P O P 6 M 0 4 0 4 0 4 4 4 4 D 4 4 9 6 1 ...

Page 137: ... 2 4 7 C 4 6 8 D 1 6 M 8 9 4 0 L 0 L 2 7 C 4 6 8 D4 1 6 M 8 9 4 0 L 0 L ...

Page 138: ... 2 2 7 C 5 4 6 8 D 0 B 6 M 8 450 4 8 450 4 8 450 4 8 450 4 8 450 4 8 450 4 4 6 1 4 9 E 4 6 1 4 9 O P 2 M O P 2 M 0 O P 2 M O P D D2 M O P 2 M ...

Page 139: ... 2 1 4 6 8 D0 0 B 6 M 0 0 0 0 4 1 4 4 1 4 4 D 1 4 4 6 1 4 4 4 4 1 1 1 1 4 4 4 0 1 4 4 4 0 1 ...

Page 140: ... 2 1 1 4D 2 1 1 4 2 5 8 1 4 6 8 D 6 M 1 2 3 4 O P 2 5 1 4 6 8 D 6 M 1 3 4 O P 4 9 6 1 ...

Page 141: ... 2 5 1 4 6 8 D 0 B M 0 94 94 4 9D 6 9 6 1 4 9 6 9 B A 1 4 6 9 6 1 4 6 9 B A 4 6 9 2 5 8 8 1 4 6 8 D 0 B 4 6 M 6 0 1 2 3 4 9 9 4 D ...

Page 142: ... 2 4 5 8 1 4 6 8 D 0 B 6 M 6 0 1 3 4 4 4 9 6 1 2 5 8 1 44 6 8 DD 0 B D 6 M 1 2 3 4 9 1 9 9 4 ...

Page 143: ... 2 2 5 1 4 6 8 D 0 B 6 M 1 3 4 1 9 4 4 9 6 1 2 5 8 1 4 6 8 D 6 M 4 9 O P ...

Page 144: ... 2 5 1 4 6 8 D 6 M 4 O P 4 9 6 1 2 5 1 4 6 8 D 0 B 6 M 4 9D 6 9 6 1 4 9 6 9 B A 1 4 6 9 6 1 4 6 9 B A 4 6 9 ...

Page 145: ... 2 5 8 8 1 4 6 8 D 0 B 4 6 M 6 0 1 2 3 4 9 9 4 D 2 5 8 1 4 6 8 D 0 B 6 M 6 0 1 3 4 4 4 9 6 1 ...

Page 146: ... 2 5 8 1 44 6 8 DD 0 B D 6 M 1 2 3 4 9 1 9 9 4 2 5 1 4 6 8 D 0 B 6 M 1 3 4 1 9 4 4 9 6 1 ...

Page 147: ... 2 4 5 1 4 0F 6 8 D 0 B 6 M 0 4 9 6 1 4 8 B4 H 4 8 DB 4 H 2 5 6 1 4 0F 6 8 D 0 B 6 M 0 4 9 6 1 4 4 2 2 1 1 4 ...

Page 148: ... 2 DD 1 4 6 8 D 0 B 6 M 0 90 4 9 6 1 4 D 4 4 1 1 0 4 9 6 1 4 4 B4 4 1 4 4 DB 4 4 1 2 5 1 4 6 8 D 0 B 6 M 0 1 2 3 4 9 1 1 ...

Page 149: ... 2 4 5 1 44 6 8 DD 0 B 6 M 0 1 2 3 4 9 1 1 2 4 5 1 4 6 8 D 0 B 6 M 0 1 2 3 4 9 1 1 2 4 1 1 42 4 ...

Page 150: ... 2 4 1 8 5 1 4 6 8 D 0 B 6 M 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 1 1 4 1 1 4 D 1 1 1 1 4 1 1 1 1 4 FDB B 1 FDB 1 1 1 FDB 4 F B B 1 F B 1 1 1 F B 4 B 6 4 B 1 B 6 4 1 1 1 B 6 4 4 B 6 B 1 B 6 1 1 1 B 6 ...

Page 151: ... 4 1 8 5 1 4 6 8 D 0 B 6 M 0 0 0 0 0 0 0 0 0 0 0 0 0 4 9 6 1 4 D 1 1 1 1 4 1 4 B 1 1 4 9DB B 1 9DB 1 1 1 9DB 4 9 B B 1 9 B 1 1 1 9 B 4 F B B 1 F B 1 1 1 F B 2 44 1 8 5 1 4 6 8 D4 0 B 6 M 0 0 0 0 0 4 9 6 1 ...

Page 152: ...B4 1 1 1 B4 4 DB 4 B 1 DB 4 1 1 1 DB 4 2 4 1 1 4 2 42 1 4 6 8 D0 0 B O P 6 M 9 9 9 9 9 9 4 B 0 B 0 B 0 0 4 9D 6 1 4 9 B 0 1 B 0 1 0 2 4 1 4 4 D DB 4 D B4 D 6 1 D 6 1 D DB 4 8 DD DB 4 8 8 D B4 8 D B4 8 8 2 4 7 1 4 ...

Page 153: ... 67 E 4 1 67 67 6 1 67 0 67 6 7 7 1 6 67 1 9 1 1 1 67 6 H 1 67 6 1 67 6 9 6 67 0 1 67 6 67 6 67 0 6 1 9 0 1 6 67 67 1 67 1 67 6 9 0 6 1 1 1 67 6 0 9 1 67 6 9 67 0 9 ...

Page 154: ... 9 67 6 1B 5 5 6 5 67 67 D 67 D 67 67D 67 67 67 67 67 67 D 67 67 D 67 67 D 2 D D 4 D D 0 D 67 0 1 67 6 1 67 6 H 67 6 C 7 H 67 6 C ...

Page 155: ...Device Number Bit 7 0 CR20 Bit 7 0 DEVIDB7 DEBIDB0 Device ID Bit 7 Bit 0 0x52 read only CR21 Bit 7 0 DEVREVB7 DEBREVB0 Device Rev Bit 7 Bit 0 0x1y read only y is version no CR22 Default 0xff Bit 7 Reserved Bit 6 HMPWD 0 Power down 1 No Power down Bit 5 URBPWD 0 Power down 1 No Power down Bit 4 URAPWD 0 Power down 1 No Power down Bit 3 PRTPWD 0 Power down 1 No Power down Bit 2 1 Reserved Bit 0 FDCP...

Page 156: ...set 1 KBC is enabled after hardware reset This bit is read only and set reset by power on setting pin The corresponding power on setting pin is SOUTA pin 54 Bit 1 Reserved Bit 0 PNPCSV 0 The Compatible PnP address select registers have default values 1 The Compatible PnP address select registers have no default value When trying to make a change to this bit new value of PNPCVS must be complementar...

Page 157: ...en DO register bit 3 is effective on selecting IRQ 1 Disable FDC legacy mode on IRQ and DRQ selection then DO register bit 3 is not effective on selecting IRQ Bit 2 DSPRLGRQ 0 Enable PRT legacy mode on IRQ and DRQ selection then DCR bit 4 is effective on selecting IRQ 1 Disable PRT legacy mode on IRQ and DRQ selection then DCR bit 4 is not effective on selecting IRQ Bit 1 DSUALGRQ 0 Enable UART A ...

Page 158: ...ternal FDC Mode 110 Reserved 111 External two FDC Mode CR29 GPIO3 multiplexed pin selection register VBAT powered Default 0x00 Bit 7 PIN64S 0 SUSLED SUSLED control bits are in CRF3 of Logical Device 9 1 GP35 Bit 6 PIN69S 00 CIRRX 01 GP34 Bit 5 PIN70S 0 RSMRST 1 GP33 Bit 4 PIN71S 0 PWROK 1 GP32 Bit 3 PIN72S 0 PWRCTL 1 GP31 Bit 2 PIN 73S 0 SLP_SX 1 GP30 Bit 1 Reserved Bit 0 Reserved ...

Page 159: ... 6 PIN128S 0 8042 P12 1 GP10 Bit 5 PIN127S 0 8042 P13 1 GP11 Bit 4 PIN126S 0 8042 P14 1 GP12 Bit 3 PIN125S 0 8042 P15 1 GP13 Bit 2 PIN124S 0 8042 P16 1 GP14 Bit 1 PIN120S 0 MSO MIDI Serial Output 1 IRQIN0 select IRQ resource through CRF4 Bit 7 4 of Logical Device 8 Bit 1 PIN119S 0 MS1 MIDI Serial Input 1 GP20 CR2B GPIO multiplexed pin selection register 2 VCC powered Default 0XC0 Bit 7 PIN92S 0 SC...

Page 160: ...cal Device8 SMI For D version only 10 Reserved 11 GP27 CR2C Default 0x00 Reserved CR2E Default 0x00 Test Modes Reserved for Winbond CR2F Default 0x00 Test Modes Reserved for Winbond 13 2 Logical Device 0 FDC CR30 Default 0x01 if PNPCSV 0 during POR default 0x00 otherwise Bit 7 1 Reserved Bit 0 1 Activates the logical device 0 Logical device is inactive CR60 CR 61 Default 0x03 0xf0 if PNPCSV 0 duri...

Page 161: ...A INDEX TRAK0 DSKCHG and WP 0 The internal pull up resistors of FDC are turned on Default 1 The internal pull up resistors of FDC are turned off Bit 6 INTVERTZ This bit determines the polarity of all FDD interface signals 0 FDD interface signals are active low 1 FDD interface signals are active high Bit 5 DRV2EN PS2 mode only When this bit is a logic 0 indicates a second drive is installed and is ...

Page 162: ...ns WE WD stay high Bit 0 SWWP 0 Normal use WP to determine whether the FDD is write protected or not 1 FDD is always write protected CRF2 Default 0xFF Bit 7 6 FDD D Drive Type Bit 5 4 FDD C Drive Type Bit 3 2 FDD B Drive Type Bit 1 0 FDD A Drive Type CRF4 Default 0x00 FDD0 Selection Bit 7 Reserved Bit 6 Precomp Disable 1 Disable FDC Precompensation 0 Enable FDC Precompensation Bit 5 Reserved Bit 4...

Page 163: ...EN DRTS1 DRTS0 DRATE1 DRATE0 MFM FM 1 1 1Meg 1 0 0 0 0 500K 250K 1 0 1 300K 150K 0 1 0 250K 125K 0 1 1 1Meg 1 0 1 0 0 500K 250K 1 0 1 500K 250K 0 1 0 250K 125K 0 1 1 1Meg 1 1 0 0 0 500K 250K 1 0 1 2Meg 0 1 0 250K 125K 0 TABLE B DTYPE0 DTYPE1 DRVDEN0 pin 2 DRVDEN1 pin 3 DRIVE TYPE 0 0 SELDEN DRATE0 4 2 1 MB 3 5 2 1 MB 5 25 2 1 6 1 MB 3 5 3 MODE 0 1 DRATE1 DRATE0 1 0 SELDEN DRATE0 1 1 DRATE0 DRATE1 ...

Page 164: ...yte boundary all modes supported EPP is only available when the base address is on 8 byte boundary CR70 Default 0x07 if PNPCSV 0 during POR default 0x00 otherwise Bit 7 4 Reserved Bit 3 0 These bits select IRQ resource for Parallel Port CR74 Default 0x04 Bit 7 3 Reserved Bit 2 0 These bits select DRQ resource for Parallel Port 0x00 DMA0 0x01 DMA1 0x02 DMA2 0x03 DMA3 0x04 0x07 No DMA active CRF0 De...

Page 165: ...rce for Serial Port 1 CRF0 Default 0x00 Bit 7 2 Reserved Bit 1 0 SUACLKB1 SUACLKB0 00 UART A clock source is 1 8462 Mhz 24MHz 13 01 UART A clock source is 2 Mhz 24MHz 12 10 UART A clock source is 24 Mhz 24MHz 1 11 UART A clock source is 14 769 Mhz 24mhz 1 625 13 5 Logical Device 3 UART B CR30 Default 0x01 if PNPCSV 0 during POR default 0x00 otherwise Bit 7 1 Reserved Bit 0 1 Activates the logical ...

Page 166: ...Mhz 24MHz 1 11 UART B clock source is 14 769 Mhz 24mhz 1 625 CRF1 Default 0x00 Bit 7 Reserved Bit 6 IRLOCSEL IR I O pins location select 0 Through SINB SOUTB 1 Through IRRX IRTX Bit 5 IRMODE2 IR function mode selection bit 2 Bit 4 IRMODE1 IR function mode selection bit 1 Bit 3 IRMODE0 IR function mode selection bit 0 IR MODE IR FUNCTION IRTX IRRX 00X Disable tri state high 010 IrDA Active pulse 1 ...

Page 167: ...R30 Default 0x01 if PNPCSV 0 during POR default 0x00 otherwise Bit 7 1 Reserved Bit 0 1 Activates the logical device 0 Logical device is inactive CR60 CR 61 Default 0x00 0x60 if PNPCSV 0 during POR default 0x00 otherwise These two registers select the first KBC I O base address 0x100 0xFFF on 1 byte boundary CR62 CR 63 Default 0x00 0x64 if PNPCSV 0 during POR default 0x00 otherwise These two regis...

Page 168: ...BRST software control 1 KBRST hardware speed up 13 7 Logical Device 6 CIR CR30 Default 0x00 Bit 7 1 Reserved Bit 0 1 Activates the logical device 0 Logical device is inactive CR60 CR 61 Default 0x00 0x00 These two registers select CIR I O base address 0x100 0xFF8 on 8 byte boundary CR70 Default 0x00 Bit 7 4 Reserved Bit 3 0 These bits select IRQ resource for CIR 13 8 Logical Device 7 Game Port and...

Page 169: ...n its respective bit can only be read CRF2 GP10 GP17 inversion register Default 0x00 When set to a 1 the incoming outgoing port value is inverted When set to a 0 the incoming outgoing port value is the same as in data register 13 9 Logical Device 8 GPIO Port 2 CR30 GP20 GP27 Default 0x00 Bit 7 1 Reserved Bit 0 1 Activate GPIO2 0 GPIO2 is inactive CRF0 GP20 GP27 I O selection register Default 0xFF ...

Page 170: ...eyboard Reset P20 to force Time out event 0 Disable 1 Enable Bit 1 0 Reserved CRF6 Default 0x00 Watch Dog Timer Time out value Writing a non zero value to this register causes the counter to load the value to Watch Dog Counter and start counting down If the Bit 7 and Bit 6 are set any Mouse Interrupt or Keyboard Interrupt event will also cause the reload of previously loaded non zero value to Watc...

Page 171: ...ivate GPIO3 0 GPIO3 is inactive CRF0 GP30 GP35 I O selection register Default 0xFF Bit 7 6 Reserve When set to a 1 respective GPIO port is programmed as an input port When set to a 0 respective GPIO port is programmed as an output port CRF1 GP30 GP35 data register Default 0x00 Bit 7 6 Reserve If a port is programmed to be an output port then its respective bit can be read written If a port is prog...

Page 172: ...up function 1 Enable Mouse wake up function Bit 4 MSRKEY Select Mouse Left Right Botton to wake up system via PANSW_OUT 0 Select click on Mouse Left botton twice to wake the system up 1 Select click on Mouse right botton twice to wake the system up Bit 3 ENCIRWAKEUP Enable CIR to wake up system via PANSW_OUT 0 Disable CIR wake up function 1 Enable CIR wake up function Bit 2 KB MS Swap Enable Keybo...

Page 173: ...leared by reading this register Bit 1 Mouse_STS The Panel switch event is caused by Mouse wake up event This bit is cleared by reading this register Bit 0 Keyboard_STS The Panel switch event is caused by Keyboard wake up event This bit is cleared by reading this register CRE4 Default 0x00 Bit 7 Power loss control bit 2 0 Disable ACPI resume 1 Enable ACPI resume Bit 6 5 Power loss control bit 1 0 0...

Page 174: ... Data 1 Inverting RX Data 0 Not inverting RX Data Bit 0 Enable Demodulation 1 Enable received signal to demodulate 0 Disable received signal to demodulate CRF0 Default 0x00 Bit 7 CHIPPME Chip level auto power management enable 0 disable the auto power management functions 1 enable the auto power management functions Bit 6 CIRPME Consumer IR port auto power management enable 0 disable the auto powe...

Page 175: ...achine will transition the system to the working state This bit is only set by hardware and is cleared by writing a 1 to this bit position or by the sleeping working state machine automatically when the global standby timer expires 0 the chip is in the sleeping state 1 the chip is in the working state Bit 6 5 Devices trap status Bit 4 Reserved Return zero when read Bit 3 0 Devices trap status CRF3...

Page 176: ...RQSTS or URBIRQEN and URBIRQSTS or HMIRQEN and HMIRQSTS or WDTIRQEN and WDTIRQSTS or IRQIN3EN and IRQIN3STS or IRQIN2EN and IRQIN2STS or IRQIN1EN and IRQIN1STS or IRQIN0EN and IRQIN0STS Bit 5 MOUIRQEN 0 disable the generation of an SMI PME interrupt due to MOUSE s IRQ 1 enable the generation of an SMI PME interrupt due to MOUSE s IRQ Bit 4 KBCIRQEN 0 disable the generation of an SMI PME interrupt ...

Page 177: ...e the generation of an SMI PME interrupt due to MIDI s IRQ Bit 1 IRQIN1EN 0 disable the generation of an SMI PME interrupt due to IRQIN1 s IRQ 1 enable the generation of an SMI PME interrupt due to IRQIN1 s IRQ Bit 0 IRQIN0EN 0 disable the generation of an SMI PME interrupt due to IRQIN0 s IRQ 1 enable the generation of an SMI PME interrupt due to IRQIN0 s IRQ CRF9 Default 0x00 Bit 7 3 Reserved Re...

Page 178: ...0 Logical device is inactive CR60 CR 61 Default 0x00 0x00 These two registers select Hardware Monitor base address 0x100 0xFFF on 8 byte boundary CR70 Default 0x00 Bit 7 4 Reserved Bit 3 0 These bits select IRQ resource for Hardware Monitor CRF0 Default 0x00 Bit 7 1 Reserved Bit 0 Disable initial abnormal beep VcoreA and 3 3 V 0 Enable power on abnormal beep 1 Disable power on abnormal beep ...

Page 179: ...P MAX UNIT CONDITIONS RTC Battery Quiescent Current IBAT 2 4 uA VBAT 2 5 V ACPI Stand by Power Supply Quiescent Current IBAT 2 0 mA VSB 5 0 V All ACPI pins are not connected I O8t TTL level bi directional pin with source sink capability of 8 mA Input Low Voltage VIL 0 8 V Input High Voltage VIH 2 0 V Output Low Voltage VOL 0 4 V IOL 8 mA Output High Voltage VOH 2 4 V IOH 8 mA Input High Leakage IL...

Page 180: ...h Leakage ILIH 10 µA VIN 3 3V Input Low Leakage ILIL 10 µA VIN 0V I O24t TTL level bi directional pin with source sink capability of 24 mA Input Low Voltage VIL 0 8 V Input High Voltage VIH 2 0 V Output Low Voltage VOL 0 4 V IOL 24 mA Output High Voltage VOH 2 4 V IOH 24 mA Input High Leakage ILIH 10 µA VIN VDD Input Low Leakage ILIL 10 µA VIN 0V OUT12t TTL level output pin with source sink capabi...

Page 181: ...gered input pin Input Low Threshold Voltage Vt 1 3 1 5 1 7 V VDD 5 V Input High Threshold Voltage Vt 3 2 3 5 3 8 V VDD 5 V Hystersis VTH 1 5 2 V VDD 5 V Input High Leakage ILIH 10 µA VIN VDD Input Low Leakage ILIL 10 µA VIN 0 V INts TTL level Schmitt triggered input pin Input Low Threshold Voltage Vt 0 5 0 8 1 1 V VDD 5 V Input High Threshold Voltage Vt 1 6 2 0 2 4 V VDD 5 V Hystersis VTH 0 5 1 2 ...

Page 182: ...29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 PRINTER PORT 13 25 12 24 11 23 10 22 9 21 8 20 7 19 6 18 5 17 4 16 3 15 2 14 1 JP13 WE2 SLCT WD2 PE MOB2 BUSY DSB2 ACK PD7 PD6 PD5 DCH2 PD4 RDD2 PD3 STEP2 SLIN WP2 PD2 DIR2 INIT TRK02 PD1 HEAD2 ERR IDX2 PD0 RWC2 AFD STB JP 13A EXT FDC DCH2 TRK02 RDD2 DIR2 WP2 MOB2 RWC2 DSB2 HEAD2 STEP2 WD2 WE2 IDX2 Parallel Port Extension FDD Mode Connection Diagram ...

Page 183: ...PE MOB2 BUSY DSB2 ACK PD5 DCH2 PD4 RDD2 PD3 STEP2 SLIN WP2 PD2 DIR2 INIT TRK02 PD1 HEAD2 ERR IDX2 PD0 RWC2 AFD STB JP 13A EXT FDC DCH2 TRK02 RDD2 DIR2 WP2 MOB2 RWC2 DSB2 HEAD2 STEP2 WD2 WE2 IDX2 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 DSA2 MOA2 Parallel Port Extension 2FDD Connection Diagram DSA2 PD7 MOA2 PD6 15 3 Four FDD Mode G1 A1 B1 G2 A2 B2 1Y0 1Y1 1Y2 1Y3 2Y0 2Y1 2Y2 2Y3 DSA MOA DSA D...

Page 184: ...Example The top marking of W83627HF AW inbond W83627HF AW 821A2B282012345 AM MEGA 87 96 1st line Winbond logo 2nd line the type number W83627HF AW 3rd line the source of KBC F W American Megatrends Incorporated TM 4th line the tracking code 821 A 2 C 282012345 821 packages made in 98 week 21 A assembly house ID A means ASE S means SPIL etc 2 Winbond internal use B IC revision A means version A B m...

Page 185: ...19 90 20 00 20 10 23 00 23 20 23 40 0 35 0 45 0 003 0 0 063 0 037 0 685 0 031 0 677 0 025 0 669 0 020 0 555 0 008 0 012 0 113 0 551 0 107 0 547 0 004 0 004 0 101 0 010 Max Nom Min Dimension in inch 0 006 0 008 7 0 783 0 787 0 791 0 905 0 913 0 921 0 014 0 018 Headquarters No 4 Creation Rd III Science Based Industrial Park Hsinchu Taiwan TEL 886 35 770066 FAX 886 35 789467 www http www winbond com ...

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