Winbond 25Q16BVFIG User Manual Download Page 17

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W25Q16BV

- 20 -

11.2.4

Instruction Set Table 3 (ID, Security Instructions)

INSTRUCTION

NAME

BYTE 1
(CODE)

BYTE 2

BYTE 3

BYTE 4

BYTE 5

BYTE 6

Release Power down /
Device ID

ABh

dummy dummy

dummy

(ID7-ID0)

(1)

Manufacturer/
Device ID

(2)

90h

dummy dummy

00h

(MF7-MF0)

(ID7-ID0)

Manufacturer/Device ID
by Dual I/O

92h

A23-A8

A7-A0, M[7:0]

(MF[7:0], ID[7:0])

Manufacture/Device ID
by Quad I/O

94h

A23-A0, M[7:0] xxxx, (MF[7:0], ID[7:0]) (MF[7:0], ID[7:0], …)

JEDEC ID

9Fh

(MF7-MF0)

Manufacturer

(ID15-ID8)

Memory Type

(ID7-ID0)

Capacity

Read Unique ID

4Bh

dummy dummy

dummy

(ID63-ID0)

Notes:

1. The Device ID will repeat continuously until /CS terminates the instruction.

2. See Manufacturer and Device Identification table for Device ID information.

Summary of Contents for 25Q16BVFIG

Page 1: ...W25Q16BV Publication Release Date July 08 2010 1 Revision F 16M BIT SERIAL FLASH MEMORY WITH DUAL AND QUAD SPI...

Page 2: ...Mode allows for efficient memory access with as few as 8 clocks of instruction overhead to read a 24 bit address allowing true XIP execute in place operation A Hold pin Write Protect pin and programma...

Page 3: ...WP IO2 GND VCC HOLD IO3 CLK DI IO0 Figure 1a W25Q16BV Pin Assignments 8 pin SOIC 150 208 mil Package Code SN SS 4 PAD CONFIGURATION WSON 6X5 MM 1 2 3 4 8 7 6 5 CS DO IO1 WP IO2 GND VCC HOLD IO3 CLK DI...

Page 4: ...PIN DESCRIPTION SOIC 150 208 MIL PDIP 300 MIL AND WSON 6X5 MM PIN NO PIN NAME I O FUNCTION 1 CS I Chip Select Input 2 DO IO1 I O Data Output Data Input Output 1 1 3 WP IO2 I O Write Protect Input Dat...

Page 5: ...OIC 300 MIL PAD NO PAD NAME I O FUNCTION 1 HOLD IO3 I O Hold Input Data Input Output 3 2 2 VCC Power Supply 3 N C No Connect 4 N C No Connect 5 N C No Connect 6 N C No Connect 7 CS I Chip Select Input...

Page 6: ...put pin Standard SPI also uses the unidirectional DO output to read data or status from the device on the falling edge CLK Dual and Quad SPI instruction use the bidirectional IO pins to serially write...

Page 7: ...FF00h xxFFFFh Sector 15 4KB xxF000h xxF0FFh Block Segmentation Data Write Protect Logic and Row Decode DO IO1 DI IO0 CS CLK HOLD IO3 WP IO2 00FF00h 00FFFFh Block 0 64KB 000000h 0000FFh 07FF00h 07FFFFh...

Page 8: ...w data to be transferred to or from the device four to six times the rate of ordinary Serial Flash The Quad Read instructions offer a significant improvement in continuous and random access transfer r...

Page 9: ...a time delay of tPUW This includes the Write Enable Page Program Sector Erase Block Erase Chip Erase and the Write Status Register instructions Note that the chip select pin CS must track the VCC sup...

Page 10: ...S1 that is set to a 1 after executing a Write Enable Instruction The WEL status bit is cleared to a 0 when the device is write disabled A write disable state occurs upon power up or after any of the...

Page 11: ...er down power up cycle 2 1 1 X One Time Program 1 Status Register is permanently protected and can not be written to Note 1 These features are available upon special order Please refer to Ordering Inf...

Page 12: ...P2 BP1 BP0 WEL BUSY STATUS REGISTER PROTECT 0 non volatile SECTOR PROTECT non volatile TOP BOTTOM PROTECT non volatile BLOCK PROTECT BITS non volatile WRITE ENABLE LATCH ERASE WRITE IN PROGRESS Figure...

Page 13: ...000000h 00FFFFh 64KB Lower 1 32 0 1 0 1 0 0 and 1 000000h 01FFFFh 128KB Lower 1 16 0 1 0 1 1 0 thru 3 000000h 03FFFFh 256KB Lower 1 8 0 1 1 0 0 0 thru 7 000000h 07FFFFh 512KB Lower 1 4 0 1 1 0 1 0 th...

Page 14: ...Instructions are completed with the rising edge of edge CS Clock relative timing diagrams for each instruction are included in figures 4 through 32 All read instructions can be completed after any clo...

Page 15: ...32KB 52h A23 A16 A15 A8 A7 A0 Block Erase 64KB D8h A23 A16 A15 A8 A7 A0 Chip Erase C7h 60h Erase Suspend 75h Erase Resume 7Ah Power down B9h Continuous Read Mode Reset 4 FFh FFh Notes 1 Data bytes ar...

Page 16: ...D7 D0 6 D7 D0 3 Octal Word Read Quad I O 8 E3h A23 A0 M7 M0 4 D7 D0 3 Notes 1 Dual Output data IO0 D6 D4 D2 D0 IO1 D7 D5 D3 D1 2 Dual Input Address IO0 A22 A20 A18 A16 A14 A12 A10 A8 A6 A4 A2 A0 M6 M4...

Page 17: ...D7 ID0 Manufacturer Device ID by Dual I O 92h A23 A8 A7 A0 M 7 0 MF 7 0 ID 7 0 Manufacture Device ID by Quad I O 94h A23 A0 M 7 0 xxxx MF 7 0 ID 7 0 MF 7 0 ID 7 0 JEDEC ID 9Fh MF7 MF0 Manufacturer ID1...

Page 18: ...e Data Input DI pin on the rising edge of CLK and then driving CS high Figure 4 Write Enable Instruction Sequence Diagram 11 2 6 Write Disable 04h The Write Disable instruction Figure 5 resets the Wri...

Page 19: ...irst as shown in figure 6 The Status Register bits are shown in figure 3a and 3b and include the BUSY WEL BP2 BP0 TB SEC SRP0 SRP1 QE and SUS bits see description of the Status Register earlier in thi...

Page 20: ...25X series the QE and SRP1 bits will be cleared to 0 After CS is driven high the self timed Write Status Register cycle will commence for a time duration of tW See AC Characteristics While the Write...

Page 21: ...nt bit MSB first The address is automatically incremented to the next higher address after each byte of data is shifted out allowing for a continuous stream of data This means that the entire memory c...

Page 22: ...highest possible frequency of FR see AC Electrical Characteristics This is accomplished by adding eight dummy clocks after the 24 bit address as shown in figure 9 The dummy clocks allow the devices in...

Page 23: ...t cache code segments to RAM for execution Similar to the Fast Read instruction the Fast Read Dual Output instruction can operate at the highest possible frequency of FR see AC Electrical Characterist...

Page 24: ...uction allows data to be transferred from the W25Q16BV at four times the rate of standard SPI devices The Fast Read Quad Output instruction can operate at the highest possible frequency of FR see AC E...

Page 25: ...or exclusion of the first byte instruction code The lower nibble bits of the M3 0 are don t care x However the IO pins should be high impedance prior to the falling edge of the first data out clock If...

Page 26: ...W25Q16BV Publication Release Date July 08 2010 29 Revision F Figure 12b Fast Read Dual I O Instruction Sequence Diagram M7 0 Axh...

Page 27: ...Quad I O instruction through the inclusion or exclusion of the first byte instruction code The lower nibble bits of the M3 0 are don t care x However the IO pins should be high impedance prior to the...

Page 28: ...W25Q16BV Publication Release Date July 08 2010 31 Revision F Figure 13b Fast Read Quad I O Instruction Sequence Diagram M7 0 Axh...

Page 29: ...of the M3 0 are don t care x However the IO pins should be high impedance prior to the falling edge of the first data out clock If the Continuous Read Mode bits M7 0 equals Ax hex then the next Word R...

Page 30: ...n F Byte 1 Byte 2 Byte 3 4 0 4 0 4 0 5 1 5 1 5 1 6 2 6 2 6 2 7 3 7 3 7 3 Byte 1 Byte 2 Byte 3 4 0 4 0 4 0 4 0 4 0 4 0 5 1 5 1 5 1 5 1 5 1 5 1 6 2 6 2 6 2 6 2 6 2 6 2 7 3 7 3 7 3 7 3 7 3 7 3 Figure 14b...

Page 31: ...ver the IO pins should be high impedance prior to the falling edge of the first data out clock If the Continuous Read Mode bits M7 0 equals Ax hex then the next Octal Word Read Quad I O instruction af...

Page 32: ...d I O Instruction Sequence Diagram M7 0 Axh Byte 2 Byte 3 Byte 4 4 0 4 0 4 0 5 1 5 1 5 1 6 2 6 2 6 2 7 3 7 3 7 3 Byte 1 4 0 5 1 6 2 7 3 Byte 2 Byte 3 Byte 4 4 0 4 0 4 0 4 0 4 0 4 0 5 1 5 1 5 1 5 1 5 1...

Page 33: ...ffect on other bytes within the same page One condition to perform a partial page program is that the number of clocks can not exceed the remaining page length If more than 256 bytes are sent to the d...

Page 34: ...time it take to clock in the data To use Quad Page Program the Quad Enable in Status Register 2 must be set QE 1 A Write Enable instruction must be executed before the device will accept the Quad Page...

Page 35: ...ctor Erase instruction will not be executed After CS is driven high the self timed Sector Erase instruction will commence for a time duration of tSE See AC Characteristics While the Sector Erase cycle...

Page 36: ...f this is not done the Block Erase instruction will not be executed After CS is driven high the self timed Block Erase instruction will commence for a time duration of tBE1 See AC Characteristics Whil...

Page 37: ...lock Erase instruction will not be executed After CS is driven high the self timed Block Erase instruction will commence for a time duration of tBE See AC Characteristics While the Block Erase cycle i...

Page 38: ...p Erase instruction will not be executed After CS is driven high the self timed Chip Erase instruction will commence for a time duration of tCE See AC Characteristics While the Chip Erase cycle is in...

Page 39: ...it equals to 0 the Suspend instruction will be ignored by the device A maximum of time of tSUS See AC Characteristics is required to suspend the erase operation The BUSY bit in the Status Register wil...

Page 40: ...diately the BUSY bit will be set from 0 to 1 within 200ns and the Sector or Block will complete the erase operation If the SUS bit equals to 0 or the BUSY bit equals to 1 the Resume instruction 7Ah wi...

Page 41: ...is is not done the Power down instruction will not be executed After CS is driven high the power down state will entered within the time duration of tDP See AC Characteristics While in the power down...

Page 42: ...S pin low and shifting the instruction code ABh followed by 3 dummy bytes The Device ID bits are then shifted out on the falling edge of CLK with most significant bit MSB first as shown in figure 25b...

Page 43: ...W25Q16BV 46 Figure 25b Release Power down Device ID Instruction Sequence Diagram...

Page 44: ...ode 90h followed by a 24 bit address A23 A0 of 000000h After which the Manufacturer ID for Winbond EFh and the Device ID are shifted out on the falling edge of CLK with most significant bit MSB first...

Page 45: ...ut the Address bits two bits per clock After which the Manufacturer ID for Winbond EFh and the Device ID are shifted out 2 bits per clock on the falling edge of CLK with most significant bits MSB firs...

Page 46: ...dummy cycles with the capability to input the Address bits four bits per clock After which the Manufacturer ID for Winbond EFh and the Device ID are shifted out four bits per clock on the falling edg...

Page 47: ...ue ID instruction is initiated by driving the CS pin low and shifting the instruction code 4Bh followed by a four bytes of dummy clocks After which the 64 bit ID is shifted out on the falling edge of...

Page 48: ...on is initiated by driving the CS pin low and shifting the instruction code 9Fh The JEDEC assigned Manufacturer ID byte for Winbond EFh and two Device ID bytes Memory Type ID15 ID8 and Capacity ID7 ID...

Page 49: ...commended to issue a Continuous Read Mode Reset instruction as the first instruction after a system Reset Doing so will release the Continuous Read Mode from the Ax hex state and allow Standard SPI in...

Page 50: ...on outside of these levels is not guaranteed Exposure to absolute maximum ratings may affect device reliability Exposure beyond absolute maximum ratings may cause permanent damage 2 Compliant with JED...

Page 51: ...hold SPEC PARAMETER SYMBOL MIN MAX UNIT VCC min to CS Low tVSL 1 10 s Time Delay Before Write Instruction tPUW 1 1 10 ms Write Inhibit Threshold Voltage VWI 1 1 2 V Note 1 These parameters are charact...

Page 52: ...1 VCC 0 9 VCC DO Open 6 7 8 9 10 5 12 mA Current Read Data Dual Quad 50MHz 2 ICC3 C 0 1 VCC 0 9 VCC DO Open 7 8 9 10 12 13 5 mA Current Read Data Dual Output Read Quad Output Read 80MHz 2 ICC3 C 0 1 V...

Page 53: ...t Rise and Fall Times TR TF 5 ns Input Pulse Voltages VIN 0 2 VCC to 0 8 VCC V Input Timing Reference Voltages IN 0 3 VCC to 0 7 VCC V Output Timing Reference Voltages OUT 0 5 VCC to 0 5 VCC V Note 1...

Page 54: ...tCLL 1 4 5 ns Clock High Low Time for Read Data 03h instruction tCRLH tCRLL 1 6 ns Clock Rise Time peak to peak tCLCH 2 0 1 V ns Clock Fall Time peak to peak tCHCL 2 0 1 V ns CS Active Setup Time rel...

Page 55: ...Read tRES2 2 1 8 s CS High to next Instruction after Suspend tSUS 2 20 s Write Status Register Time tW 10 15 ms Byte Program Time First Byte 4 tBP1 20 50 s Additional Byte Program Time After First By...

Page 56: ...W25Q16BV Publication Release Date July 08 2010 59 Revision F 12 8 Serial Output Timing 12 9 Serial Input Timing 12 10 Hold Timing...

Page 57: ...33 0 51 0 013 0 020 c 0 19 0 25 0 008 0 010 E 3 3 80 4 00 0 150 0 157 D 3 4 80 5 00 0 188 0 196 e 2 1 27 BSC 0 050 BSC HE 5 80 6 20 0 228 0 244 Y 4 0 10 0 004 L 0 40 1 27 0 016 0 050 0 10 0 10 Notes 1...

Page 58: ...28 5 38 0 204 0 208 0 212 D1 5 13 5 23 5 33 0 202 0 206 0 210 E 5 18 5 28 5 38 0 204 0 208 0 212 E1 5 13 5 23 5 33 0 202 0 206 0 210 e 2 1 27 BSC 0 050 BSC H 7 70 7 90 8 10 0 303 0 311 0 319 L 0 50 0...

Page 59: ...YMBO L Min Nom Max Min Nom Max A 5 33 0 210 A1 0 38 0 015 A2 3 18 3 30 3 43 0 125 0 130 0 135 D 9 02 9 27 10 16 0 355 0 365 0 400 E 7 62 BSC 0 300 BSC E1 6 22 6 35 6 48 0 245 0 250 0 255 L 2 92 3 30 3...

Page 60: ...A 0 70 0 75 0 80 0 028 0 030 0 031 A1 0 00 0 02 0 05 0 000 0 001 0 002 b 0 35 0 40 0 48 0 014 0 016 0 019 C 0 20 REF 0 008 REF D 5 90 6 00 6 10 0 232 0 236 0 240 D2 3 35 3 40 3 45 0 132 0 134 0 136 E...

Page 61: ...ging Information please contact Winbond for the latest minimum and maximum specifications 2 BSC Basic lead spacing between centers 3 Dimensions D and E do not include mold flash protrusions and should...

Page 62: ...0 41 0 51 0 013 0 016 0 020 C 0 18 0 23 0 28 0 007 0 009 0 011 D 10 08 10 31 10 49 0 397 0 406 0 413 E 10 01 10 31 10 64 0 394 0 406 0 419 E1 7 39 7 49 7 59 0 291 0 295 0 299 e 2 1 27 BSC 0 050 BSC L...

Page 63: ...RoHS Compliant Halogen free TBBA Antimony Oxide free Sb2O3 P Green Package with Status Register Power Lock Down OTP enabled Notes 1a Only the 2 nd letter is used for the part marking WSON package type...

Page 64: ...an abbreviated 10 digit number PACKAGE TYPE DENSITY PRODUCT NUMBER TOP SIDE MARKING SN 2 SOIC 8 150mil 16M bit W25Q16BVSNIG W25Q16BVSNIP 25Q16BVNIG 25Q16BVNIP SS SOIC 8 208mil 16M bit W25Q16BVSSIG W25...

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