Wiener VM-DBA User Manual Download Page 7

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WIENER, Plein & Baus GmbH

www.wiener-d.com

2.4

VME Base Address

The VM-DBA base addresses for all modes (A16/A24/A32) are set via jumpers in the JP 4
array on the PCB. A jumper that is inserted in the left position (below “1”) counts as a 1 in
the base address bit pattern.

Mode

SN4

SN3

SN2

SN1

SN0

Default BADR

A16

A15

A14

A13

A12

A11 A10…0

0x7800

A24

A23

A22

A21

A20

A19 A18…0

0x78 0000

A32

A31

A30

A29

A28

A27 A26…0

0x7800 0000

Jumper

The factory

default the VM-DBA Base Address is SN0=SN1=SN2=SN3=1 and

as shown

in picture below.

BADR16 = 0x7800 (A16).
BADR24 = 0x78 0000 (A24).
BADR32 = 0x7800 0000 (A32).

Summary of Contents for VM-DBA

Page 1: ...uy your excess underutilized and idle equipment along with credit for buybacks and trade ins Custom engineering so your equipment works exactly as you specify Critical and expedited services Leasing R...

Page 2: ...WIENER Plein Baus GmbH 1 www wiener d com VM DBA User Manual Version 0 4...

Page 3: ...ny kind even if W Ie Ne R has been advises of the possibility of such damages arising from any defect or error in this manual or product Any use of the product which may influence health of human bein...

Page 4: ...VME Bus Analyzer Example for IRQ Interrupt triggered Event 19 5 VME USB Interface Architecture Description 21 5 1 VME USB Register Overview 21 5 2 USB Interface 22 5 3 Communicating with VM DBA 22 5...

Page 5: ...NSI IEEE STD 1014 IEC821 and IEC297 Dual user interface VME and USB LED indicators for all VME bus lines 32 data and 32 address lines interrupt lines IRQ1 7 IACK IACKIN Bus Clear Bus Busy BG1 BG3 and...

Page 6: ...or to the right of any other slave module 2 2 User interface The VM DBA bus display and bus analyzer is D32 and A16 A24 A32 VME slave module with additional USB 2 interface for communication and data...

Page 7: ...eft position below 1 counts as a 1 in the base address bit pattern Mode SN4 SN3 SN2 SN1 SN0 Default BADR A16 A15 A14 A13 A12 A11 A10 0 0x7800 A24 A23 A22 A21 A20 A19 A18 0 0x78 0000 A32 A31 A30 A29 A2...

Page 8: ...bus lines in three different ways direct latched and stretched In the direct or raw mode the LED s indicate the actual state of the lines while in latched mode the states of the lines are captured eit...

Page 9: ...BSY Utility bus SYSRESET SYSFAIL ACFAIL The state of power lines 5V 3 3V 12V and 12V and the SYSCLK line are displayed as is In addition to displaying the state of the VME bus lines VM DBA displays on...

Page 10: ...1 Connect VM DBA to the computer via USB and power up the VME crate 2 Run inf wizard exe from libusb win32 bin 1 2 6 0 this will identify all USB devices and should find the WIENER VM DBA among them 3...

Page 11: ...WIENER Plein Baus GmbH 10 www wiener d com 4 Ignore warning for unknown publisher...

Page 12: ...xxdbawin_install directory Change the destination folder in case needed and or click on the computer button to start the installation process After installation the program group program XXDBAWin shou...

Page 13: ...ions General setup and define the VM DBA interrupt settings IRQ setup The VME bus analyzer can be configured by defining the trigger conditions as well as time base and ranges When done the trigger ca...

Page 14: ...The IRQ number 1 to 7 and ID can be programmed 4 2 4 VME Bus Analyzer The VME bus analyzer allows to sample all VME bus lines as a function of time in order to analyze the sequence and timing of sign...

Page 15: ...OR NOT Valid AM By selecting a trigger condition the matching input fields will be displayed All inputs consist of a mask and actual values to match the condition shown in left to the input fields Ti...

Page 16: ...rs when both cursors are present A zoom to all 2048 time steps L shift the viewing window left by 100 time steps R shift the viewing window right by 100 time steps C Zooming by pressing keyboard keys...

Page 17: ...Waveforms showing the selected bus line waveforms With the mouse cursor it is possible to zoom curser in cross mode in by selecting a range between time lines When pointing outside this area double ar...

Page 18: ...condition As an example the bus analyzer should be triggered when reading or writing to an address in the range 0x7000 to 0x7ffff the AM value is ignored 1 Set the waveform acquisition trigger condit...

Page 19: ...off and the blue F4 LED will flash indicating that waveform data for read out are available 6 Click on Read Waves 7 Select the lines to be shown on the waveform plot This will open a new window Wavef...

Page 20: ...the red AQ LED will light up Run will change to Halt 5 Any interrupter IRQ 1 to 7 issued on the VME bus will trigger the bus analyzer and as a result AQ LED will go off and the blue F4 LED will flash...

Page 21: ...upt handler with IACK A 0 to A 3 are set by the master with the IRQ value The interrupt requestor places the vector ID on the data lines after receiving the IACKIN and asserts a DTACK Following the BC...

Page 22: ...ation A32 Address Space BADR32 Offset Offset WR Function RD Function 0 Firmware ID 0x4 Utility and test REG_A Utility and test REG_A 0x8 Utility and test REG_B Utility and test REG_B 0xC Utility and t...

Page 23: ...useful In communicating with VM DBA it is recommended to use the dynamic link library lixxusb dll designed originally for communicating with VM USB and CC USB controllers This library is proven to wor...

Page 24: ...n the command sequence is the Address Word representing here the VME address offset only The base address bits the 5 most significant bits in the full VME address are disregarded as it is presumed to...

Page 25: ...M DBA passes WRITE data to the registers or utility FIFO or returns the READ data from the registers or the waveform FIFOs to the USB interface WORD xxusb_stack_execute HANDLE hDevice LPDWORD lpData P...

Page 26: ...ndle to the XX USB device DataBuffer pointer to the dual use buffer when calling DataBuffer contains unsigned short stack data with first word serving as a placeholder upon successful return DataBuffe...

Page 27: ...ay of returned data when ReturnValue 0 Structure of OUT packets When the use of the libxxusb dynamic link library is not desired one may pack the stack data into OUT packets and bulk transfer bulk wri...

Page 28: ...bits of the waveform control word WFC in a way illustrated below When the waveform acquisition is active the latter words are stored in the Control FIFO at the base address of BADR32 0x300 WFC 7 6 5 4...

Page 29: ...r storage of the waveforms in the three waveform FIFOs in anticipation of the trigger signal The waveform setup parameters are stored in sections of the utility registers REGA REGB REGC and REGD struc...

Page 30: ...inuous waveform acquisition into circularly configured FIFO s is activated by setting TRSEL 0 It is then terminated at the detection of a valid trigger signal Here are the steps to be made to start a...

Page 31: ...the waveform storage relative to the trigger signal and the trigger selection code into REG_E at the base address 20 0x14 At this moment the red LED labeled AQ indicating continuous waveform acquisiti...

Page 32: ...3 Halt enabled mode when the LED display of VM DBA freezes at the detection of BERR requiring a reset to re activate the display 4 IRQ enabled mode where VM DBA generates an IRQ upon detecting a vali...

Page 33: ...3 1kHz internal clock TOUT Timeout code for pseudo DTACK generator 0 4 s 1 3 s 2 2 s 3 1 s IRQ ID IRQ level 1 7 IRQVECT 8 bit identifier Interrupt Software Trigger Register at the base address of 32...

Page 34: ...Sequence The unlock sequence consists of two consecutive A24 D32 write commands to the address offset of 0x55554 of data words first 0x55555555 and then 0xAAAAAAAA It is valid only for the operation...

Page 35: ...he unlock sequence write 0xAAAAAAAA to the A24 address offset of 0x55554 same as that of the unlock sequence The last of the above steps triggers the bulk erase cycle that is wholly controlled by the...

Page 36: ...32 bit data word composed of the consecutive 4 bytes of the XILINX configuration bit file with little endian mapping DataWord64 StartAddress2 StartAddress1 256 the SPI address is in bytes DataWords S...

Page 37: ...on Access The RORA mode requires the VME controller to reset IRQ by writing 2 into Software Interrupt Register at A16 base address of 32 0x20 When configured for ROAC mode VM DBA resets IRQ upon dete...

Page 38: ...site 1 Check Base address of VM DBA following example shown for factory default Base address 0x78000000 Note The Base address is only needed when updating the firmware via VME 2 Check current Firmwar...

Page 39: ...h Operations tab and see right side VM BA SPI Select Main SPI memory location For upgrade via VME type in value for A32 Base Address 7800 0000 for factory default This value is not used and can be ign...

Page 40: ...aus GmbH 39 www wiener d com When erasing the old firmware and programming flashing LED s on the VM DBA will indicate the upgrade 4 Reboot VM DBA Reboot the VM DBA by clicking on Reboot or power cycle...

Page 41: ...BLT A32 WRITE 4 0000 5 0004 address offset for Reg_a 6 0000 7 5678 data low half word 8 1234 data high half word Note xxusb_stack_execute returns 1 on success B Stack of two simple A32 Write commands...

Page 42: ...n 6 0000 7 0000 low half word of the address offset for the utility FIFO 8 0800 high half word of the address offset for the utility FIFO 9 249609 half words of the data to be written Note xxusb_longs...

Page 43: ...uipment Have surplus equipment taking up shelf space We ll give it a new home Learn more Visit us at artisantg com for more info on price quotes drivers technical specifications manuals and documentat...

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