WIENER, Plein & Baus GmbH
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Subsequently, one may read out the contents of the three waveform FIFOs via a sequence of
32 32-bit block read commands, terminated by the BERR signal indicating that the particular
FIFO has been emptied.
5.5
Setup of the waveform acquisition
The setup of the waveform acquisition entails (i) selection of the sampling frequency of
either 100 MHz or 200 MHz, (ii) defining of the trigger signal for the commencement of the
waveform storage cycle, (iii) defining of the start time step with respect to the trigger signal,
and (iv) activation of the continuous circular storage of the waveforms in the three waveform
FIFOs, in anticipation of the trigger signal.
The waveform setup parameters are stored in sections of the utility registers REGA, REGB,
REGC and REGD structured as shown in tables below.
REG_A at the base address of 4
Bits
31 - 1
0
Function
TRA
WFFR
TRA – Trigger Reference Address
WFFR – Waveform FIFOs Reset when set. Must be reset for FIFOs to be active.
REG_B at the base address of 8
Bits
5, 4
0
Function
MSPS
RAWDIS
MSPS – Sampling frequency code
00 – 100 Msps
01 – 200 Msps
RAWDIS – when 1, front panel LEDs display live state of the VME bus lines (no latching).
REG_C at the base address of 12 (0xC)
Bits
31 - 1
Function
AMASK
AMASK – Active trigger address bit
s.
REG_D at the base address of 16 (0x10)
Bits
13 - 8
6 - 0
Function
TRAM
AMMASK/IRQMASK
