Wiener AVM16, User Manual

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Each of the ADC channel is equipped with a symetrizing amplifier, anti-aliasing filter and an
individual 12-bit Analog-to-Digital converter running at 160 Msamples/s.
After conversion, the digital data is passed to 4 FPGA circuits providing buffers for data retention
and a feature extraction logic. One Spartan-3 FPGA from Xilinx is used for a block of four
channel keeping a history of 1024 samples for each channel in it’s internal registers. Feature
extraction algorithms are used for calculate important parameters of the input pulses, such as
amplitude, time, intergrals and many others, which allows for minimizing of the readout data
volume and thus increasing the readout speed. The user may still choose to read a full set of
samples, recorded in the buffer or read s ubset of those samples within specified time boundaries,
being in relation to the trigger.
After a trigger request from a Data acquisition system, the stored and/or extracted data is passed to
a control FPGA chip via four Data Local Busses and then transferred over a VME bus or a VXS
backplane P2P connection fabric.
In multichannel systems, where a common time base is required, a global clock and
synchronization signals are provided over a front panel connector or over a non-legacy user VME
connector pins. The clocking and synchronization circuitry allows for choosing of the clock
source.