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5.6.7

Absolute hex

Translation of absolute column into hex.

5.6.8

Shows the relationship between the data computed by the FPGA and the raw data. This is to verify
if the FPGA correctly inferred timing and values of maxima and minima as well as integrals,
averages and zero crossing times.

Extracted Data

Meaning

370770

mean level

370779

mean of 4 preceeding

206BBB

Integral

37077A

mean of 4 trailing

300028

trigger window start time

310770

mean level 1

32000C

min. time 1

33FFEB

min. lev. 1

34FFF0

max. time 1

3502F6

max. lev. 1

364005

Extracted zero crossing 1

202D66

First integral

32FFAC

min. time 2

330168

min. lev. 2

34FF88

max. time 2

350366

max. lev. 2

363F96

Extracted zero crossing 2

203E55

Second integral

Summary of Contents for AVM16

Page 1: ...1 16 channel ADC 160 MHz with features extraction User s Manual W Ie Ne R AVM16 AVX16...

Page 2: ......

Page 3: ...of any kind even if W Ie Ne R has been advises of the possibility of such damages arising from any defect or error in this manual or product Any use of the product which may influence health of human...

Page 4: ...VME addressing 13 5 4 Software registers 14 5 4 1 Overview of registers 14 5 4 2 First group of registers control FPGA 15 5 4 3 Registers that are sent to all ADC FPGAs too 18 5 4 4 Registers that ar...

Page 5: ...triggering mode Integration time window relative to trigger time or to pulse arrival time Time resolution 1 5625 ns interpolated signal t0 Feature extraction Amplitude Integral Time of arrival Multipl...

Page 6: ...ut is present on all boards AMP ADC AMP ADC AMP ADC AMP ADC Feature extraction FPGA AMP ADC AMP ADC AMP ADC AMP ADC Feature extraction FPGA AMP ADC AMP ADC AMP ADC AMP ADC Feature extraction FPGA AMP...

Page 7: ...y others which allows for minimizing of the readout data volume and thus increasing the readout speed The user may still choose to read a full set of samples recorded in the buffer or read s ubset of...

Page 8: ...s FWHM The anti aliasing filter can be customized or removed by the manufacturer or by an authorized person see figure 2 An on board pulse generator provides test pulses for every channel R1 51 1 2 3...

Page 9: ...els overcomes the trigger level set in the register 0x110 with reference to the actual baseline all non inhibited channels are read out The trigger condition is ADC_VALUE BASE_LINE TRIGGER_LEVEL and i...

Page 10: ...10 5 Technical description of AVM 16 AVX 16 Figure 6 shows location of key connectors user may interface to Figure 4 The AVM 16 AVX 16 Printed circuit board...

Page 11: ...ogic is implemented on 4 SPARTAN 3 FPGAs each one serving 4 ADCs and one VIRTEX 5 Control FPGA as interface between the 4 ADC FPGAs and the VME Bus The Control FPGA is VIRTEX 5 XC5VLX50T The FPGAs ser...

Page 12: ...a signal distributed on dedicated user lines of the VME bus present on request Data from within the boundaries of the window control are transferred to the Waveform Feature Extraction section and if...

Page 13: ...Pi time for the first non zero value Pz pulse start time calculated from slope crossing the pedestal value Pa signal amplitude Pq signal integral charge PPi minimum value before pileup PPz pileup pul...

Page 14: ...16 channels and address the corresponding ADC FPGA The range of the fourth group is foreseen for access to the readout data in single mor in block transfer mode The meaning and functions of the intern...

Page 15: ...f integral of the signal analyzing 0x12C aclk_shift step phase shift factor status 0x130 0x13C lb_test 4 rw test register for the local bus to 4 SPARTAN s reserved 0x200 0x23C base_line 16 auto base l...

Page 16: ...DAVAL Data available compared to the DVAL bit this bit is already set when the first word is present in a FIFO DVAL is only set when all data were written in the FIFOs and thus the dlength register i...

Page 17: ...this way it is possible to insert pauses after commands tp_dac 0x01C With bit 3 in act register it is possible to generate a test pulse through a DAC The height of the test pulse is set by means of t...

Page 18: ...he corresponding ADC FPGA sends the trigger time to VIRTEX 5 which forwards it to all ADC FPGAs in order to start the read out 3 VERBOSE When this bit is set the pairs of values for minima and maxima...

Page 19: ...the supplementary integral window in the search main window The time unit is the ADC sample rate 6 25 ns The value must be bigger or equal 4 in order for the 4 values leading the window to be present...

Page 20: ...5 4 4 Registers that are individually available for every channel base_line 16 0x200 to 0x23C In the FPGA the ADC mean value for each channel is computed continuously ADC input test pulses are exclude...

Page 21: ...llows according to the following list for the first channel channel 0 Label 0x30 window start time first value referred to the trigger time that is the time reference and corresponds to t 0 or window...

Page 22: ...and baseline for pile up peaks the last minimum is used instead of the baseline using 1 2 and 4 bins The choosen value corresponds to the biggest X for which h Y h where h is the peak heigth From the...

Page 23: ...23 Figure 9 upper picture graphical representation of the extracted features Lower picture input parameters with details on SW_INT_LENGTH...

Page 24: ...rlier by the user defined parameter SW_INTLENGTH Note all labels refer to channel 0 In order to decode labels for other channels following formula applies Label for channel 0 e g 0x37 4 0x10 channel n...

Page 25: ...lute abs Hex Register Value In 1 5625ns units Used in calculations 1 78E 28 30 028 2 770 24 3 762 20 4 78B 1C 78B 1931 27 001B Mean of 5 761 18 761 1889 15 FFFFFFFFF1 4 preceeding 6 77C 14 77C 1916 12...

Page 26: ...2421 517 0205 25 994 FC8 994 2452 548 0224 26 94F FC4 94F 2383 479 01DF 27 94D FC0 94D 2381 477 01DD 28 945 FBC 945 2373 469 01D5 29 904 FB8 904 2308 404 0194 30 929 FB4 929 2345 441 01B9 31 901 FB0...

Page 27: ...BB 2235 331 014B 58 862 862 2146 242 00F2 59 85D 85D 2141 237 00ED 60 855 855 2133 229 00E5 61 802 802 2050 146 0092 62 81A 81A 2074 170 00AA 63 7E5 7E5 2021 117 0075 64 7BB 7BB 1979 75 004B 65 7EF 7E...

Page 28: ...raw data value was sampled This values were not read out from the ADC they were added manually basing on the window start time value The window start time is part of the data analysis and can be read...

Page 29: ...integrals averages and zero crossing times Extracted Data Meaning 370770 mean level 370779 mean of 4 preceeding 206BBB Integral 37077A mean of 4 trailing 300028 trigger window start time 310770 mean...

Page 30: ...30...

Page 31: ...User s Manual AVM16 AVX16 W Ie Ne R Plein Baus GmbH September 10 31...

Page 32: ......

Page 33: ...User s Manual AVM16 AVX16 W Ie Ne R Plein Baus GmbH September 10 33...

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