Wiener AVM16, User Manual

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16
com_ids 0x008 - In this register there are three identifiers for communication.
Bit Meaning
2:0
Interrupt Request Level (1 to 6) an interrupt is issued
if data are available. A 0 disables the interrupt
7:3
Null
15:8
Interrupt Vector, it is transmitted on Interrupt
Acknowledge in order to identify the interrupt
19:16 Data recognition. These 4 bits are written in bit 31:28
of data, so that it is possible to map data to a
specific module (see data format)
31:20 Null
state 0x010 - General Status Register
Bit Name Meaning
0 DVAL
Data valid: data are ready in VIRTEX-5. If this
bit is set an interrupt is triggered in case the
programmed Interrupt Level is not zero. Only
when all data have been read, more data (that
may have been triggered meanwhile) from the ADC
FPGAs can be loaded. The number of bytes is in
dlength register.
1 DAVAL
Data available, compared to the DVAL bit, this
bit is already set when the first word is
present in a FIFO. DVAL is only set when all
data were written in the FIFOs and thus the
dlength register is valid.
2 ROBUSY
This bit is set when a trigger is fired,
blocking further triggers. It is only reset when
all data in the FIFOs are read out. As long as
old data are present in a FIFO, this bit remains
set. This means that the readout data still
cannot be transmitted from the ADC Spartan FIFOs
to the VIRTEX-5 FIFOs.
3
Null
7:4 LTSRC
Level Trigger Source, indicates which ADC
channel fired the last level trigger.
31:8 Null
dlength 0x014 - This register indicates how many bytes are present in the FIFOs (in total).
For each ADC SPARTAN-3 is a FIFO available. By readout FIFO 0 (channel 0 to
3) has the higher priority. A FIFO can store 32 kB (8k values).
jtag_csr 0x030 - JTAG control/status Register
Bit Name Write Read
0 TDI Data Input to the first JTAG device
1 TMS Mode Select
2
TCK JTAG Clock, must be zero when AUTO_CLK is used