Wersi DX 400, Assembly Manual

Page: 44 / 68

AM 334-01-502
44
II. Control Panels
The following pages contain schematic diagrams of the
control panel PC boards CB. . . which include slide controls,
switches and drawbars, and key contact boards KD. . .
which decode and route inputs from the key. boards and
pedals.
1. CB Boards
The control panel PC boards CB. . . work on a principle of
continuous polling of the control switches by the CPU on
master processor board MST 3, On, for example, CB 21
(Fig. 21), the parallel-out serial shift registers lC2, 7, 8, 9, 1
and 10 are clocked by peripheral output line pulses from the
CPU. The register outputs continuously and rapidly poll the
status of the control panel function switches.
A momentary switch closure results in a sense pulse, which
is applied to the CPU's data bus. This sense pulse occupies a
specific time slot in the CPU's sequence pro-gram and
instructs the CPU to initiate the function for that time slot.
The CPU, in turn, senses a serial data code to the appropriate
register set, designating the LED(s) to illuminate on the
panel switches.
2. Key Contact Boards
KD la (Fig. 25a)
The dynamic perception of keyboard action is possible
through the principle of time measurement. To accomplish
this, the spring contact for each key performs a normally
closed-to-normally open switching function. The. time from
the opening of the normally closed (rest) state of the contact
to the closing of the normally open (working) state is
measured electronically.
Every eight contacts are assigned to a matrix address. For
five octaves (61 keys), eight matrix addresses are necessary.
These matrix addresses are sequentially switched to ground
so that the statuses of the 61 contacts can be polled. The
speed at which the polling takes place is determined by the
setting of the code switch S1. (Note: "Reset" must be
pressed after any change in the code switch). If the polling
rate is very short, a key must be pressed quickly to achieve
maximum dynamic value.
The dynamic value is transferred to one of two 2-byte
parallel ports. The first port, 1C5, transfers data that
determines pitch values and whether a note should be turned
on or off. The second port transfers data determining the
dynamic value. When the dynamic value is entered, lC8a, a
flip-flop, toggles, releasing an FIRQ (interrupt request) shot
to the CPU.
During the port read cycle, the key (1C5) is read first
and the FIRQ appears in its highest bit (on IC4/pin
13). This tells the CPU which manual the FIRQ is for.
When this is determined, the dynamic value for that
manual is read and the flip-flop resets; In addition, the
FIRQ can be cancelled by the other flip-flop, IC8b.
1C7 handles the address decoding.
KD lb (Fig. 25b)
The circuitry of this board polls the pedal switching matrices
to determine pedal switch closures. Specific matrix schemes
are used according to organ type and these are selected by
jumpers Ju7 thru 14.
KD2/KD4
These extend the key contact matrices according to the
number of octaves (KD4 for 4 octaves, KD2 for 5 octaves).