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VMICPCI-7755 Product Manual

Timer 4 IRQ Clear (T4IC)

The Timer 4 IRQ Clear (T4IC) register is used to clear an interrupt caused by Timer 4.
Writing to this register, located at offset 0x3C from the address in BAR1, causes the
interrupt from Timer 4 to be cleared.  This can also be done by writing a “0” to the
appropriate “Timer x Caused IRQ” field of the timer Control Status Register (CSR1).
This register is write only and the data written is irrelevant.

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Summary of Contents for VMICPCI-7755

Page 1: ...South Memorial Parkway Huntsville Alabama 35803 3308 USA 256 880 0444 w 800 322 3616 w Fax 256 882 0859 VMICPCI 7755 Intel Pentium III Processor with 133MHz Front Side Bus Product Manual 500 657755 000 Rev E ...

Page 2: ......

Page 3: ...VMIC s Standard Conditions of Sale AMXbus BITMODULE COSMODULE DMAbus IOMax IOWorks Foundation IOWorks Manager IOWorks Server MAGICWARE MEGAMODULE PLC ACCELERATOR ACCELERATION Quick Link RTnet Soft Logic Link SRTbus TESTCAL The Next Generation PLC The PLC Connection TURBOMODULE UCLIO UIOD UPLC Visual Soft Logic Control ler VMEaccess VMEbus Access VMEmanager VMEmonitor VMEnet VMEnet II and VMEprobe ...

Page 4: ......

Page 5: ... 25 Unpacking Procedures 25 Hardware Setup 26 Power Requirements 29 Installation 30 BIOS Setup 31 Front Rear Panel Connectors 33 LED Definition 34 Chapter 2 Standard Features 37 CPU Socket 38 Physical Memory 38 I O Port Map 39 Interrupts 41 System Interrupts 41 PCI Interrupts 44 PCI Device Interrupt Map 45 Integrated Peripherals 48 Ethernet Controller 49 10BaseT 49 100BaseTx 49 ...

Page 6: ...RLCR12 57 Timer 3 Load Count Register TMRLCR3 57 Timer 4 Load Count Register TMRLCR4 58 Timer 1 2 Current Count Register TMRCCR12 58 Timer 3 Current Count Register TMRCCR3 58 Timer 4 Current Count Register TMRCCR4 59 Timer 1 IRQ Clear T1IC 59 Timer 2 IRQ Clear T12C 59 Timer 3 IRQ Clear T3IC 59 Timer 4 IRQ Clear T4IC 60 Watchdog Timer 61 General 61 WDT Control Status Register WCSR 61 WDT Keepalive ...

Page 7: ... Setup 87 Microsoft Windows 98 SE Software Driver Installation 88 Intel 815 Chipset Software Installation 88 Ultra ATA Storage Driver Installation 89 Video Driver Installation 89 Create an Ethernet Adapter Driver Disk 89 Ethernet Adapter Driver Installation 89 Microsoft Windows NT 4 0 Software Driver Installation 91 Ultra ATA Storage Driver Installation 91 Video Driver Installation 91 Create an Et...

Page 8: ...02 Com Port Address 102 Baud Rate 102 Console Type 102 Flow Control 103 Console Connection 103 Continue C R After POST 103 System Memory 103 Extended Memory 103 Extended Memory 103 Advanced Menu 104 Advanced Chipset Control 104 Video Boot Type 105 Enable Memory Gap 105 Cache Memory 105 I O Device Configuration 106 Reset Configuration Data 106 Installed O S 106 Large Disk Access Mode 106 LBA Assist...

Page 9: ...rd Changes 111 Save Changes 111 Appendix D LANWorks BIOS 113 Boot Menus 114 First Boot Menu 114 Boot Menu 114 BIOS Features Setup 116 RPL 116 TCP IP 116 Netware 117 PXE 117 Appendix E Sample C Software 119 Directory 21154 119 Directory fpga 119 Directory i2c 120 Directory include 120 Directory max1617 120 Directory support 120 Directory vlm 120 Appendix F Serial ROM for the 21154 121 VMICPCI 7755 ...

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Page 11: ...ctions for the PC Interrupt Logic Controller 46 Figure 3 1 Typical System Configuration 64 Figure A 1 J1 Connector and Pinout 72 Figure A 2 J2 Connector and Pinout 73 Figure A 3 J3 Connector and Pinout 74 Figure A 4 J4 Connector optional and Pinout 75 Figure A 5 J5 Connector and Pinout 76 Figure A 6 Ethernet Connector and Pinout 77 Figure A 7 Video Connector and Pinout 78 Figure A 8 Keyboard Mouse...

Page 12: ...12 ...

Page 13: ... 41 Table 2 3 PC Interrupt Vector Table 42 Table 2 4 PCI Device Interrupt Mapping by the BIOS 45 Table 2 5 NMI Register Bit Descriptions 47 Table 2 6 Supported Graphics Video Resolutions 50 Table 3 1 I2C bus Through J1 53 Table 3 2 PCI Configuration Space Registers 54 Table A 1 Keyboard Mouse Y Splitter Cable 79 Table A 2 PMC 1 J11 PMC 2 J15 Connector Pinout 80 Table A 3 PMC 1 J10 PMC 2 J14 Connec...

Page 14: ...14 ...

Page 15: ...stems such as Up to 512MB PC133 SDRAM Built in SVGA support with 4 Mbytes DRAM display cache Built in 10 100 Mbit Ethernet IDE drive support Floppy drive support Two RS232 serial ports USB port Real Time clock calendar Front panel reset switch Miniature speaker Keyboard Mouse port The 815E chipset allows the VMICPCI 7755 to provide enhanced features such as 133MHz front side bus support and ATA 10...

Page 16: ... I O routing to the J3 J5 connectors of the CompactPCI bus The VMICPCI 7755 is capable of executing many of today s embedded operating systems such as VxWorks QNX Solaris LynxOS and Microsoft s embedded Windows NT The embedded features of the VMICPCI 7755 are described in Chapter 3 of this manual The VMICPCI 7755 is suitable for use in applications ranging from telecommunications simulation instru...

Page 17: ...ilizing a new Advanced Hub Architecture AHA The AHA allows for increased system performance by separating many high bandwidth I O accesses like IDE or USB devices from PCI accesses relieving bottlenecks on the PCI bus Furthermore the 815E chipset brings new levels of integration to motherboard chipsets and provides additional features like ATA 100 support over other chipsets ...

Page 18: ...ntroller Hub GMCH SDRAM Advanced Hub Architecture AHA Bus I O Controller Hub Intel 82801BA ICH2 CompactPCI CompactPCI CompactPCI Firmware Hub Intel 82802AB SVGA LPC FWH Bus CompactPCI USB Ultra DMA CompactPCI IDE Expansion 1 PMC Expansion 2 5V 5V PCI Bus 32 bit PCI Interface FPGA Timers Watchdog Timer Ethernet Controller Intel 82559ER LAN 10BaseT 100BaseTX Embedded PCI Bridge Intel 21154 32 Kbyte ...

Page 19: ...ions Chapter 4 Maintenance provides information relative to the care and maintenance of the unit Appendix A Connector Pinouts illustrates and defines the connectors included in the unit s I O ports Appendix B System Driver Software provides details for installing drivers under Windows 98 SE and Windows NT Appendix C Phoenix BIOS describes the menus and options associated with the Phoenix system BI...

Page 20: ...nterest Group P O Box 14070 Portland OR 97214 800 433 5177 U S 503 797 4207 International 503 234 6762 FAX PC87366 128 Pin LPC Super I O with System Hardware Monitoring MIDI and Game Ports National Semiconductor 2900 Semiconductor Dr P O Box 58090 Santa Clara CA 95052 8090 800 272 9959 800 737 7018 FAX CMC Specification P1386 Draft 2 0 from IEEE Standards Department Copyrights and Permissions 445 ...

Page 21: ...224 1239 FAX www picmg org The following is useful information related to remote Ethernet booting of the VMICPCI 7755 Microsoft Windows NT Server Resource Kit Microsoft Corporation ISBN 1 57231 344 7 www microsoft com The following is useful information related to the operation of the I2 C controllers The I2 C Specification version 2 0 Philips Semiconductor 811 East Arques Ave Sunnyvale CA 94088 3...

Page 22: ...nment constitutes a definite safety hazard Keep Away from Live Circuits Operating personnel must not remove product covers Component replacement and internal adjustments must be made by qualified maintenance personnel Do not replace components with power cable connected Under certain conditions dangerous voltages may exist even with the power cable removed To avoid injuries always disconnect power...

Page 23: ...azard It calls attention to a procedure practice or condition which if not correctly performed or adhered to could result in injury or death to personnel CAUTION denotes a hazard It calls attention to an operating procedure practice or condition which if not correctly performed or adhered to could result in damage to or destruction of part or all of the system NOTE denotes important information It...

Page 24: ...VMICPCI 7755 Product Manual 24 ...

Page 25: ...ed printed circuit board s heat damage and other visible contamination All claims arising from shipping damage should be filed with the carrier and a complete report sent to VMIC Customer Service along with a request for advice concerning the disposition of the damaged item s CAUTION Some of the components assembled on VMIC s products may be sensitive to electrostatic discharge and damage may occu...

Page 26: ...are illustrated in Figure 1 1 on page 27 The definitions of the CPU board jumpers and connectors are included in Table 1 1 through Table 1 4 Please note that the VMICPCI 7755 offers two PMC sites designated PMC 1 and PMC 2 as shown in Figure 1 1 on page 27 CAUTION All jumpers marked User Configurable in the following tables may be changed or modified by the user All jumpers marked factory configur...

Page 27: ...27 Hardware Setup 1 Figure 1 1 VMICPCI 7755 PMC and Jumper Locations PMC 1 PMC 2 ...

Page 28: ...pins 2 3 3 Wait approximately 5 seconds 4 Move jumper shunt on E1 back to pins 1 2 5 Power up the unit When power is reapplied to the unit the CMOS password will have been cleared Table 1 1 CPU Board Connectors Connector Function J7 Mouse Keyboard J6 Ethernet J5 USB COM1 IDE J3 COM2 Floppy P3 Video E30 E36 E40 Factory Reserved Do Not Use E38 ITP E37 I2 C Header E34 Fan J8 J10 J11 PMC Slot 1 J12 J1...

Page 29: ...nt provided on the 5V supply is 1 5A per PMC site The maximum current provided on the 3 3V supply is 1 5A per PMC site The 12V and 12V supplies are provided to both PMC sites and to the rear transition board such as the ACC 0577 board The total 12v or 12v current provided to the VMICPCI 7755 as indicated above the two PMC sites and the rear transition board must not exceed 1A each in accordance wi...

Page 30: ...nto a CompactPCI chassis system controller slot While ensuring that the board is properly aligned and oriented in the supporting board guides slide the board smoothly forward against the mating connector Use the ejector handles to firmly seat the board 4 All needed peripherals can be accessed from the front panel and the rear I O VMIACC 0577 Rear Transition utility board Each connector is clearly ...

Page 31: ...backed memory chip and are collectively referred to as the board s CMOS Configuration The CMOS configuration controls many details concerning the behavior of the hardware from the moment power is applied The VMICPCI 7755 is shipped from the factory with hard drive type configuration set to AUTO in the CMOS Details of the VMICPCI 7755 BIOS setup program are included in Appendix C ...

Page 32: ...32 1 VMICPCI 7755 Product Manual Figure 1 2 Installing a PMC Card on the VMICPCI 7755 Third Party PMC Expansion Board Standoff ...

Page 33: ...ouse and keyboard connector S Status LEDs The VMICPCI 7755 provides rear I O support for the following PMC I O for both expansion sites IDE drive floppy drive two serial ports and one USB port These signals are accessed by the use of a rear panel transition board such as the VMIACC 0577 which terminate into industry standard connectors The front panel connectors including connector pinouts and ori...

Page 34: ... LED 3 Power Indicates when power is applied to the board Green LED LED 4 Reset Lights during reset condition Red LED LAN Active Indicates the Ethernet is active yellow LED 10 100BaseTx Indicates whether 10BaseT or 100BaseTx mode Yellow LED indicates 10BaseT and Green LED indicates 100BaseTx Figure 1 3 Front Panel LED Positions RST CompactPCI M K L A N S V G A TM S M E Z Z A N I N E C A R D M E Z ...

Page 35: ...n Reset LAN 10BaseT 100BaseT LED alternates Yellow Green and Red Reset LED is illuminated CPU Not Present Green Power LED is illuminated and the Red Reset LED flashes at a rapid rate Normal Operation LED 1 Off Boot Completed LED 2 Off or Flashing IDE Activity LED 3 On Power is up and good LED 4 Off Out of Reset VRM Failure Green Power LED is off and the red Reset LED flashes at a rapid rate Thrott...

Page 36: ...36 1 VMICPCI 7755 Product Manual ...

Page 37: ...ustry standard desktop systems The VMICPCI 7755 therefore retains industry standard memory and I O maps along with a standard interrupt architecture The integrated peripherals described in this section such as serial ports USB ports IDE drives floppy drives video controller and Ethernet controller are all memory mapped the same as similarly equipped desktop systems ensuring compatibility with mode...

Page 38: ... board DRAM is dual ported to the CompactPCI bus through the PCI to PCI bridge and is addressable by the local processor NOTE When using the Configure utility of VMIC s IOWorks Access with Windows NT 4 0 to configure RAM do not request more than 25 percent of the physical RAM Exceeding the 25 percent limit may result in a known Windows NT bug that causes unpredictable behavior during the Windows N...

Page 39: ...orts hard and floppy drive controllers video system real time clock system timers and interrupt controllers are addressed in this region of I O space The BIOS initializes and configures all these registers properly adjusting these I O ports directly is not normally necessary The assigned and user available I O addresses are summarized in the I O Address Map Table 2 1 Table 2 1 VMICPCI 7755 I O Add...

Page 40: ...2 Serial I O 16550 Compatible 2FF 36F 113 Reserved 370 377 8 Super I O Chip Secondary Floppy Disk Controller 378 37F 8 Super I O Chip LPT1 Parallel I O 380 3E7 108 Reserved 3E8 3EE 7 UART COM3 Serial I O 3F0 3F7 8 Super I O Chip Primary Floppy Disk Controller 3F8 3FE 7 Super I O Chip COM1 Serial I O 16550 Compatible 3FF 4FF 256 Reserved 500 CFF 2048 Reserved While these I O ports are reserved for ...

Page 41: ... from IRQ0 to IRQ7 at the PIC The IBM PC AT computer added eight more IRQx lines numbered IRQ8 to IRQ15 by cascading a second slave PIC into the original master PIC IRQ2 at the master PIC was committed as the cascade input from the slave PIC This architecture is represented in Figure 2 1 on page 46 To maintain backward compatibility with PC XT systems IBM chose to use the new IRQ9 input on the sla...

Page 42: ...vailable 08 8 IRQ0 Timer Tick Double Exception Detected 09 9 IRQ1 Keyboard Input Coprocessor Segment Overrun 0A 10 IRQ2 BIOS Reserved Invalid Task State Segment 0B 11 IRQ3 COM2 Serial I O Segment Not Present 0C 12 IRQ4 COM1 Serial I O Stack Segment Overrun 0D 13 IRQ5 Unassigned Unassigned 0E 14 IRQ6 Floppy Disk Controller Page Fault 0F 15 IRQ7 Unassigned Unassigned 10 16 BIOS Video I O Coprocessor...

Page 43: ... 35 DOS Control Break Handler Same as Real Mode 24 36 DOS Critical Error Handler Same as Real Mode 25 37 DOS Absolute Disk Read Same as Real Mode 26 38 DOS Absolute Disk Write Same as Real Mode 27 39 DOS Program Terminate Stay Resident Same as Real Mode 28 40 DOS Keyboard Idle Loop Same as Real Mode 29 41 DOS CON Dev Raw Output Same as Real Mode 2A 42 DOS 3 x Network Comm Same as Real Mode 2B 43 D...

Page 44: ...x lines The Interrupt Pin register defines which INTx line the function uses to request an interrupt If a device implements a single INTx line it is called INTA if it implements two lines they are called INTA and INTB and so forth For a multifunction device all functions may use the same INTx line or each may have its own up to a maximum of four functions or any combination thereof A single functi...

Page 45: ...R ID DEVICE ID CPU ADDRESS MAP ID SELECT PCI IRQ Arbitration Request Line PCI to PCI Bridge Intel 21154 0x1011 0x0026 AD26 N A REQ0 Timer SRAM FPGA VMIC Proprietary 0x114A 0x6504 AD20 INTD N A PMC1 N A N A N A AD31 INTC REQ3 PMC2 N A N A N A AD30 INTA REQ2 Ethernet Controller Intel 82559ER 0x8086 0x1209 AD22 INTE REQ1 PCI Host Bridge GMCH 0x8086 0x1130 N A N A N A VGA Controller GMCH 0x8086 0x1132...

Page 46: ...BY BIOS PMC Site 1 BRIDGE C P C b u s Timer Keybd Com 2 Com 1 Unused Floppy Control Interrupt 8 15 Unused Real Tm Clock Mouse Math AT Flash Hard Drv NA NA Coproc PIRQA PIRQB PIRQC PIRQD IRQ2 INTB INTC INTD MAPPER 8259 SLAVE PORTS 0A0 0A1 I O Controller Hub ICH2 INT Drive I Bus PCI to PCI INTA PMC Site 2 INTB INTC INTD Ethernet INT PIRQE IRQ8 IRQ9 IRQ10 IRQ12 IRQ11 IRQ13 IRQ14 IRQ15 FPGA INT Timers...

Page 47: ...he corresponding enable disable bit to 1 The NMI Enable and Real Time Clock register can mask the NMI signal and disable enable all NMI sources Table 2 5 NMI Register Bit Descriptions Status Control Register I O Address 061 Read Write Read Only Bit 7 SERR NMI Source Status Read Only This bit is set to 1 if a system board agent detects a system board error It then asserts the PCI SERR line To reset...

Page 48: ...Hub ICH2 chip The IDE interface supports two channels known as the primary and secondary channels The secondary channel is routed on board to the optional compact flash socket The primary channel is routed out the CompactPCI backplane to a transition utility board which terminates into a standard 40 pin header This channel can support two drives a master and slave The IDE interface on the VMICPCI ...

Page 49: ... the 10BaseT standard uses unshielded twisted pair cables providing an economical solution to networking by allowing the use of existing telephone wiring and connectors The RJ 45 connector is used with the 10BaseT standard 10BaseT has a maximum length of 100 meters 100BaseTx The VMICPCI 7755 also supports the 100BaseTx Ethernet A network based on a 100BaseTx standard uses unshielded twisted pair c...

Page 50: ...tion and extended video modes Table 2 6 shows the graphics video modes supported by the GMCH video controller Not all SVGA monitors support resolutions and refresh rates beyond 640 x 480 at 85 Hz Do not attempt to drive a monitor to a resolution or refresh rate beyond its capability Table 2 6 Supported Graphics Video Resolutions Screen Resolution Maximum Colors Maximum Refresh Rates Hz 640 x 480 1...

Page 51: ...with a programmable Watchdog Timer for synchronizing and controlling multiple events in embedded applications The VMICPCI 7755 also provides a bootable Flash Disk system and 32 Kbyte of non volatile SRAM Also the VMICPCI 7755 supports an embedded intelligent CompactPCI bridge to allow compatibility with the most demanding CompactPCI applications These features make the unit ideal for embedded appl...

Page 52: ...multiple transactions in either direction 256 byte of posted write data and address buffering in each direction 256 byte of read data buffering in each direction Four delayed transaction entries in each direction Configuration Register and Control Status Registers CSRs Two sets of standard PCI configuration registers corresponding to the local and CompactPCI interfaces accessible from either the l...

Page 53: ...n the I2 C signals This gives the system the flexibility of setting the pull up voltage level of the I2 C bus with a single pair of pull up resisters located on the system controller backplane or any other connected system device The controller can issue interrupts to the VMICPCI 7755 when handshaking on the I2 C bus When the I2 C bus controller drives the interrupt active software must service an...

Page 54: ...r ID fields indicate VMIC s PICMG assigned Vender ID 114A The Subsystem ID field indicates the model number of the product 7755 Table 3 2 PCI Configuration Space Registers 31 16 15 00 Register Address Device ID 6504 Vendor ID 114A 00h Status Command 04h Class Code Revision ID 08h BIST Header Type Latency Timer Cache Line Size 0Ch PCI Base Address 0 for Memory Mapped 32kb NVRAM 10h PCI Base Address...

Page 55: ...ontrol Status Register 1 TCSR1 The timers are controlled and monitored via the Timer Control Status Register 1 TCSR1 located at offset 0x00 from the address in BAR1 The mapping of the bits in this register are as follows Field Bits Read or Write Timer 1 Caused IRQ TCSR1 0 R W Timer 1 Enable TCSR1 1 R W Timer 1 IRQ Enable TCSR1 2 R W Timer 1 Clock Select TCSR1 4 3 R W Timer 2 Caused IRQ TCSR1 8 R W...

Page 56: ... also clear the interrupt When clearing the interrupt using the Timer x Caused IRQ fields note that it is very important to ensure that a proper bit mask is used so that other register settings are not affected The preferred method for clearing interrupts is to use the Timer x IRQ Clear registers described below Timer Control Status Register 2 TCSR2 The timers are also controlled by bits in the Co...

Page 57: ...he mapping of bits in this register are as follows When either of these fields are written either by a single 32 bit write or separate 16 bit writes the respective timer is loaded with the written value on the next rising edge of the timer clock regardless of whether the timer is enabled or disabled The value stored in this register is also automatically reloaded on terminal count or timeout of th...

Page 58: ...t Register TMRCCR12 located at offset 0x20 from the address in BAR1 The mapping of bits in this register are as follows When either field is read the current count value is latched and returned There are two modes that determine how the count is latched depending on the setting of the Read Latch Select bit in the WDT Control Status Register CSR2 See the CSR2 register description for more informati...

Page 59: ...ter located at offset 0x30 from the address in BAR1 causes the interrupt from Timer 1 to be cleared This can also be done by writing a 0 to the appropriate Timer x Caused IRQ field of the timer Control Status Register CSR1 This register is write only and the data written is irrelevant Timer 2 IRQ Clear T12C The Timer 2 IRQ Clear T2IC register is used to clear an interrupt caused by Timer 2 Writing...

Page 60: ...caused by Timer 4 Writing to this register located at offset 0x3C from the address in BAR1 causes the interrupt from Timer 4 to be cleared This can also be done by writing a 0 to the appropriate Timer x Caused IRQ field of the timer Control Status Register CSR1 This register is write only and the data written is irrelevant ...

Page 61: ...s used to select the timeout value of the Watchdog Timer as follows The SERR RST Select bit is used to select whether the WDT generates an SERR on the local PCI bus or a system reset If this bit is set to 0 the WDT will generate a system reset Otherwise the WDT will make the local PCI bus SERR signal active Field Bits Read or Write SERR RST Select WCSR 16 R W WDT Timeout Select WCSR 10 8 R W WDT E...

Page 62: ... continue to operate Once the Watchdog Timer is enabled the application software must refresh the Watchdog Timer within the selected timeout period to prevent a reset or SERR from being generated The Watchdog Timer is refreshed by performing a write to the WDT Keepalive register WKPA The data written is irrelevant WDT Keepalive Register WKPA When enabled the Watchdog Timer is prevented from resett...

Page 63: ...e SRAM This memory is mapped in 32K of address space starting at the address in BAR0 This memory is available at any time and supports byte short word and long word accesses from the PCI bus The contents of this memory is retained when the power to the board is removed ...

Page 64: ...s Figure 3 1 maps the configuration possibilities for a typical system consisting of the VMICPCI 7755 with a resident Flash Disk a hard drive attached to the Primary IDE interface and a floppy drive attached to the floppy interface Figure 3 1 Typical System Configuration The Primary and Secondary PCI IDE Interfaces are controlled enabled or disabled in the Integrated Peripheral Setup screen of the...

Page 65: ...system As discussed earlier a typical system consists of the VMICPCI 7755 with its resident Flash Disk configured as the Secondary IDE device a hard drive attached to the Primary IDE interface and a floppy drive attached to the floppy interface Using this configuration it may be desirable to have a logical device on either IDE device configured as a bootable device allowing the selection of the fi...

Page 66: ...Master to AUTO 19 Set boot device to desired boot source Drive letter assignments for a simple system are illustrated in Figure 3 1 on page 64 Understanding the order the operating system assigns drive letters is necessary for these multiple partition configurations The operating system assigns drive letter C to the active primary partition on the first hard disk the boot device Drive D is assigne...

Page 67: ...onnected through the LAN front panel RJ 45 connector to boot remotely This feature allows users to create systems without the worry of disk drive reliability or the extra cost of adding Flash drives BootWare Features Netware 802 1 802 3 or EthII TCP IP DHCP or BootP RPL and PXE boot support Unparalleled boot sector virus protection Detailed boot configuration screens Comprehensive diagnostics Opti...

Page 68: ...68 3 VMICPCI 7755 Product Manual ...

Page 69: ...ion 7 No components or adjacent boards were disturbed when inserting or removing the board from the chassis 8 Quality of cables and I O connections If products must be returned contact VMIC for a Return Material Authorization RMA Number This RMA Number must be obtained prior to any return VMIC Customer Service is available at 1 800 240 7782 Or E mail us at customer service vmic com Maintenance Pri...

Page 70: ...70 4 VMICPCI 7755 Product Manual ...

Page 71: ...Connectors and Pinout J7 79 PMC Connector Pinout 80 Introduction The VMICPCI 7755 CompactPCI Peripheral SBC has several connectors for its I O ports Wherever possible the VMICPCI 7755 uses connectors and pinouts typical for any desktop PC This ensures maximum compatibility with a variety of systems Connector diagrams in this appendix are generally shown in a natural orientation with the controller...

Page 72: ... GND 24 C_AD 1 5 V CPCI_VIO C_AD 0 C_ACK64 N C 23 CPCI_3 3 C_AD 4 C_AD 3 5 V C_AD 2 GND 22 C_AD 7 GND CPCI_3 3 C_AD 6 C_AD 5 N C 21 CPCI_3 3 C_AD 9 C_AD 8 GND C_C BE0 GND 20 C_AD 12 GND CPCI_VIO C_AD 11 C_AD 10 N C 19 CPCI_3 3 C_AD 15 C_AD 14 GND C_AD 13 GND 18 C_SERR GND CPCI_3 3 C_PAR C_C BE1 N C 17 CPCI_3 3 I2C_SCL I2C_SDA GND C_PERR GND 16 C_DEVSEL GND CPCI_VIO C_STOP C_LOCK N C 15 CPCI_3 3 C_...

Page 73: ...EQ6 C_GNT6 N C 16 N C N C PULLUP GND N C GND 15 N C GND PULLUP C_REQ5 C_GNT5 N C 14 C_AD35 C_AD34 C_AD33 GND C_AD32 GND 13 C_AD38 GND CPCI_VIO C_AD37 C_AD36 N C 12 C_AD42 C_AD41 C_AD40 GND C_AD39 GND 11 C_AD45 GND CPCI_VIO C_AD44 C_AD43 N C 10 C_AD49 C_AD48 C_AD47 GND C_AD46 GND 9 C_AD52 GND CPCI_VIO C_AD57 C_AD50 N C 8 C_AD56 C_AD55 C_AD54 GND C_AD53 GND 7 C_AD59 GND CPCI_VIO C_AD58 C_AD57 N C 6 ...

Page 74: ...w E Row F 19 WGATE WDATA STEP WPT DSKCHG GND 18 DRVSB DRATE0 TRK0 RDATA DIR GND 17 MOTEA DRVSA INDEX SIDE1 MOTEB GND 16 REDWC SP1_RX SP1_RTS SP1_R1 SP1_DTR GND 15 VIO SP1_TX SP1_CTS SP1_DC0 SP1_DSR GND 14 VCC_3 3 VCC_3 3 VCC_3 3 VCC_5 0 VCC_5 0 GND 13 J12_5 J12_4 J12_3 J12_2 J12_1 GND 12 J12_10 J12_9 J12_8 J12_7 J12_6 GND 11 J12_15 J12_14 J12_13 J12_12 J12_11 GND 10 J12_20 J12_19 J12_18 J12_17 J12...

Page 75: ...mination to function A 4 7k Ohm pullup resister to 5v a 33 Ohm series resistor and a 180pF bypass cap to ground are suggested for each signal Pin No Row A Row B Row C Row D Row E Row F 25 RSV P_SLCT N C RSV RSV GND 24 RSV P_PE N C RSV RSV N C 23 RSV P_BSY_WT N C RSV RSV GND 22 RSV P_ACK RSV RSV RSV N C 21 RSV P_SLIN RSV RSV RSV GND 20 RSV P_INIT N C RSV RSV N C 19 N C N C RSV RSV RSV GND 18 P_STB ...

Page 76: ...8_14 J8_13 J8_12 J8_11 GND 19 J8_20 J8_19 J8_18 J8_17 J8_16 GND 18 J8_25 J8_24 J8_23 J8_22 J8_21 GND 17 J8_30 J8_29 J8_28 J8_27 J8_26 GND 16 J8_35 J8_34 J8_33 J8_32 J8_31 GND 15 J8_40 J8_39 J8_38 J8_37 J8_36 GND 14 J8_45 J8_44 J8_43 J8_42 J8_41 GND 13 J8_50 J8_49 J8_48 J8_47 J8_46 GND 12 J8_55 J8_54 J8_53 J8_52 J8_51 GND 11 J8_60 J8_59 J8_58 J8_57 J8_56 GND 10 VIO J8_64 J8_63 J8_62 J8_61 GND 9 DDP...

Page 77: ...re A 6 Figure A 6 Ethernet Connector and Pinout ETHERNET CONNECTOR 10BaseT 100BaseTx PIN Signal Name 1 TD Transmit Data 2 TD Transmit Data 3 RD Receive Data 4 TX_CT_OUT Transmit Center Tap Out 5 TX_CT_OUT Transmit Center Tap Out 6 RD Receive Data 7 RX_CT_OUT Receive Center Tap Out 8 RX_CT_OUT Receive Center Tap Out Connector Opening Pin 1 Top View ...

Page 78: ...re A 7 Video Connector and Pinout NOTE An adapter to convert the micro DB9 connector to a standard female high density DB15 connector is available as an option order 360 000168 004 Video Connector Pin Direction Function 1 Out Red 2 Out Green 3 Out Blue 4 Out Horizontal Sync 5 Out Vertical Sync 6 Out 5V 7 I O DDC Data 8 I O DDC Clock 9 Out Ground 1 6 9 5 ...

Page 79: ...oard Mouse Pin Dir Function Pin Dir Function 1 In Out Keyboard Data 1 In Out Mouse Data 2 Unused 2 Unused 3 Ground 3 Ground 4 5 V 4 5 V 5 Out Keyboard Clock 5 Out Mouse Clock 6 Unused 6 Unused Shield Chassis Ground Shield Chassis Ground 1 2 3 4 5 6 Keyboard Mouse Connector Pin Dir Function 1 In Out Mouse Data 2 In Out Keyboard Data 3 Ground 4 5 V 5 Out Mouse Clock 6 Out Keyboard Clock Shield Chass...

Page 80: ...5 PMC Connector J11 J15 Left Side Right Side Left Side Right Side Pin Name Pin Name Pin Name Pin Name 1 GND 2 12 33 FRAME 34 GND 3 GND 4 INTA 35 GND 36 IRDY 5 INTB 6 INTC 37 DEVSEL 38 5 V 7 BMODE1A 8 5 V 39 GND 40 LOCK 9 INTD 10 NC 41 SDONE 42 NC 11 GND 12 NC 43 PAR 44 GND 13 CLK 14 GND 45 5 V 46 AD 15 15 GND 16 GNT 47 AD 12 48 AD 11 17 REQ 18 5 V 49 AD 9 50 5 V 19 5 V 20 AD 31 51 GND 52 C BE0 21 ...

Page 81: ...NC 3 GND 4 NC 35 TRDY 36 3 3 V 5 5 V 6 GND 37 GND 38 STOP 7 GND 8 NC 39 PERR 40 GND 9 NC 10 NC 41 3 3 V 42 SERR 11 PRSNT2 12 3 3 V 43 C BE1 44 GND 13 RST 14 GND 45 AD 14 46 AD 13 15 3 3 V 16 GND 47 GND 48 AD 10 17 NC 18 GND 49 AD 8 50 3 3 V 19 AD 30 20 AD 29 51 AD 7 52 NC 21 GND 22 AD 26 53 3 3 V 54 NC 23 AD 24 24 3 3 V 55 NC 56 GND 25 IDSEL 26 AD 23 57 NC 58 NC 27 3 3 V 28 AD 20 59 GND 60 NC 29 A...

Page 82: ...E20 12 J8 12 J5 pin D20 43 J8 43 J5 pin C14 44 J8 44 J5 pin B14 13 J8 13 J5 pin C20 14 J8 14 J5 pin B20 45 J8 45 J5 pin A14 46 J8 46 J5 pin E13 15 J8 15 J5 pin A20 16 J8 16 J5 pin E19 47 J8 47 J5 pin D13 48 J8 48 J5 pin C13 17 J8 17 J5 pin D19 18 J8 18 J5 pin C19 49 J8 49 J5 pin B13 50 J8 50 J5 pin A13 19 J8 19 J5 pin B19 20 J8 20 J5 pin A19 51 J8 51 J5 pin E12 52 J8 52 J5 pin D12 21 J8 21 J5 pin ...

Page 83: ... J3 pin D20 43 J12 43 J3 pin C14 44 J12 44 J3 pin B14 13 J12 13 J3 pin C20 14 J12 14 J3 pin B20 45 J12 45 J3 pin A14 46 J12 46 J3 pin E13 15 J12 15 J3 pin A20 16 J12 16 J3 pin E19 47 J12 47 J3 pin D13 48 J12 48 J3 pin C13 17 J12 17 J3 pin D19 18 J12 18 J3 pin C19 49 J12 49 J3 pin B13 50 J12 50 J3 pin A13 19 J12 19 J3 pin B19 20 J12 20 J3 pin A19 51 J12 51 J3 pin E12 52 J12 52 J3 pin D12 21 J12 21 ...

Page 84: ...84 A VMICPCI 7755 Product Manual ...

Page 85: ...ccess by means of on board PCI based adapters and associated software drivers High performance video and Ultra ATA storage device control are provided by the embedded Intel 815E chipset High performance LAN operation including 10BaseT and 100BaseTx is provided by the Intel GD82559ER Fast Ethernet adapter chip To optimize performance of each of these PCI based subsystems the user must install the d...

Page 86: ...led Windows 98 SE 2000 will attempt to load a device driver for a device USB that is not present at that point See BIOS Setup on page 87 for guidelines on changing BIOS settings A suggested workaround to this situation is to connect a PS 2 keyboard and mouse disable Legacy USB Support and enable Assign Interrupt to USB in the BIOS and install Windows 98 SE 2000 At some point after the installation...

Page 87: ...OS setting Press or on the number keypad to toggle the setting between Other Win 95 and Win 98 Win2000 4 Using the arrow keys select the Assign Interrupt to USB setting Press or on the number keypad to toggle the setting between Enabled and Disabled NOTE See Using USB Keyboard Mouse with Microsoft Windows Operating Systems on page 86 for proper setting 5 Using the arrow keys select the Legacy USB ...

Page 88: ...ing the Windows 98 SE installation process NOTE Leave the Windows 98 SE installation CD ROM in the CD ROM drive during the entire setup process as additional files may need to be copied Intel 815 Chipset Software Installation 1 If not already present insert the Windows Drivers CD ROM 2 Click Start Run Browse In the Look in pull down selection menu select the Windows Drivers CD ROM Double click on ...

Page 89: ... OK 3 At the Intel 810 810E 815 815E 815EM Chipset Graphics Driver Software Setup window click Next 4 Click Yes to agree to the software license agreement 5 Ensure Yes I want to restart my computer now is selected and click Finish The computer will re boot Create an Ethernet Adapter Driver Disk 1 Insert a blank floppy disk The disk will be formatted and files will automatically be copied onto the ...

Page 90: ... Windows driver file search for the device Intel GD82559ER PCI Adapter Click Next If a Copying Files window appears asking for the location of the Windows 98 SE CD ROM specify the path to the CD ROM drive containing the Windows 98 SE CD ROM for example d and click OK After files have been copied click Finish and remove the floppy disk and CD ROM 6 At the System Settings Change window that says Do ...

Page 91: ...down selection menu select the Windows Drivers CD ROM Double click on the WinNT folder Double click on the UltraATA folder Double click on UltraATA Click OK 3 At the Intel Ultra ATA storage Driver 6 1 Setup window click Next Click Yes to agree to the license agreement Click Next twice 4 Ensure Yes I want to restart my computer now is selected and click Finish The computer will re boot Video Driver...

Page 92: ...ick Select from list Click Have Disk OK 6 In the Select OEM Option window ensure Intel GD82559ER Fast Ethernet Adapter is selected and click OK 7 In the following window ensure Intel GD82559ER Fast Ethernet Adapter is selected and click Next 8 Select the desired protocols and click Next 9 Click Next two more times 10 In the Windows NT Setup window enter D If a drive letter other than D is assigned...

Page 93: ...D ROM Double click on the Win2000 folder Double click on the 815CPHST folder Double click on the DISK1 folder Double click on SETUP Click OK 3 At the Welcome window click Next 4 Click Yes to agree to the software license agreement 5 Click Next at Readme Information window 6 At the Setup Complete window ensure Yes I want to restart my computer now is selected and click Finish Windows 2000 will rest...

Page 94: ...rnet Adapter Driver Installation 1 Insert the Windows Drivers CD ROM 2 Right click on My Computer and select Properties Click on the Hardware tab Click Device Manager 3 Double click on Ethernet Controller found under Other devices 4 In the Ethernet Controller Properties window click on the Driver tab Click Update Driver Click Next twice Ensure Specify a location is the only search location selecte...

Page 95: ...talling all of the drivers provided on the Windows Drivers CD ROM Device Manager will still indicate that several PCI devices do not have drivers loaded These devices are the PCI to PCI bridge and the VMIC proprietary FPGA Although these devices are listed as non functioning by Windows the hardware is functioning as designed ...

Page 96: ...96 B VMICPCI 7755 Product Manual ...

Page 97: ...BIOS for configuration such as floppy drive configuration or system memory The parameters shown throughout this section are the default values Help Window The help window on the right side of each menu displays the help text for the currently selected field It updates as you move the cursor to each field Pressing F1 or ALT H on any menu brings up the General Help window that describes the legend k...

Page 98: ... to highlight ATAPI CD ROM Drive Press ENTER to continue with system boot This feature is accessed by pressing the ESC at the very beginning of the boot cycle The selection made from this screen applies to the current boot only and will not be used during the next boot up of the system If you have trouble accessing this feature disable the QuickBoot Mode in the Main BIOS setup screen Exit saving c...

Page 99: ... PGDN key to step through the available choices or type in the information System Date Press the left or right arrow key to move the cursor to the desired field month day year Press the PGUP or PGDN key to step through the available choices or type in the information 3KRHQL 6HWXS 8WLOLW 0 1 GYDQFHG 6HFXULW 3RZHU RRW LW WHP 6SHFLILF HOS 4XLFN RRW 0RGH QDEOHG 6 VWHP 7LPH OORZV WKH V VWHP WR VNLS FHU...

Page 100: ... Slave The VMICPCI 7755 is capable of utilizing one IDE hard disk drive on the Primary Master bus The default setting is Auto The Primary Slave is assigned to the CD ROM if installed If a setting other than Auto is selected the user must match the settings to the hardware 3KRHQL 6HWXS 8WLOLW 0 1 WHP 6SHFLILF HOS 3ULPDU 0DVWHU 8VHU RX HQWHU SDUDPHWHUV RI KDUG GLVN GULYH LQVWDOOHG DW WKLV FRQQHFWLRQ...

Page 101: ...nables or disables the Keyboard Auto Repeat Rate and Delay settings When disabled the values in the Typematic Rate and Delay are ignored The default is Disabled Keyboard Auto Repeat Rate Chars Sec If the Key Click is enabled this determines the rate a character is repeated when a key is held down The options are 30 26 7 21 8 18 5 13 3 10 6 or 2 characters per second The default is 30 3KRHQL 6HWXS ...

Page 102: ...he console Com Port Address If enabled it will allow remote access through the serial port The options are Disabled Motherboard Com A and Motherboard Com B The default is Disabled Baud Rate Selects a baud rate for the serial port The options are 600 1200 2400 4800 9600 19 2 38 4 and 115 2 The default is 19 2 Console Type Selects the type of console to be used The options are PC ANSI or VT100 The d...

Page 103: ...aded The options are OFF or ON The default setting is OFF System Memory The System Memory field is for informational purposes only and cannot be modified by the user This field displays the base memory installed in the system Extended Memory The Extended Memory field is for informational purposes only and cannot be modified by the user This field displays the total amount of memory installed in th...

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Page 105: ...bling the cache memory enhances the speed of the processor When the CPU requests data the system transfers the requested data from the main DRAM into the cache memory where it is stored until processed by the CPU The default is Enabled 3KRHQL 6HWXS 8WLOLW 9 1 WHP 6SHFLILF HOS DFKH 0HPRU 6HWV WKH VWDWH RI WKH PHPRU FDFKH 0HPRU DFKH QDEOHG DFKH 6 VWHP 26 DUHD ULWH 3URWHFW DFKH 9LGHR 26 DUHD ULWH 3UR...

Page 106: ...ent representations of drive geometries The default is DOS LBA Assisted Translation LBA Logical Block Addressing During drive accesses the IDE controller transforms the data address described by sector head and cylinder number into a physical block address This significantly improves data transfer rates for drives with greater than 1024 cylinders The default is Disabled 3KRHQL 6HWXS 8WLOLW 9 1 WHP...

Page 107: ...ted from a Cardbus controller located behind a PCI to PCI Bridge When enabled the screen will show the amount allocated The default is Enabled POST Errors Pauses and displays Setup Entry or Resume Boot prompt if an error occurs on boot If disabled the prompt will be bypassed and the system will attempt to boot The default is Enabled Force Hard Reset A reboot causes a warm restart which does not is...

Page 108: ...ainst viruses The default is Normal Diskette Access Controls access to the diskette drives The default is User 3KRHQL 6HWXS 8WLOLW 6HFXULW WHP 6SHFLILF HOS 6HFXULW 6XSHUYLVRU 3DVVZRUG FRQWUROV FFHVV WR WKH VHWXS XWLOLW 6HW 8VHU 3DVVZRUG QWHU 6HW 6XSHUYLVRU 3DVVZRUG QWHU 3DVVZRUG RQ ERRW LVDEOHG L HG GLVN ERRW VHFWRU 1RUPDO LVNHWWH DFFHVV 8VHU HOS 6HOHFW WHP KDQJH 9DOXHV 6HWXS HIDXOWV 6 LW 6HOHFW 0...

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Page 110: ...ressing Shift 1 Enter expands or collapses devices with a or next to them 3KRHQL 6HWXS 8WLOLW 0 1 GYDQFHG 6HFXULW 3RZHU RRW LW WHP 6SHFLILF HOS 5HPRYDEOH HYLFHV DUG ULYH H V XVHG WR YLHZ RU FRQILJXUH GHYLFHV QWHU H SDQGV RU FROODSVHV GHYLFHV ZLWK D RU WUO QWHU H SDQGV DOO 6KLIW HQDEOHV RU GLVDEOHV D GHYLFH DQG PRYHV WKH GHYLFH XS RU GRZQ Q PD PRYH UHPRYDEOH GHYLFH EHWZHHQ DUG LVN RU 5HPRYDEOH LVN ...

Page 111: ...carding any changes to CMOS Load Setup Defaults Load System defaults as defined at the factory Discard Changes Discard any changes without exiting the Setup program Save Changes Save any changes made without exiting the Setup program 3KRHQL 6HWXS 8WLOLW 0DLQ GYDQFHG 3RZHU RRW LW WHP 6SHFLILF HOS LW 6DYLQJ KDQJHV LW LVFDUGLQJ KDQJHV LW 6 VWHP 6HWXS DQG VDYH RXU FKDQJHV WR 026 RDG VHWXS HIDXOWV LVFD...

Page 112: ...112 C VMICPCI 7755 Product Manual ...

Page 113: ...nus 114 BIOS Features Setup 116 Introduction The VMICPCI 7755 includes a LANWorks option which allows the VMICPCI 7755 to be booted from a network This appendix describes the procedures to enable this option and the LANWorks BIOS Setup screens D ...

Page 114: ...g in the Boot menu Using the arrow keys highlight Managed PC Boot Agent MBA and press the ENTER key to continue with the system boot Boot Menu The second method of enabling the LANWorks BIOS option is to press the F2 key during system boot This will access the BIOS Setup Utility Advance to the Boot menu and using the arrow keys highlight the Managed PC Boot Agent MBA option Repeat entering until M...

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Page 118: ...118 D VMICPCI 7755 Product Manual ...

Page 119: ...e directory sample code on CD 320 500077 000 labeled Windows Drivers included with the VMICPCI 7755 These files are provided without warranty All source code is 2001 VMIC Corporation Directory 21154 This directory contains code used to test accesses across the CompactPCI bus between a peripheral CPU card for example the VMICPCI 7756 and a system controller CPU for example the VMICPCI 7755 Director...

Page 120: ...s directory contains common files required to compile several of the sample code applications Directory max1617 This directory contains code that demonstrates how to read the temperatures from the max1617 device on the VMICPCI 7755 Directory support This directory contains memory and PCI access routines used by many of the sample code applications Directory vlm This directory contains code that de...

Page 121: ...M used to load the 21154 Embedded PCI bridge chip at power up and reset The contents of the SROM are as follows VMICPCI 7755 21154 SROM Code Preload enable bit 7 set for preload enable 00 80 01 00 02 00 03 00 Primary Class Code 04 00 05 80 06 06 Subvendor IDs 07 55 08 77 09 4A 0A 11 Primary Min GNT Max Lat 0B 00 0C 00 F ...

Page 122: ... a 4K window size FFFFF000 12 00 13 F0 14 FF 15 FF Downstream Mem 1 or I O Set 256 byte I O window size FFFFFF01 16 01 17 FF 18 FF 19 FF Downstream Mem 2 Set 1 MB memory window size FFF00000 1A 00 1B 00 1C F0 1D FF Downstream Mem 3 Set 1 MB memory window size FFF00000 1E 00 1F 00 20 FC 21 FF Downstream Mem 3 Upper 32 22 00 23 00 24 00 25 00 ...

Page 123: ...B FF Upstream Mem 1 Set 256 MB memory window size F0000000 2C 00 2D 00 2E 00 2F F0 Chip Control 0 30 00 Clear lockout bit 31 00 Chip Control 1 32 00 LUT disable I2O disable 33 90 Arbiter control Sets internal 21154 secondary bus req to high priority ring 34 00 35 02 System error disable 36 00 37 00 Power management 38 00 39 00 3A 00 3B 00 ...

Page 124: ...ompactPCI backplane The CPCI 7755 21154 bridge will be programmed as follows The outbound memory window is 256MBytes inbound is 1MByte Both I O windows are 256 bytes inbound and outbound Address translation registers power up at 0 values such that the mapping forces the absolute address to 0 for outbound and inbound memory and I O windows The user MUST load program translation offset registers if ...

Page 125: ...k Drive 100 Floppy Drive A 100 I I O address space 39 port map 39 installation 30 Intel 815 Chipset 88 Intel 82559 Ethernet Controller 49 interrupt line assignment 41 J jumper locations 27 L LPT1 Parallel I O 40 LPT2 Parallel I O 40 M master interrupt controller 39 N Non Maskable Interrupt NMI 39 41 47 P PCI interrupt lines 44 local bus 44 PCI Configuration Space Registers 54 programmable time 39 ...

Page 126: ...rial I O COM1 2 3 4 40 SERR interrupt 47 System BIOS Setup Utility 97 U unpacking procedures 25 V vector interrupt table 41 video driver installation 89 91 93 W Windows 2000 Installation 93 Windows 98 SE Installation 88 Windows NT 4 0 91 ...

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