VMIC VMICPCI-7755, Product Manual

Page: 53 / 126

53
I2C Support
3
I
2
C Support
The VMICPCI-7755 supports the I
2
C-bus and can operate as an I
2
C-bus master or
slave per the I
2
C-bus specification, version 2.0, developed by Philips Semiconductor.
Communication over the I
2
C-bus is accomplished through the use of the National
Semiconductor Super I/O I
2
C-bus controller. This controller is capable of
communicating on the I
2
C-bus on a byte-wise basis using interrupt or polled
handshaking and supports a programmable clock rate when operating in Master
mode. The I
2
C-bus signals are routed through the VMICPCI-7755’s J1 connector as
shown in Table 3-1.
Because multiple processors may share the I
2
C signals, the VMICPCI-7755 does not
provide pull-ups on the I
2
C signals. This gives the system the flexibility of setting the
pull-up voltage level of the I
2
C bus with a single pair of pull-up resisters located on
the system controller, backplane or any other connected system device.
The controller can issue interrupts to the VMICPCI-7755 when handshaking on the
I
2
C-bus. When the I
2
C-bus controller drives the interrupt active, software must
service and then clear the interrupt. Software can determine the cause of the interrupt
by reading the bit of the status register.
For more information related to programming the I
2
C-bus controller, see the section
“Access, Bus Interface (ACB)” in the “PC87366 128-pin LPC Super I/O with System
Hardware Monitoring and MIDI and Game Ports” datasheet available from National
Semiconductor.
Table 3-1 I
2
C-bus Through J1
Signal Name Pin
I2C_SCL B17
I2C_SDA C17
The user must supply appropriate pullups on these pins.