ViewSonic VX922-1, Service Manual

Page: 101 / 104

RESET circuit
External ROM
SPI EEPROM
Extrenal ROM Download Connector
CONFIG SETTING
SPI_SCK
SPI_SI
RXE1+
O_S
D1_G6
O_S
D1_G7
O_S
D1_R
3
O_S
D1_R
4
O_S
D1_R
5
O_S
D1_R
6
O_S
D1_R
7
E_S
D
1_B
3
E_S
D
1_B
4
E_S
D
1_B
5
E_S
D
1_B
6
E_S
D
1_B
7
E_
SD
1_G3
E_
SD
1_G4
E_
SD
1_G5
O_S
D1_B
3
O_S
D1_B
4
O_S
D1_B
5
O_S
D1_B
6
E_
SD
1_G6
E_
SD
1_G7
E_S
D
1_R
3
E_S
D
1_R
4
E_S
D
1_R
5
E_S
D
1_R
6
E_S
D
1_R
7
D_O_S
D1_B3
D_O_S
D1_B4
D_O_S
D1_B5
D_O_S
D1_B6
D_O_S
D1_G6
D_O_S
D1_G7
D_O_S
D1_R3
D_O_S
D1_R4
D_O_S
D1_R5
D_O_S
D1_R6
D_O_S
D1_R7
D_E
_S
D1_B
3
D_E
_S
D1_B
4
D_E
_S
D1_B
5
D_E
_S
D1_B
6
D_E
_S
D1_B
7
D_E
_S
D1_G3
D_E
_S
D1_G4
D_E
_S
D1_G5
D_E
_S
D1_G6
D_E
_S
D1_G7
D_E
_S
D1_R
3
D_E
_S
D1_R
4
D_E
_S
D1_R
5
D_E
_S
D1_R
6
D_E
_S
D1_R
7
SD
_C
LK
SD
RAM_
CL
OCK
E_SD2_R7
E_SD2_R6
E_SD2_R5
D_E_SD2_ R7
D_E_SD2_ R6
D_E_SD2_ R5
E_SD2_R4
E_SD2_R3
E_SD2_ G7
E_SD2_ G6
D_E_SD2_ R4
D_E_SD2_ R3
D_E_SD 2_G7
D_E_SD 2_G6
D_E_SD 2_G5
D_E_SD 2_G4
D_E_SD 2_G3
D_E_SD2_ B7
E_SD2_B6
E_SD2_B5
E_SD2_B4
E_SD2_B3
D_E_SD2_ B6
D_E_SD2_ B5
D_E_SD2_ B4
D_E_SD2_ B3
O_SD2_R 7
O_SD2_R 6
O_SD2_R 5
O_SD2_R 3
O_SD2_G7
O_SD2_G6
O_SD2_R 4
O_SD2_G4
O_SD2_G3
O_SD2_B 7
O_SD2_G5
O_SD2_B 5
O_SD2_B 4
O_SD2_B 3
O_SD2_B 6
D_O_SD2 _R5
D_O_SD2 _R7
D_O_SD2 _R6
D_O_SD2 _R4
D_O_SD2 _R3
D_O_SD2_G7
D_O_SD2_G6
D_O_SD2_G5
D_O_SD2_G4
D_O_SD2_G3
D_O_SD2 _B7
D_O_SD2 _B6
D_O_SD2 _B5
D_O_SD2 _B4
D_O_SD2 _B3
SEL_ROM_1
SEL_ROM_2
TAB_SEL_2
TAB_SEL_0
TAB_SEL_1
OD_EN
D_O_SD1 _B3
D_O_SD1 _B4
D_O_SD1 _B5
D_O_SD1 _B6
D_O_SD1 _B7
D_O_SD1_G3
D_O_SD1_G4
D_O_SD1_G5
SD_DQ M0
SD1_WE
SD_CAS
SD_RAS
SD_CS
SD_BA0
SD_A10
SD_A0
SD_A1
SD_A2
SD_A3
D_O_SD1 _R7
D_O_SD1 _R6
D_O_SD1 _R5
D_O_SD1 _R4
D_O_SD1 _R3
D_O_SD1_G7
D_O_SD1_G6
SD_DQ M0
SDRAM_CLOCK
SD_A9
SD_A8
SD_A7
SD_A6
SD_A5
SD_A4
D_E_SD1_ B3
D_E_SD1_ B4
D_E_SD1_ B5
D_E_SD1_ B6
D_E_SD1_ B7
D_E_SD 1_G3
D_E_SD 1_G4
D_E_SD 1_G5
SD_DQ M0
SD1_WE
SD_CAS
SD_RAS
SD_CS
SD_BA0
SD_A10
SD_A0
SD_A1
SD_A2
SD_A3
D_E_SD1_ R7
D_E_SD1_ R6
D_E_SD1_ R5
D_E_SD1_ R4
D_E_SD1_ R3
D_E_SD 1_G7
D_E_SD 1_G6
SD_DQ M0
SDRAM_CLOCK
SD_A9
SD_A8
SD_A7
SD_A6
SD_A5
SD_A4
D_E_SD2_G5
D_E_SD2_G4
D_E_SD2_G3
D_E_SD2 _B7
D_E_SD2 _B6
D_E_SD2 _B5
D_E_SD2 _B4
D_E_SD2 _B3
SD_DQM1
SD2_WE
SD_CAS
SD_RAS
SD_CS
SD_BA0
SD_A10
SD_A0
SD_A1
SD_A2
SD_A3
D_E_SD2_G6
D_E_SD2_G7
D_E_SD2 _R3
D_E_SD2 _R4
D_E_SD2 _R5
D_E_SD2 _R6
D_E_SD2 _R7
SD_DQM1
SDRAM_CLOCK
SD_A9
SD_A8
SD_A7
SD_A6
SD_A5
SD_A4
D_O_SD2_G5
D_O_SD2_G4
D_O_SD2_G3
D_O_SD2 _B7
D_O_SD2 _B6
D_O_SD2 _B5
D_O_SD2 _B4
D_O_SD2 _B3
SD_DQM1
SD2_WE
SD_CAS
SD_RAS
SD_CS
SD_BA0
SD_A10
SD_A0
SD_A1
SD_A2
SD_A3
D_O_SD2_G6
D_O_SD2_G7
D_O_SD2_R3
D_O_SD2_R4
D_O_SD2_R5
D_O_SD2_R6
D_O_SD2_R7
SD_DQM1
SDRAM_CLOCK
SD_A9
SD_A8
SD_A7
SD_A6
SD_A5
SD_A4
SD
_C
A
S
E_S
D
1_R
6
E_SD1_B3
TAB_SEL_1
RESET
O_S
D2_R
5
E_SD2_G7
SD_A5
O_S
D1_R
5
O_S
D1_G6
O_S
D1_G3
O_S
D1_B
6
E_S
D
1_R
7
TX
E2
-
O_S
D2_G7
O_SD2_B 3
E_SD2_G3
E_SD2_B 3
E_SD1_G7
SPI_SCK
TXO1+ TXO2+
O_SD2_B 7
O_SD2_B 6
E_SD2_B 6
SD2_WE
O_S
D1_R
6
TXO3- TX
EC
+
TX
E3
-
O_S
D2_R
3
SD_A2
SD_BA0
O_S
D1_B
3
SPI_SO
SD
_DQM
1
O_S
D1_B
7
SPI_CS
SEL_ROM_2
SEL_ROM_1
TXO0- TX
E1
+
O_S
D2_R
7
O_S
D2_R
6
E_SD2_R 3
E_SD2_G4
SD_A1
SD_A10
O_S
D1_R
4
O_S
D1_G5
O_S
D1_B
5
O_S
D1_B
4
E_SD1_R3
E_
SD
1_G5
O_SD2_B 4
SD_A7
SD
_C
LK
E_S
D
1_R
5
E_
SD
1_G4
OD_EN
RXO1+
TXO1-
E_SD2_B 7
O_S
D1_G4
TXOC+ TX
EC
-
E_SD2_R 7
SD_A8
E_S
D
1_R
4
E_SD1_B7 E_SD1_B6 E_SD
1
_
B
5
E_SD2_R 6
E_SD2_B 4
SD_A3
SD_A6
SD
1_W
E
SPI_SI
RESET
TX
E0
-
TX
E1
-
E_SD2_R 4
E_SD2_G5
SD_A4
O_S
D1_R
3
SD
_R
A
S
TAB_SEL_0
TAB_SEL_2
TXO0+
TX
E0
+
O_S
D2_R
4
E_SD2_G6
O_S
D1_G7
TXOC- TX
E2
+
RXO0-
E_SD2_B 5
SD_A0
SD
_DQM
0
O_S
D1_R
7
E_SD1_G6
E_
SD
1_G3
E_SD1_B4
RXE0+
TXO2-
TXO3+
TX
E3
+
O_SD2_B 5
E_SD2_R 5
SD_A9
SD
_C
S
SPI_SO
SPI_CS
SPI_CS SPI_SO
SPI_SCK SPI_SI
RESET
RXO3-
RXOC+
RXO2-
RXO3+
RXO1-
RXO0+
RXE3-
RXE3+
RXEC+
RXEC-
RXE2-
RXE2+
RXE0-
RXOC-
RXO2+
E_SD2_ G4
E_SD2_ G5
E_SD2_B7
E_SD2_ G3
O_SD2_G5
O_SD2_G4
O_SD2_G3
O_SD2_G6
RXO0- RXO0+
RXO1- RXO1+
RXO2- RXO2+
RXOC-
RXO3-
RXE0-
RXE2-
RXEC-
RXE3- RXE3+
RXEC+
RXE2+
RXE1+
RXO3+
RXOC+
RXE0+
RXE1-
RXE1-
TXO0+
TXO2-
TXOC- TXOC+
TXO0-
TXE3+
TXE2+
TXO1-
TXO3-
TXE1+
TXO1+
TXO3+
TXO2+
TXE0+
TXE3-
TXEC- TXEC+
TXE2-
TXE0-
TXE1-
O_S
D1_B
7
O_S
D1_G5
D_O_S
D1_B7
O_S
D1_G3
D_O_S
D1_G5
D_O_S
D1_G3
O_S
D1_G4
D_O_S
D1_G4
DGND
3.3V
DGND
DGND
3.3V
OD_3.3V
3.3V
LVDS_3.3V
LVDS_GND
3.3V
OD_3.3V
DGND
3.3V SDRAM1_3.3V
DGND
3.3V SDRAM2_3.3V
3.3V
SDRAM1_3.3V
DGND DGND
DGND
SDRAM1_3.3V
DGND
SDRAM2_3.3V
SDRAM2_3.3V
LVDS_GND
DGND
DGND
DGND
DGND
LVDS_GND LVDS_GND
LVDS_GND
LVDS_GND
LVDS_GND
LVDS_GND
5V
5V
LVDS_3.3V
C61
0.
1uF/
6
R9
100/6 1%
PR9
33x4
1 2 3 4
5 6 7 8
C39
0.
1uF/
6
C88
0.
1uF/
6
PR6
33x4
1
2
3
4
5
6
7
8
L4
CX00080 0000/8
C70
0.
1uF/
6
C9 0.
1uF/
6
C44
0.
1uF/
6
C83
0.
1uF/
6
C66
0.
1uF/
6
C37
0.
1uF/
6
C10
0.
1uF/
6
C80
0.
1uF/
6
C69
0.
1uF/
6
C43
0.
1uF/
6
PR2
33x4
1
2
3
4
5
6
7
8
C78
0.
1uF/
6
C68
0.
1uF/
6
C11
0.
1uF/
6
Receiver_ODD
Receiver_EVEN
Config
SPI
E_SD1_ B E_SD1_ G E_SD1_R O_SD1_R O_SD1_G O_SD1_ B
E_SD2_B
E_SD2_G
E_SD2_R
O_SD2_B
O_SD2_BR Transmitter_EVEN Transmitter_ODD
VTIO3602
U4
VTIO3601_LQFP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 78 79 80 81 74 75 76 77 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208
LVDS_VCC
LVDS_VCC
LVDS_VCC
RXO0-
RXO0+
RXO1-
RXO1+
RXO2-
RXO2+
RXOC-
RXOC+
RXO3-
RXO3+
LVDS_GND
LVDS_GND
LVDS_GND
LVDS_GND
LVDS_VCC
LVDS_VCC
LVDS_VCC
RXE0-
RXE0+
RXE1-
RXE1+
RXE2-
RXE2+
RXEC-
RXEC+
RXE3-
RXE3+
LVDS_GND
LVDS_GND
LVDS_GND
LVDS_GND
RESERVED
RESERVED
SEL_ROM_1
SEL_ROM_2
RSTN
TAB_SEL_1
TAB_SEL_2
TAB_SEL_0
OD_EN
SPI_CLK
SPI_SI
SPI_CS
SPI_SO
PAD_TEST
PAD_TCLK
RESERVED
VCC
GND
GND VCC EVEN_SD1_B3 EVEN_SD1_B4 EVEN_SD1_B5 EVEN_SD1_B6 EVEN_SD1_B7 EVEN_SD1_G3 EVEN_SD1_G4 EVEN_SD1_G5 EVEN_SD1_G6 EVEN_SD1_G7 EVEN_SD1_R3 RESERVED GND VCC RESERVED EVEN_SD1_R4 EVEN_SD1_R5 EVEN_SD1_R6 EVEN_SD1_R7 RESERVED GND VCC RESERVED ODD_SD1_B3 ODD_SD1_B4 ODD_SD1_B5 ODD_SD1_B6 ODD_SD1_B7 ODD_SD1_G3 ODD_SD1_G4 ODD_SD1_G5 ODD_SD1_G6 ODD_SD1_G7 ODD_SD1_R3 ODD_SD1_R4 GND VCC RESERVED ODD_SD1_R5 ODD_SD1_R6 ODD_SD1_R7 SDRAM_DQM_0 SDRAM_1_W
E
SDRAM_DQM_1 SDRAM_CAS SDRAM_RAS SDRAM_CLK SDRAM_CS GND VCC
GND
VCC
SDRAM_A9
SDRAM_BA0
SDRAM_A8
SDRAM_BA1
SDRAM_A7
SDRAM_A10
SDRAM_A6
SDRAM_A0
SDRAM_A5
SDRAM_A1
SDRAM_A4
SDRAM_A2
SDRAM_A3
RESERVED
GND
VCC
RESERVED
SDRAM_2_WE
EVEN_SD2_B3
EVEN_SD2_B4
EVEN_SD2_B5
EVEN_SD2_B6
EVEN_SD2_B7
EVEN_SD2_G3
GND
VCC
RESERVED
EVEN_SD2_G4
EVEN_SD2_G5
EVEN_SD2_G6
EVEN_SD2_G7
EVEN_SD2_R3
EVEN_SD2_R4
EVEN_SD2_R5
EVEN_SD2_R6
GND
VCC
RESERVED
EVEN_SD2_R7
ODD_SD2_B3
ODD_SD2_B4
ODD_SD2_B5
ODD_SD2_B6
ODD_SD2_B7
ODD_SD2_G3
ODD_SD2_G4
ODD_SD2_G5
ODD_SD2_G6
GND
VCC
VCC GND
ODD_SD2_G7 ODD_SD2_R3 ODD_SD2_R4 ODD_SD2_R5 ODD_SD2_R6 ODD_SD2_R7
LVDS_GND LVDS_VCC LVDS_GND LVDS_GND
TXE3+ TXE3-
TXEC+
TXEC- TXE2+ TXE2-
LVDS_VCC
TXE1+ TXE1- TXE0+ TXE0-
LVDS_GND LVDS_GND LVDS_VCC LVDS_GND LVDS_VCC LVDS_GND LVDS_GND
TXO3+
TXO3-
TXOC+
TXOC-
TXO2+
TXO2-
LVDS_VCC
TXO1+
TXO1-
TXO0+
TXO0-
LVDS_GND LVDS_GND LVDS_VCC RESERVED LVDS_VCC LVDS_GND RESERVED RESERVED RESERVED RESERVED RESERVED
C35
0.
1uF/
6
R5
100/6 1%
C77
0.
1uF/
6
PR10
33x4
1 2 3 4
5 6 7 8
C65
0.
1uF/
6
PR5
33x4
1
2
3
4
5
6
7
8
C41
0.
1uF/
6
C12
0.
1uF/
6
C82
0.
1uF/
6
C71
0.
1uF/
6
R12
100/6 1%
C45
0.
1uF/
6
C76
0.
1uF/
6
C64
0.
1uF/
6
C59
10uF/
8
C13
0.
1uF/
6
C40
0.
1uF/
6
C5
10uF/8
C85
0.
1uF/
6
JP1
1841 30P
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29 2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
C63
0.
1uF/
6
C24
10uF/
8
PR1
33x4
1
2
3
4
5
6
7
8
U7
DRAM_16M
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Vcc
DQ0
DQ1
VssQ
DQ2
DQ3
VccQ
DQ4
DQ5
VssQ
DQ6
DQ7
VccQ
LDQM
WE
CAS
RAS
CS
BA
A10
A0
A1
A2
A3
Vcc
Vss
A4
A5
A6
A7
A8
A9
NC
CKE
CLK
UDQM
NC
VccQ
DQ8
DQ9
VssQ
DQ10
DQ11
VccQ
DQ10
DQ11
VssQ
DQ14
DQ15
Vss
C58
10uF/
8
U6
DRAM_16M
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Vcc
DQ0
DQ1
VssQ
DQ2
DQ3
VccQ
DQ4
DQ5
VssQ
DQ6
DQ7
VccQ
LDQM
WE
CAS
RAS
CS
BA
A10
A0
A1
A2
A3
Vcc
Vss
A4
A5
A6
A7
A8
A9
NC
CKE
CLK
UDQM
NC
VccQ
DQ8
DQ9
VssQ
DQ10
DQ11
VccQ
DQ10
DQ11
VssQ
DQ14
DQ15
Vss
C36
0.
1uF/
6
U5
DRAM_16M
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Vcc
DQ0
DQ1
VssQ
DQ2
DQ3
VccQ
DQ4
DQ5
VssQ
DQ6
DQ7
VccQ
LDQM
WE
CAS
RAS
CS
BA
A10
A0
A1
A2
A3
Vcc
Vss
A4
A5
A6
A7
A8
A9
NC
CKE
CLK
UDQM
NC
VccQ
DQ8
DQ9
VssQ
DQ10
DQ11
VccQ
DQ10
DQ11
VssQ
DQ14
DQ15
Vss
C14
0.
1uF/
6
C74
10uF/
8
U2
DRAM_16M
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Vcc
DQ0
DQ1
VssQ
DQ2
DQ3
VccQ
DQ4
DQ5
VssQ
DQ6
DQ7
VccQ
LDQM
WE
CAS
RAS
CS
BA
A10
A0
A1
A2
A3
Vcc
Vss
A4
A5
A6
A7
A8
A9
NC
CKE
CLK
UDQM
NC
VccQ
DQ8
DQ9
VssQ
DQ10
DQ11
VccQ
DQ10
DQ11
VssQ
DQ14
DQ15
Vss
C72
0.
1uF/
6
PR13
33x4
1 2 3 4
5 6 7 8
C42
0.
1uF/
6
C79
0.
1uF/
6
R16 1K/6/NC
C73
0.
1uF/
6
C23
10uF/
8
C34
0.
1uF/
6
R
8
10K/6
C86
0.
1uF/
6
R13
100/6 1%
R15 1K/6/NC
C89
0.
1uF/
6
C18
10uF/
8
U3
SPI_AT25F512
1
2
3
4
5
6
7
8
CS
SO
WP
GND
SI
SCK
HOLD
VCC
PR14
33x4
1 2 3 4
5 6 7 8
PR8
33x4
1
2
3
4
5
6
7
8
C15
0.
1uF/
6
C87
0.
1uF/
6
R19 1K/6/NC
C16
0.
1uF/
6
C81
0.
1uF/
6
R11
100/6 1%
PR11
33x4
1 2 3 4
5 6 7 8
R18 1K/6/NC
C84
0.
1uF/
6
C17
0.
1uF/
6
C75
10uF/
8
R14 1K/6
PR15
33x4
1 2 3 4
5 6 7 8
R6
100/6 1%
C33
10uF/
8
PR7
33x4
1
2
3
4
5
6
7
8
R17 1K/6/NC
R7
100/6 1%
C32
10uF/
8
PR12
33x4
1 2 3 4
5 6 7 8
R4
100/6 1%
C19
10uF/
8
L3
CX00080 0000/8
L2
CX00080 0000/8
R3
100/6 1%
L5
CX00080 0000/8
C21
10uF/
8
PR16
33x4
1 2 3 4
5 6 7 8
JP2
20321-30-SMD
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29 2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
PR4
33x4
1
2
3
4
5
6
7
8
C6 0.
1uF/
6
D1
1SS355/NC
C22
10uF/
8
C62
0.
1uF/
6
R21
33/6
C60
0.
1uF/
6
JP3
20321-06-SMD/NC
1 2
3 4
5 6
1 2
3 4
5 6
C7 0.
1uF/
6
R10
100/6 1%
C67
0.
1uF/
6
PR3
33x4
1
2
3
4
5
6
7
8
R20 0/1206
C38
0.
1uF/
6
C8 0.
1uF/
6
Model
Title
Date Rev:
ViewSonic Corporation
BLOCK DIAGRAM
98
ViewSonic Corporation Co nfidential - Do Not Copy
VX922-1