CS#
SO
WP#
GND
SI
SCLK
HOLD#
VCC
8
7
6
5
4
3
2
1
A
B
C
D
E
F
AX M
1
2
3
4
5
6
7
8
A
B
C
D
E
F
OF:
A3
PROJECT NAME :
SCH NAME :
DRAWN BY :
SHEET:
AVDD_MI_3
MDATA[2]
MDATA[5]
AVDD_MI_6
SPI_SCK
AVDD_MIPLL
AVDD_MI_2
GND8
WADR[0]
WADR[1]
WADR[2]
WADR[3]
WADR[4]
WADR[5]
WADR[6]
WADR[7]
WADR[8]
WADR[9]
WADR[10]
WADR[11]
WEZ
CASZ
AVDD_MI_1
GND7
VDDC2
RASZ
BADR[0]
BADR[1]
ALE
RDZ
WRZ
AD[3]
AD[2]
AD[1]
AD[0]
DQM0
DQS0
MDATA[0]
MDATA[1]
GND9
MDATA[3]
AVDD_MI_4
MDATA[4]
MDATA[6]
MDATA[7]
AVDD_MI_5
MDATA[8]
MDATA[9]
GND10
MDATA[10]
MDATA[11]
MDATA[12]
MDATA[13]
MDATA[14]
MDATA[15]
AVDD_MI_7
DQS1
DQM1
MCLKZ
MCLK
MCLKE
MVREF
SPI_SDI
SPI_SCZ
SPI_SDO
GND13
VDDC3
5
VSS1
A4
A5
A6
A7
A8
A9
A11
NC5
NC6
CKE
CK
/CK
UDM
VSS2
VREF
NC7
UDQS
VSSQ3
NC8
DQ8
VDDQ4
DQ9
DQ10
VSSQ4
DQ11
DQ12
VDDQ5
DQ13
DQ14
VSSQ5
DQ15
VSS3
VDD3
A3
A2
A1
A0
A10/AP
BS1
BS0
NC4
/CS
/RAS
/CAS
/WE
LDM
NC3
VDD2
NC2
LDQS
VDDQ3
NC1
DQ7
VSSQ2
DQ6
DQ5
VDDQ2
DQ4
DQ3
VSSQ
DQ2
DQ1
VDDQ
DQ0
VDD1
GND1
A4
A5
A6
A7
A8
A9
NC1
CKE
CLK
UDQM
NC2
VDDQ3
DQ8
DQ9
GNDQ3
DQ10
DQ11
VDDQ4
DQ12
DQ13
GNDQ4
DQ14
DQ15
GND2
VDD2
A3
A2
A1
A0
A10
A11
CS
RAS
CAS
WE
LDQM
VDDQ2
DQ7
DQ6
GNDQ2
DQ5
DQ4
VDDQ1
DQ3
DQ2
GNDQ1
DQ1
DQ0
VDD1
R4
R3
R2
R1
R4
R3
R2
R1
R4
R3
R2
R1
R4
R3
R2
R1
R4
R3
R2
R1
R4
R3
R2
R1
R4
R3
R2
R1
DDRAM OPSION
SDRAM OPSION
DDRAM OPTION
SDRAM OPTION
PIN13
PIN129
PIN203
PIN131
PIN147
PIN162
PIN168
PIN173
PIN179
PIN184
WARNING!!!DON'T USE VIA FOR DQS,MCLK,MCLKZ AND DATA SIGNALS
FLASH
PIN3
PIN15
PIN44
PIN9
PIN38
PIN1
PIN18
PIN33
PIN55
PIN61
PIN7
1
T
P160
1
2
R761
4K7
1
T
P117
1
2
C605
10U
10V
1
2
C184
100N
10V
SPDIF_OUT
1
T
P116
1
2
F150
330R
3V3_STBY
1
2
C469
10U
10V
3V3_VCC
2
1
4K7
R296
PANEL_VCC_ON/OFF
3V3_VCC
1
2
R295
4K7
BACKLIGHT_ON/OFF
1
2
R499
100R
1
2
R478
100R
MCLKZ
MCLK
VDDM
1
2
C190
100N
10V
2
1
10V
100N
C186
VDD_DMQ
2
1
10V
100N
C191
1
2
C208
100N
10V
VDD_DMC
8
7
6
5
4
3
2
1
100R
R589
8
7
6
5
4
3
2
1
100R
R588
VDD_DMC
8
7
6
5
4
3
2
1
100R
R591
8
7
6
5
4
3
2
1
100R
R587
8
7
6
5
4
3
2
1
100R
R586
MDATA_15
UDM1
MADR_7
MADR_6
MADR_4
MADR_3
MADR_2
MADR_0
MADR_11
MDATA_0
UDM
MDATA_15
LDM
DQS[0]
MDATA[7]
MDATA[4]
MDATA[2]
MDATA[0]
1
T
P119
1
T
P114
1
T
P115
1
T
P113
1
T
P118
MDATA_0
MDATA_1
MDATA_2
MDATA_3
MDATA_4
MDATA_5
MDATA_6
MDATA_7
VDD_DMQ
LDM1
WEZ1
CASZ1
RASZ1
MADR_0
MADR_1
MADR_2
MADR_3
MDATA_14
MDATA_13
MDATA_12
MDATA_11
MDATA_10
MDATA_9
MDATA_8
UDM1
MCLKE1
MADR_10
MADR_11
MADR_9
MADR_8
MADR_7
MADR_6
MADR_5
MADR_4
VDDM
1
2
F162
60R
VDDM
1
2
C203
100N
10V
1
2
F157
330R
1
2
3
4
5
6
7
8
100R
R592
1
2
3
4
5
6
7
8
R590
100R
3V3_STBY
1
2
C500
1N
50V
VDD_DMQ
2V6_VCC
VDDM
MCLK
2
1
330R
F125
1
2
C195
100N
10V
VDDM
VDDM
VDDM
2
1
10V
100N
C194
VDDM
CASZ
VDDC
VDDC
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
U131
IS42S16100C1
1
2
C211
100N
10V
BA1
MDATA_12
MDATA_13
MDATA_14
MDATA_11
MDATA_10
MDATA_9
MDATA_8
MCLKE1
MADR_9
MADR_8
MADR_5
MADR_1
MADR_10
RASZ1
CASZ1
WEZ1
LDM1
MDATA_7
MDATA_6
MDATA_5
MDATA_4
MDATA_3
MDATA_2
MDATA_1
1
2
R358
100R
VDD_DMQ
1
2
R360
100R
1
2
R681
150R
MCLKZ
MCLK
1
2
R361
100R
MCLKE
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
U142
HY5DV281622DT-5
MADR[3]
MADR[2]
MADR[1]
MADR[0]
1
2
R105
22R
VDD_DMC
VDD_DMQ
VDD_DMQ
3V3_VCC
1
2
C213
100N
10V
UDM
LDM
MADR[7]
MADR[6]
CASZ
RASZ
1
2
R103
22R
WEZ
VDD_DMQ
VDD_DMC
VDD_DMQ
VDD_DMC
VDDC
162
166
170
179
198
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
160
161
163
164
165
167
168
169
171
172
173
174
175
176
177
178
180
181
182
183
184
185
186
187
188
189
190
199
200
201
202
203
U138
MST6WB7GQ-3
MDATA[11]
VDDM
VDDM
DQS[1]
DQS[0]
MADR[11]
MADR[10]
MADR[1]
1
2
C501
1N
50V
2
1
10K
R536
1
2
R535
10K
SCK
MDATA[10]
SCK
SDI
SCZ
SDO
BA0
RASZ
MADR[8]
MADR[9]
MADR[6]
MADR[5]
MADR[4]
MADR[3]
MADR[2]
MADR[5]
MADR[4]
MDATA[15]
MDATA[14]
MDATA[13]
MDATA[12]
MDATA[9]
MDATA[8]
MDATA[7]
MDATA[6]
MDATA[5]
MDATA[3]
MDATA[2]
MDATA[1]
MDATA[0]
MVREF_D
1
2
R533
10K
1
2
R534
10K
MDATA[12]
MDATA[13]
MDATA[15]
MDATA[14]
MDATA[8]
MDATA[10]
MDATA[9]
MDATA[11]
MADR[8]
MADR[10]
MADR[9]
MADR[11]
SDO
SCZ
BA0
BA1
1
2
R363
100R
4-16-2008_14:01
6
12
MEMORY INTERFACE
ÖNDER GENÇ
17MB35-1
1
2
R370
100R
SDI
1
2
R369
100R
1
2
R365
100R
1
2
R364
100R
1
2
R362
100R
MDATA[6]
MDATA[5]
MDATA[3]
MDATA[1]
1
2
R104
22R
1
2
R359
100R
MVREF_D
1
2
C212
100N
10V
1
2
F163
60R
1
2
C210
100N
10V
1
2
C204
100N
10V
1
2
C462
220U
6V3
1
2
C461
220U
6V3
MADR[7]
WEZ
MCLKE
MADR[0]
VDDM
VDD_DMQ
VDD_DMC
VDD_DMQ
VDD_DMQ
1
2
R357
100R
2
1
10V
100N
C189
1
2
C193
100N
10V
MDATA[4]
2
1
10V
100N
C202
1
2
C201
100N
10V
1
2
C200
100N
10V
2
1
10V
100N
C199
1
2
C198
100N
10V
2
1
10V
100N
C197
1
2
C196
100N
10V
3V3_VCC
1
2
F126
330R
1
2
100R
R366
1
2
100R
R368
1
2
100R
R367
1
2
3
4
5
6
7
8
U132
MX25L512
DQS[1]
DVB_SPDIF
Summary of Contents for 17MB35
Page 1: ......
Page 6: ......
Page 10: ...3 4 2 Operating Specifications 3 5 Pinning ...
Page 14: ...6 4 Pinning ...
Page 27: ...11 4 Pinning ...
Page 34: ......
Page 57: ...15 18 4 Pinning ...
Page 75: ......
Page 76: ...18 2 Power Management ...
Page 77: ...18 3 Integrated DVB T Receiver Block Diagram ...
Page 78: ...18 4 MSTAR Block Diagram ...