VESTEL 17MB35, Service Manual

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8.4. Pinning
9. IS42S16100C1 SDRAM
9.1. General Description
I SSI’s 16Mb Synchronous DRAM IS42S16100C1 is organized as a 524,288-word x 16-
bit x 2-bank for improved performance. The synchronous DRAMs achieve high-speed
data transfer using pipeline architecture. All inputs and outputs signals refer to the rising
edge of the clock input.
9.2. Features

Clock frequency: 200, 166, 143 MHz

Fully synchronous; all signals referenced to a positive clock edge

Two banks can be operated simultaneously and independently