Special Registers
VL-EPIC-25 Reference Manual
62
I
NTERRUPT
S
TATUS
R
EGISTER
This register is used for reading the status of interrupts generated by the PLD.
IRQSTAT (Read-Status/Write-Clear) CA4h
D7
D6
D5
D4
D3
D2
D1
D0
Reserved
Reserved
Reserved
Reserved
Reserved
ISTAT_TC5 ISTAT_TC4 ISTAT_TC3
Table 30: Interrupt Status Register Bit Assignments
Bit
Mnemonic
Description
D7-D3
Reserved
These bits are reserved. Only write 0 to these bits and ignore all read values.
D2
ISTAT _TC5
Status for the 8254 Timer #5 output (terminal count) Interrupt when read.
0 = Timer output (terminal count) has not transitioned from 0 to a 1 level
1 = Timer output (terminal count) has transitioned from a 0 to a 1 level
This bit is read-status and a write-1-to-clear.
D1
ISTAT _TC4
Status for the 8254 Timer #4 output (terminal count) Interrupt when read.
0 = Timer output (terminal count) has not transitioned from 0 to a 1 level
1 = Timer output (terminal count) has transitioned from a 0 to a 1 level
This bit is read-status and a write-1-to-clear.
D0
ISTAT _TC3
Status for the 8254 Timer #3 output (terminal count) Interrupt when read.
0 = Timer output (terminal count) has not transitioned from 0 to a 1 level
1 = Timer output (terminal count) has transitioned from a 0 to a 1 level
This bit is read-status and a write-1-to-clear.
The interrupt status register is valid whether the interrupt mask is set or not for the interrupt (that
is, it can be used for polled status). An interrupt status is acknowledged (cleared to a 0) by
writing a ‘1’ to the status bit.
The PLD implements an 8254 timer (consisting of three individual timers). The outputs of these
timers can generate interrupts when they transition from a 0 level to a 1 level (edge sensitive).
