Interfaces and Connectors
VL-EPIC-25 Reference Manual
42
Digital I/O
The 40-pin I/O connector (J25) incorporates 16 digital I/O lines. Table 17 shows the function of
each pin. The digital I/O lines are controlled using the SPI registers. See "SPI Registers" for a
complete description of the registers.
The digital lines are grouped into two banks of 16-bit bi-directional ports. The direction of each
8-bit port is controlled by software. The digital I/O lines are powered up in the input mode. The
24 mA source/sink drive and short protected outputs are an excellent choice for industrial
LVTTL interfacing. All I/O pins use +3.3V signaling.
Warning!
Damage may occur if the I/O pins are connected to +5V logic.
Table 17: J25 I/O Connector Pinout
J25
Pin
Signal
VL-CBR-4004
Connector
VL-CBR-4004
Pin (Label)
16
Digital I/O 1
J4
5 (IO13)
17
Digital I/O 2
4 (IO14)
18
Digital I/O 3
3 (IO15)
19
Digital I/O 4
2 (IO16)
20
Ground
1 (GND2)
21
Digital I/O 5
J6
1 (IO17)
22
Digital I/O 6
2 (IO18)
23
Digital I/O 7
3 (IO19)
24
Digital I/O 8
4 (IO20)
25
Ground
5 (GND3/PBRST#)
26
Digital I/O 9
J7
1 (IO21)
27
Digital I/O 10
2 (IO22)
28
Digital I/O 11
3 (IO23)
29
Digital I/O 12
4 (IO24)
30
Ground
5 (GND3)
31
Digital I/O 13
J8
1 (IO25)
32
Digital I/O 14
2 (IO26)
33
Digital I/O 15
3 (IO27)
34
Digital I/O 16
4 (IO28)
35
Ground
5 (GND4)
Note:
Connector J6 pin 5 on the CBR-4004 is labeled "GND3/PBRST#" for
compatibility with other VersaLogic CPU boards. When connected to the Iguana,
this pin is GND3.
D
IGITAL
I/O
P
ORT
C
ONFIGURATION
U
SING THE
SPI
I
NTERFACE
Digital I/O channels 0-15 are accessed via SPI slave select 6 (writing 6h to the SS field in
SPICONTROL). Each pair of I/O ports is configured by a set of paged I/O registers accessible
through SPI. These registers control settings such as signal direction, input polarity, and interrupt
source.
