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Configuration and Setup

VL-EPIC-25 Reference Manual

Figure 1. Typical Start-up Configuration

1. Install Memory



Insert a DDR3 DRAM module into SO-DIMM socket J1 on the bottom of the board and
latch it into place.

2. Attach Cables and Peripherals



Plug the appropriate video cable into the LVDS connector (J3) or the VGA connector
(J2) and attach the monitor.

ATX

Power Supply

SVGA or LVDS

USB Keyboard

and USB Mouse

USB CD-

ROM Drive

OS Installation
CD-ROM

IGUANA

VL-EPIC-25

VL-CBR-2022

J29

VL-CBR-0701

VL-CBR-5013B

J19

J16
J17

J11
J12

VL-CBR-2010 or
VL-CBR-2011

VL-CBR-5013A

SATA

Hard Drive

VL-CBR-0401

VL-CBR-1201

SVGA

LVDS

Summary of Contents for Iguana VL-EPIC-25

Page 1: ...Reference Manual DOC REV 12 6 2013 Iguana VL EPIC 25 Intel Atom based SBC with Ethernet SATA USB eUSB CompactFlash mSATA Serial Industrial I O and SPX ...

Page 2: ...re this document is error free VersaLogic makes no representations or warranties with respect to this product and specifically disclaims any implied warranties of merchantability or fitness for any particular purpose VersaLogic reserves the right to revise this product and associated documentation at any time without obligation to notify anyone of such changes PC 104 and the PC 104 logo are tradem...

Page 3: ...Manual PDF format Device drivers Data sheets and manufacturers links for chips used in this product Photograph of the circuit board BIOS and PLD information and upgrades This is a private page for Iguana users that can be accessed only by entering this address directly It cannot be reached from the VersaLogic homepage The VersaTech KnowledgeBase is an invaluable resource for resolving technical is...

Page 4: ... Setup 8 Operating System Installation 10 BIOS Setup Screens 10 Physical Details 11 Dimensions and Mounting 11 Iguana Dimensions 11 VL CBR 5013 Dimensions 12 VL CBR 4004 Dimensions 13 Hardware Assembly 14 Standoff Locations 14 External Connectors 15 Iguana Connector Locations Top 15 Iguana Connector Locations Bottom 16 Iguana Connector Functions and Interface Cables 17 VL CBR 5013 Connector Locati...

Page 5: ...e 29 Ethernet Connectors 29 Ethernet Status LEDs 29 Status LED 30 SATA Interface 30 Serial Ports 31 COM Port Configuration 31 RS 485 Mode Line Driver Control 31 Serial Port Connectors 32 USB Interface 32 Flash Interfaces 33 CompactFlash 33 eUSB Socket 33 PCIe Mini Card mSATA Socket 33 PCIe Mini Card Wireless Status LEDs 35 Video 36 SVGA Output Connector 36 LVDS Flat Panel Display Connector 37 Audi...

Page 6: ... Resources and Maps 56 Legacy Memory Map 56 I O Map 56 Special Registers 57 PLED and Product Code Register 57 PLD Revision and Type Register 58 BIOS and Jumper Status Register 59 Appendix A References 60 Appendix B Custom Programming 61 PLD Interrupts 61 Interrupt Control Register 61 Interrupt Status Register 62 8254 Timer Control Register 63 A D and D A Control Status Register 64 ...

Page 7: ...nt analog and FPD output capability Intel 3rd generation graphics core 24 bit VGA up to 2048x1536 18 bit LVDS up to 1366x768 SPX interface supports up to four external SPI devices either of user design or any of the SPX series of expansion boards with clock frequencies from 1 8 MHz Two 16 bit counter timers standard three 8254 Programmable Interval Timers custom TVS devices for ESD protection Watc...

Page 8: ... vertical latching connectors one port to the mSATA port Flash Storage eUSB site PCIe Mini Card mSATA site CompactFlash socket Ethernet Interface Two Intel 82574IT based 10BaseT 100BaseTX 1000BaseT Ethernet Controllers USB Eight host USB channels two on board Type A connectors four Type A connectors on VL CBR 5013 paddleboard one on Mini PCIe connector 1 on eUSB header Serial Ports 0 1 RS 232 422 ...

Page 9: ...alog Output 4 SPX Fan Super I O Tach HD Audio Speaker Driver Audio Jacks Speaker Reset Button Power Button PLED LVDS RGB Key DDR3 SMB Electronic Mux SMB PCIe SATA SMB USB 2 0 RTC Monitor Serial SPI SS0 1 2 3 LPC LPC 4 Timer I Os CTC SPI Boot Flash PC 104 PCI Intel 82574IT Intel 82574IT PCIe x1 6 PCIe x1 4 5 SATA 0 SATA 1 PCIe x1 1 PCIe x1 2 IDE I F PCI32 SATA 2 PCIe x1 3 SMB GPIO USB 8 USB 9 USB 0...

Page 10: ...automatically slow down by 50 whenever its die temperature exceeds 100 C When the temperature falls back below 100 C the CPU resumes full speed operation As a failsafe if the CPU die temperature climbs above 105 C the CPU will turn itself off to prevent damage to the chip MODEL DIFFERENCES VersaLogic offers both commercial and industrial temperature models of the VL EPIC 25 The basic operating tem...

Page 11: ...onents The circuit board must only be handled at an ESD workstation If an approved station is not available some measure of protection can be provided by wearing a grounded antistatic wrist strap Keep all plastic away from the board and do not slide the board over any surface After removing the board from its protective wrapper place the board on a grounded static free surface component side up Us...

Page 12: ...edgeBase articles related to the VL EPIC 25 If you have further questions contact VersaLogic Technical Support at 503 747 2261 VersaLogic support engineers are also available via e mail at Support VersaLogic com REPAIR SERVICE If your product requires service you must obtain a Returned Material Authorization RMA number by calling 503 747 2261 Please provide the following information Your name the ...

Page 13: ...ranty repairs are subject to diagnosis and labor charges parts charges and return shipping fees Please specify the shipping method you prefer and provide a purchase order number for invoicing the repair Note Please mark the RMA number clearly on the outside of the box before returning ...

Page 14: ...ing steps outline the procedure for setting up a typical development system The Iguana should be handled at an ESD workstation or while wearing a grounded antistatic wrist strap Before you begin unpack the Iguana and accessories Verify that you received all the items you ordered Inspect the system visually for any damage that may have occurred in shipping Contact Support VersaLogic com immediately...

Page 15: ...ch Cables and Peripherals Plug the appropriate video cable into the LVDS connector J3 or the VGA connector J2 and attach the monitor ATX Power Supply SVGA or LVDS USB Keyboard and USB Mouse USB CD ROM Drive OS Installation CD ROM IGUANA VL EPIC 25 VL CBR 2022 J29 VL CBR 0701 VL CBR 5013B J4 J19 J7 J1 J3 J16 J17 J11 J12 VL CBR 2010 or VL CBR 2011 VL CBR 5013A SATA Hard Drive VL CBR 0401 J1 J2 VL CB...

Page 16: ...the Iguana and peripheral devices 5 Power On Turn on the ATX power supply and the video monitor If the system is correctly configured a video signal should be present There might be a delay of several seconds before the video signal becomes present If video does not appear press the Power Button on the paddleboard 6 Install Operating System Install the OS according to the instructions provided by ...

Page 17: ... The VL EPIC 25 complies with EPIC dimensional standards Dimensions are given below to help with pre production planning and layout Figure 2 Iguana Dimensions and Mounting Holes Not to scale All dimensions in inches 3 3 6 096 4 128 4 328 2 596 5 496 0 200 5 596 2 446 0 000 3 375 0 200 0 000 ...

Page 18: ...Physical Details VL EPIC 25 Reference Manual 12 VL CBR 5013 DIMENSIONS Figure 3 VL CBR 5013 Dimensions and Mounting Holes Not to scale All dimensions in inches 1 95 1 57 5 50 5 10 1 17 1 24 0 065 ...

Page 19: ...VL EPIC 25 Reference Manual 13 VL CBR 4004 DIMENSIONS Figure 4 VL CBR 4004 Dimensions and Mounting Holes Not to scale All dimensions in inches J1 J2 J3 J4 J6 J7 J8 J9 J5 2 38 2 87 0 25 0 25 0 40 1 95 0 70 0 63 0 62 0 06 ...

Page 20: ...st be used under the stack These are secured with four male female standoffs C threaded from the top side which also serve as mounting struts for the PC 104 stack Standoffs are secured to the top circuit board using pan head screws Four standoffs and screws are available as part number VL HDW 106 Note A minimum height clearance of 8 5mm is required beneath the board to avoid contacting the tallest...

Page 21: ...P Figure 6 Connector Locations Top J27 SPX J28 External Ethernet LED J3 LVDS J22 Ethernet 1 J7 J8 ISA J6 PCI J16 J17 J16 USB0 J17 USB1 J19 User I O J29 Power J25 Digital Analog Timers ICH8M J13 PCIe Mini Card or mSATA J20 Ethernet 0 J11 SATA0 J12 SATA1 J2 VGA J18 eUSB J11 J12 DCBA B A C D Atom CPU ...

Page 22: ...Physical Details VL EPIC 25 Reference Manual 16 IGUANA CONNECTOR LOCATIONS BOTTOM Figure 7 Connector Locations Bottom J9 CompactFlash J1 SODIMM ...

Page 23: ... 793 J12 SATA Standard SATA VL CBR 0701 VL CBR 0401 500 mm 19 75 7 pin straight to straight SATA data ATX to SATA power adapter 30 4 187 3 793 J13 PCIe Mini Card mSATA 33 1 514 2 533 J16 USB 1 Standard USB Type A 32 3 805 4 120 J17 USB 2 Standard USB Type A 32 4 128 4 120 J18 eUSB Flash Drive 33 2 809 5 102 J19 COM ports USB PLED power LED push button reset power button audio jacks PC speaker Oupi...

Page 24: ...tor FCI 98414 F06 50ULF 2 mm 50 pin keyed header J5 COM2 Conta Clip 10250 4 5 pin screw terminal J6 COM3 Conta Clip 10250 4 5 pin screw terminal J7 USB1 USB2 USB Type A USB Host J8 External Reset and Power Buttons Conta Clip 10250 4 3 pin screw terminal D1 PLED Top Power LED Bottom LED S1 Power Button Pushbutton S2 Reset Button Pushbutton SP1 Speaker Piezo speaker J7 USB1 Top USB2 Bottom J3 Audio ...

Page 25: ...Physical Details VL EPIC 25 Reference Manual 19 VL CBR 4004 CONNECTOR LOCATIONS Figure 9 VL CBR 4004 Connectors 2 1 40 39 J1 J2 J3 J4 J6 J7 J8 J9 5 1 5 1 5 1 5 1 1 5 1 5 1 5 1 5 Pin 1 J5 ...

Page 26: ... Details VL EPIC 25 Reference Manual 20 Jumper Blocks JUMPERS AS SHIPPED CONFIGURATION Figure 10 Jumper Block Locations V4 V5 V1 V1 V7 V2 V6 V4 V5 1 2 3 V6 V3 V2 V3 1 2 3 2 4 6 8 1 3 5 7 1 2 2 1 2 1 3 4 V7 2 1 ...

Page 27: ...x endpoint termination Out RS 232 Out 31 V4 3 4 COM1 configuration In RS 485 Rx endpoint termination Out RS 232 Out 31 V4 5 6 COM2 configuration In RS 485 Rx endpoint termination Out RS 232 Out 31 V4 7 8 COM3 configuration In RS 485 Rx endpoint termination Out RS 232 Out 31 V5 1 2 BIOS Select In Secondary BIOS Out Primary BIOS Out 59 V5 3 4 General Purpose Input Bit 1 In Bit D7 in GPI register rea...

Page 28: ...SB 5V Stand By signal Since the EBX 11 does not support soft off pin 6 is an internal no connect Note The 3 3 VDC 12 VDC and 12 VDC inputs are necessary for expansion modules that require these voltages POWER REQUIREMENTS The Iguana requires only 5V 5 for proper operation Initial power up typically requires 4 85V due to 0 1V of input voltage monitoring hysteresis The higher voltages required for t...

Page 29: ... between the power source and the power connector Implement the remote sense feature on your power supply if it has one Connect the remote sense lines in tandem with one of the power input and ground pins This is done at the connector to compensate for losses in the power wires Use a high quality power supply that can supply a stable voltage while reacting to widely varying current draws LITHIUM B...

Page 30: ...x 512 kB 8 way L2 cache for D500 dual core processor 1 x 512 kB 8 way L2 cache for D400 single core processor Processor memory features include Support for DDR3 at data transfer rate of 800 MT s I O Voltage of 1 5 V for DDR3 Integrated graphics features include The GPU contains a refresh of the 3rd generation graphics core Intel Dynamic Video Memory Technology support 4 0 Directx 9 compliant Pixel...

Page 31: ...al time clock calendar chip Under normal battery conditions the clock maintains accurate timekeeping functions when the board is powered off The accuracy of the RTC clock is 20 ppm parts per million at 25 C which equates to approximately 1 7 seconds per day of clock drift error 20 ppm is the crystal frequency accuracy The RTC accuracy varies with temperature The approximate clock accuracy at any t...

Page 32: ...ection The Iguana can be configured for remote access by redirecting the console to a serial communications port The BIOS setup utility and some operating systems such as DOS can use this console for user interaction Console redirection settings are configured in the Serial Port Console Redirection BIOS setup screen Console redirection is disabled by default Console redirection can be disabled or ...

Page 33: ...ecification and can support four bus master capable PC 104 Plus modules The BIOS automatically allocates I O and memory resources However manual PCI Interrupt routing is used The following table shows the maximum PC 104 Plus slot power on the Iguana Table 5 Maximum PC 104 Plus Slot Power Voltage Max Current 5V 8A 3 3V 4A 12V 1A 12V 0 5A PC 104 ISA The Iguana provides full support of the PC 104 bus...

Page 34: ...CFA 0xCFB 0x03E 0x03F 0x0B6 0x0B7 0x377 0x3BF 0xD00 0x043 0x04D 0x0BA 0x0BB 0x3E0 0x3E7 0x053 0x05F 0x0BE 0x0BF 0x3F0 0x3F5 Available base I O addresses for COM ports are 2E8h 2F8h 3E8h 3F8h PC 104 MEMORY SUPPORT The following memory addresses are available on the ISA bus 0xA0000 0xB7FFF 0xD0000 0xDFFFF PC 104 IRQ SUPPORT Interrupts are routed automatically though manual routing control may be add...

Page 35: ...ounted RJ45 connectors are provided to make connection with Category 5 or 6 Ethernet cables The 82574IT Ethernet controller auto negotiates connection speed These interfaces use IEC 61000 4 2 rated TVS components to help protect against ESD damage ETHERNET STATUS LEDS On board status LEDs are provided at locations D7 single yellow and D8 dual green yellow for Ethernet 0 and D9 single yellow and D1...

Page 36: ...d pin 20 on custom models SATA Interface The Iguana provides two serial ATA SATA ports which communicate at a rate of up to 3 0 GB s SATA 2 The SATA connectors at locations J11 and J12 are standard 7 pin straight SATA connectors with friction latching Power to SATA drives is supplied by the ATX power supply Note that the standard SATA drive power connector is different than the common 4 pin Molex ...

Page 37: ...per block V4 is used to configure serial ports for RS 422 485 operation See Jumper Summary for details The termination resistor should be enabled for RS 422 and the RS 485 endpoint stations It should be disabled for RS 232 and RS 485 intermediate stations If RS 485 mode is used the differential twisted pair TxD RxD and TxD RxD is formed by connecting both transmit and receive pairs together For ex...

Page 38: ...D 8 8 CTS RxD RxD 9 9 Table 10 COM2 3 Pinout VL CBR 5013 Connectors J5 6 COM2 COM3 J5 Pin J6 Pin RS 232 RS 422 RS 485 1 1 Ground Ground Ground 2 2 RXD RxD RxD 3 3 CTS RxD RxD 4 4 TXD TxD TxD 5 5 RTS TxD TxD USB Interface The USB interface on the Iguana is UHCI Universal Host Controller Interface and EHCI Enhanced Host Controller Interface compatible which provides a common industry software hardwa...

Page 39: ... available in quantities of 10 in the VL HDW 108 hardware kit from VersaLogic Table 11 eUSB Port Locations J18 Pin Signal Name Function 1 5V 5V Power Supply 2 NC Not connected 3 D Data 4 NC Not connected 5 D Data 6 NC Not connected 7 GND Ground 8 NC Not connected 9 Key Physical key 10 LED SSD LED The blue LED at location D6 upper right corner of the board as shown in Figure 7 lights with activity ...

Page 40: ... connected Reserved Not connected 13 REFCLK Reference clock input Reserved Not connected 14 NC Not connected Reserved Not connected 15 GND Ground GND Ground 16 NC Not connected Reserved Not connected 17 NC Not connected Reserved Not connected 18 GND Ground GND Ground 19 NC Not connected Reserved Not connected 20 W_DISABLE Wireless disable 1 Reserved Not connected 21 GND Ground GND Ground 22 PERST ...

Page 41: ...28 2 This pin is not grounded on the Iguana since it can be used to detect the presence of an mSATA module versus a PCIe Mini Card Grounding this pin is available as an option on custom boards 3 This pin is not grounded on the Iguana to make it available for mSATA module detection 4 This signal drives the blue LED activity indicator at location D11 upper right corner of the board as shown in Figur...

Page 42: ...ideo output SVGA and LVDS Flat Panel Display SVGA OUTPUT CONNECTOR An adapter cable part number VL CBR 1201 is available to translate J2 into a standard 15 pin D Sub SVGA connector This connector is protected against ESD damage Table 13 Video Output Pinout J2 Pin Signal Name Function Mini DB15 Pin 1 GND Ground 6 2 RED Red Video 1 3 GND Ground 7 4 GREEN Green Video 2 5 GND Ground 8 6 BLUE Blue Vide...

Page 43: ...tempting to use contact Support VersaLogic com for a custom video BIOS Table 14 LVDS Flat Panel Display Pinout J3 Pin Signal Name Function 1 GND Ground 2 NC Not Connected 3 NC Not Connected 4 NC Not Connected 5 GND Ground 6 LVDSCLK0 Differential Clock 7 LVDSCLK0 Differential Clock 8 GND Ground 9 LVDSA2 Diff Data 2 10 LVDSA2 Diff Data 2 11 GND Ground 12 LVDSA1 Diff Data 1 13 LVDSA1 Diff Data 1 14 G...

Page 44: ... line level stereo input and line level stereo output connection points The outputs will drive most amplified PC speaker sets The following table shows the pinout of the audio connector J3 on the VL CBR 5013 breakout board Table 15 VL CBR 5013 J3 Audio Connector Pinout J3 Pin Signal Name Function 1 LINE_INL Line In Left 2 LINE_INR Line In Right 3 HDA_GND HDA Ground 4 LINE_OUTL Line Out Left 5 LINE...

Page 45: ...4 5 5 0V 4 Ground Ground 29 Data 5 TXD TxD 30 Data 6 RTS TxD 31 USB 6 USB6 7 5 0V 7 COM1 Ground Ground 32 Data 8 J2 RXD RxD 33 Data 9 Bottom DB9 CTS RxD 34 USB 7 USB6 7 5 0V 10 Ground Ground 35 Data 11 TXD TxD 36 Data 12 RTS TxD 37 5 0V Protected 13 COM2 Ground Ground 38 D1 Programmable LED 14 J5 RXD RxD 39 SP1 Speaker 15 CTS RxD 40 S2 J8 Pin 1 Pushbutton Reset 16 Ground Ground 41 S1 J8 Pin 3 Powe...

Page 46: ...ower button is provided on the VL CBR 5013 breakout board Terminal block J8 also provides a power button signal on pin 3 and ground on pin 2 In configurations where a power button is not connected to the board if the system is put into an S5 state power can be restored by turning off the power supply and turning it back on This behavior is set by default by the BIOS The behavior can be changed usi...

Page 47: ...he register make sure not to alter the value of the other bits The following code examples show how to turn the LED on and off LED On LED Off MOV DX CA0H MOV DX CA0H IN AL DX IN AL DX OR AL 80H AND AL 7FH OUT DX AL OUT DX AL POWER LED The power LED on the VL CBR 5013 indicates that the paddle board is being powered by the 5V supply though it does not indicate that all S0 power supplies are good Th...

Page 48: ...Label 16 Digital I O 1 J4 5 IO13 17 Digital I O 2 4 IO14 18 Digital I O 3 3 IO15 19 Digital I O 4 2 IO16 20 Ground 1 GND2 21 Digital I O 5 J6 1 IO17 22 Digital I O 6 2 IO18 23 Digital I O 7 3 IO19 24 Digital I O 8 4 IO20 25 Ground 5 GND3 PBRST 26 Digital I O 9 J7 1 IO21 27 Digital I O 10 2 IO22 28 Digital I O 11 3 IO23 29 Digital I O 12 4 IO24 30 Ground 5 GND3 31 Digital I O 13 J8 1 IO25 32 Digita...

Page 49: ...lizes the on board digital I O chips at boot time MOV DX CA8h MOV AL 26h SPICONTROL SPI Mode 00 24bit auto SPI 6 OUT DX AL MOV DX CA9h MOV AL 30h SPISTATUS 8MHz no IRQ left shift OUT DX AL MOV DX CABh MOV AL 44h SPIDATA1 Mirror Open Drain interrupts OUT DX AL MOV DX CACh MOV AL 0Ah SPIDATA2 MCP23S17 address 0x0A OUT DX AL MOV DX CADh MOV AL 40h SPIDATA3 MCP23S17 write command OUT DX AL BUSY MOV DX...

Page 50: ...ress 00h OUT DX AL MOV DX CADh MOV AL 40h SPIDATA3 MCP23S17 write command OUT DX AL CALL BUSY Poll busy flag to wait for SPI transaction Write 55h to MCP23S17 register GPIOA MOV DX CABh MOV AL 55h SPIDATA1 data to write OUT DX AL MOV DX CACh MOV AL 14h SPIDATA2 MCP23S17 register address 14h OUT DX AL MOV DX CADh MOV AL 40h SPIDATA3 MCP23S17 write command OUT DX AL CALL BUSY Poll busy flag to wait ...

Page 51: ...ction OUT SPICONTROL2 H30 INITIALIZE MCP23S17 MCP23S17 IOCON Register D7 BANK 0 Registers in same bank addresses are sequential D6 MIRROR 1 The INT pins are internally connected D5 SEQOP 0 Sequential op disabled Addr ptr does not increment D4 DISSLW 0 Slew rate control for SDA output enabled D3 HAEN 0 Hardware address enable addr pins disabled D2 ODR 1 INT pin is open drain D1 INTPOL 0 Polarity of...

Page 52: ...ddress OUT SPIDATA2 H0 MCP23S17 SPI Control Byte Write OUT SPIDATA3 H40 WHILE INP SPISTATUS AND H1 H1 WEND Repeat until ESC key is pressed WHILE INKEY CHR 27 READ DIO INPUT DATA FROM MCP23S17 MCP23S17 GPIOA Register Address OUT SPIDATA2 H12 MCP23S17 SPI Control Byte Read OUT SPIDATA3 H41 WHILE INP SPISTATUS AND H1 H1 WEND DIO Input Data PRINT HEX INP SPIDATA1 WEND SYSTEM ...

Page 53: ...a complete description of the registers See the Linear Technology LTC1857 A D Converter Datasheet for programming information Warning Application of analog voltages greater than 25V or less than 25V can damage the converter EXTERNAL CONNECTIONS Single ended analog voltages are applied to connectors J1 and J2 of the VL CBR 4004 board connected to J25 of the Iguana as shown in the following table Ta...

Page 54: ...o bits 3 2 of SPIDATA3 I O address CADh Any write operation to this register triggers an SPI transaction The 2 bit input range codes are 0 5V 1 10V 2 0 to 5V or 3 0 to 10V Set bit 7 if you wish your conversion to be for a single ended channel For example if converting the 4th A D channel channel number 3 with a 0 to 5V range as a single channel then SPIDATA3 is set to d8h 5 Poll the SPI BUSY bit i...

Page 55: ...7h to the SPICONTROL register I O address CA8h This value configures the SPI port to select the D A converter 24 bit frame length low SCLK idle state rising edge SCLK edge and automatic slave select 2 Write 30h to the SPISTATUS register I O address CA9h This value selects 8 MHz SCLK speed hardware IRQ disable and left shift data 3 Write the LS 4 bits of the 12 bit output value into the MS 4 bits o...

Page 56: ...ctor VL CBR 4004 Pin Label 36 Output OCTC3 Timer 3 Counter Output J9 1 IO29 37 Input ICTC3 Timer 3 Clock Input 2 IO30 38 Output OCTC4 Timer 4 Counter Output 3 IO31 39 Input ICTC4 Timer 4 Clock Input 4 IO32 40 GND Ground 5 GND4 Relative to VL EPIC 25 The Custom Programming appendix discusses how to use and configure these timers using the following registers Register Read Write Address Name IRQCTRL...

Page 57: ...e Data In and Data Out with respect to the Master The SPX implementation adds additional features such as chip selects and an interrupt input to the Master The Master device initiates all SPI transactions A slave device responds when its Chip Select is asserted and it receives Clock pulses from the Master The SPI clock rate can be software configured to operate at speeds between 1 MHz and 8 MHz Pl...

Page 58: ...f SPX modules that provide a variety of standard functions such as analog input digital I O CANbus controller and others These are small boards 1 2 x 3 78 that can mount on the PC 104 stack using standard standoffs or up to two feet away from the baseboard For more information contact VersaLogic at info VersaLogic com ...

Page 59: ...nd auto slave select modes SPILEN1 SPILEN0 Frame Length 0 0 8 bit 0 1 16 bit 1 0 24 bit 1 1 32 bit D3 MAN_SS SPI Manual Slave Select Mode This bit determines whether the slave select lines are controlled through the user software or are automatically controlled by a write operation to SPIDATA3 CADh If MAN_SS 0 then the slave select operates automatically if MAN_SS 1 then the slave select line is c...

Page 60: ...SEL by an SPI device 0 SPI IRQ disabled default 1 SPI IRQ enabled Note The selected IRQ is shared with PC 104 ISA bus devices CMOS settings must be configured for the desired ISA IRQ D2 LSBIT_1ST SPI Shift Direction Controls the SPI shift direction of the SPIDATA registers The direction can be shifted toward the least significant bit or the most significant bit 0 SPIDATA data is left shifted MSbit...

Page 61: ...ord for example the LSB of a 24 bit frame would be SPIDATA1 Data is sent according to the LSBIT_1ST setting When LSBIT_1ST 0 the MSbit of SPIDATA3 is sent first and received data will be shifted into the LSbit of the selected frame size set in the SPILEN field When LSBIT_1ST 1 the LSbit of the selected frame size is sent first and the received data will be shifted into the MSbit of SPIDATA3 Data r...

Page 62: ...ing care to avoid the devices already in the map as shown below Table 25 On Board I O Devices I O Device Standard I O Addresses Reserved CB4h CBFh PLD Internal 8254 Timers CB0h CB3h ADC DAC Control Status Register CAFh mSATA PCIe Mux Control Register CAEh SPI Data Register 3 CADh SPI Data Register 2 CACh SPI Data Register 1 CABh SPI Data Register 0 CAAh SPI Status Register CA9h SPI Control Registe...

Page 63: ... Bit Assignments Bit Mnemonic Description D7 PLED Light Emitting Diode Controls the programmable LED on connector J7 0 Turns LED off 1 Turns LED on D6 D0 PC Product Code These bits are hard coded to represent the product type The Iguana always reads as 0000011 Other codes are reserved for future products PC6 PC5 PC4 PC3 PC2 PC1 PC0 Product Code 0 0 0 1 0 1 1 VL EPIC 25 These bits are read only 7 7...

Page 64: ...code revision PLD4 PLD3 PLD2 PLD1 PLD0 Revision 0 0 0 0 0 Rev 0 10B 0 0 0 0 1 Rev 0 10B 0 0 0 1 0 Rev 0 20A 0 0 0 1 1 Rev 1 00A 0 0 1 0 0 Rev 1 01A These bits are read only Note For beta boards the Revision Level is set to 1 00A but the Production Level is set to Beta D2 Reserved This bit is reserved D1 CUSTOM PLD Class This bit indicates whether the PLD code is standard or customized 0 Standard P...

Page 65: ...OS selected 1 No jumper installed primary system BIOS selected This bit is read only D6 BIOS_OR BIOS Jumper Override Overrides the system BIOS selector jumper and selects the BIOS with BIOS_SEL 0 No BIOS override 1 BIOS override D5 BIOS_SEL BIOS Select Selects the system BIOS when BIOS_OR is set 0 Backup BIOS selected 1 Primary BIOS selected D4 D2 Reserved These bits are reserved Only write 0 to t...

Page 66: ... Intel Atom Datasheet Vol 1 and Vol 2 Chipset Intel ICH8 Intel ICH8 Datasheet Super I O Chip SMSC SCH3114 SCH3114 Datasheet Ethernet Controller Intel 82574IT Ethernet Controller Intel 8257IT Datasheet PC 104 Interface PC 104 Specification PC 104 Plus Interface PC 104 Plus Specification A ...

Page 67: ...Enable interrupt D6 D5 IRQSEL 2 0 Specifies the interrupt mapping this setting is ignored when IRQEN 0 interrupts are disabled 000 IRQ3 default 001 IRQ4 010 IRQ5 011 IRQ10 100 IRQ6 101 IRQ7 110 IRQ9 111 IRQ11 D4 Reserved These bits are reserved Only write 0 to these bits and ignore all read values D2 IMASK_TC5 Mask for the 8254 Timer 5 output terminal count Interrupt 0 Disable interrupt 1 Enable i...

Page 68: ..._TC4 Status for the 8254 Timer 4 output terminal count Interrupt when read 0 Timer output terminal count has not transitioned from 0 to a 1 level 1 Timer output terminal count has transitioned from a 0 to a 1 level This bit is read status and a write 1 to clear D0 ISTAT _TC3 Status for the 8254 Timer 3 output terminal count Interrupt when read 0 Timer output terminal count has not transitioned fro...

Page 69: ...7 MHz internal clock PCI clock divided by 8 1 Timer 4 input clock is from User I O connector Input ICTC4 D2 TM3SEL Configure the clock source for 8254 Timer 3 0 Timer 3 input clock is 4 167 MHz internal clock PCI clock divided by 8 1 Timer 3 input clock is from User I O connector Input ICTC3 D1 D0 Reserved These bits are reserved Only write 0 to these bits and ignore all read values An 8254 timer ...

Page 70: ...allow for three clock inputs and four timer outputs as well as three timer gate inputs for all three 16 bit timers by using some of the digital I O signal pins on J25 A D and D A Control Status Register This register is used to control A D and D A conversion ADCONSTAT Read Write CAFh D7 D6 D5 D4 D3 D2 D1 D0 Reserved Reserved Reserved DACLDA0 Reserved ADCBUSY0 Reserved ADCONVST0 Table 32 A D D A Co...

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