VersaLogic Blackbird VL-EPU4562, Reference Manual, Page: 30 / 47

FPGA Registers
EPU-4562 Programmer’s Reference Manual 25
Table 27: DIOISTAT2 – Digital I/O 16-9 Interrupt Mask Register
Bits Identifier Access Default Description
7-0 ISTAT_DIO[16:9]
RW/C
N/A
DIOx interrupt status. A read returns the interrupt status. Writing
a ‘1’ clears the interrupt status.
This bit is set to a ‘1’ on a transition from low-to-high
(POL_DIOx=0) or high-to-low (POL_DIOx=1).
DIOCR – Digital I/O Control Register
One interrupt can be generated for the 16 digital I/Os. Reset type is Platform.
Table 28: DIOCR – Digital I/O Control Register
Bits Identifier Access Default Description
7 IRQEN
R/W
0
DIO interrupt enable/disable:
0 – Interrupts disabled
1 – Interrupts enabled
6-4 IRQSEL(2:0)
R/W
000
DIO interrupt IRQ select in LPC SERIRQ:
000 – IRQ3
001 – IRQ4
010 – IRQ5
011 – IRQ10
100 – IRQ6
101 – IRQ7
110 – IRQ9
111 – IRQ11
3-1 RESERVED
RO
000 Reserved. Writes are ignored; reads always return 0.
0 TMREN
R/W
0
Timer enable signals (used to switch digital I/Os to timer control
signals):
0 – Timers disabled
1 – Timers enabled and some DIOs are used based on the
TMRFULL setting in the Timer control register (TCR)