VersaLogic Blackbird VL-EPU4562, Reference Manual, Page: 29 / 47

FPGA Registers
EPU-4562 Programmer’s Reference Manual 24
Table 22: DIOIN1 – Digital I/O 8-1 Input Status Register
Bits Identifier Access Default Description
7-0 IN_DIO[8:1]
RO
N/A
Reads the DIO input status. For each bit:
0 – Input de-asserted if polarity not-inverted;
asserted if polarity inverted
1 Input asserted if polarity not-inverted;
de-asserted if polarity inverted
Table 23: DIOIN2 – Digital I/O 16-9 Input Status Register
Bits Identifier Access Default Description
7-0 IN_DIO[16:9]
RO
N/A
Reads the DIO input status. For each bit:
0 – Input de-asserted if polarity not-inverted;
asserted if polarity inverted
1 Input asserted if polarity not-inverted;
de-asserted if polarity inverted
DIOIMASKx (x=1,2) – Digital I/O Interrupt Mask Registers
These two registers are the interrupt mask registers for the digital IOs. The reset type is Platform
Reset because interrupts always have to be setup after exiting sleep states.
Table 24: DIOIMASK1 – Digital I/O 8-1 Interrupt Mask Register
Bits Identifier Access Default Description
7-0 IMASK_DIO[8:1]
R/W
0
Digital I/O 8-1 interrupt mask. For each bit:
0 – Interrupt disabled
1 – Interrupt enabled
Table 25: DIOIMASK2 – Digital I/O 16-9 Interrupt Mask Register
Bits Identifier Access Default Description
7-0 IMASK_DIO[16:9]
R/W
0
Digital I/O 16-9 interrupt mask. For each bit:
0 – Interrupt disabled
1 – Interrupt enabled
DIOISTATx (x=1,2) – Digital I/O Interrupt Status Registers
Table 26: DIOISTAT1 – Digital I/O 8-1 Interrupt Mask Register
Bits Identifier Access Default Description
7-0 ISTAT_DIO[8:1]
RW/C
N/A
DIOx interrupt status. A read returns the interrupt status. Writing
a ‘1’ clears the interrupt status.
This bit is set to a ‘1’ on a transition from low-to-high
(POL_DIOx=0) or high-to-low (POL_DIOx=1).