FPGA Registers
EPU-4562 Programmer’s Reference Manual
19
SPISTATUS
The SPX interrupt is not connected on this product. The control bits and status associated are
still defined in the register set but the SPX interrupt will always be de-asserted.
Table 14: SPI Interface Status Register
Bits
Identifier
Access
Default
Description
7-6
IRQSEL[1:0]
R/W
00
The SPX interrupt is not connected on this product (always de-
asserted).
Selects which IRQ will be enabled if HW_IRQ_EN = 1. Interrupts are
not used on this board, so this just becomes a read/write non-
functional field.
00 – IRQ3
01 – IRQ4
10 – IRQ5
11 – IRQ10
Note:
These are the first four interrupts in the “usual” LPC SERIRQ
group of eight interrupts.
5-4
SPICLK(1:0)
R/W
00
Selects one of four SCLK frequencies. This is based on a 33 MHz
LPC clock.
00 – 0.75Mhz(24Mhz/32)
01 – 1.5 Mhz(24Mhz/16)
10 – 2 Mhz(24 Mhz/8)
11 – 6 Mhz (24Mhz/4)
3
HW_IRQ_EN
R/W
0
The SPX interrupt is not connected on this product (always de-
asserted).
This enables the selected IRQ to be activated by a SPI device that is
configured to use its interrupt capability.
0 - IRQs are disabled for SPI operations.
1 - The IRQ can be asserted
2
LSBIT_1ST
R/W
0
Controls the SPI shift direction from the SPIDATA(x) registers.
0 - Data is left-shifted (MSB first).
1 - Data is right-shifted (LSB first)
1
HW_INT
RO
0
SPX interrupt is not connected on this product (always de-asserted).
Status flag which indicates when the hardware SPX signal SINT# is
asserted.
0 - The hardware interrupt SINT# is de-asserted.
1 - An interrupt is present on SINT#
If HW_IRQ_EN= 1, the selected IRQ will also be asserted by the
hardware interrupt. HW_INT is read-only and is cleared when the
external hardware interrupt is no longer present.
0
BUSY
RO
N/A
Status flag which indicates when an SPI transaction is underway. I
2
C
is so slow that there is no reason to ever poll this.
0 - The SPI bus is idle.
1 - SCLK is clocking data in/out of the SPIDATA(x) registers (that is,
busy)