VAR-320SBC Reference Guide
Copyright © 2008 Variscite
35
42
N.C.
n/a
43 V_BATT
n/a
44
N.C.
n/a
45 L_DD_14
O
LCD Data line
69
46 BACKUP
BATTERY
O
Backup battery charger output
n/a
47 L_DD_15
O
LCD Data line
70
48 BACKUP
BATTERY
O
Backup battery charger output
n/a
49 nXCVREN
O
External transceiver enable, Data flash interface.
n/a
50 GND
n/a
51 DF_CLE_NOE
Output enable for static memory, muxed with DF CLE.
n/a
52
N.C.
n/a
53 DF_ALE_NWE O
Output write enable for static memory, muxed with DF ALE
n/a
54 SSP4_SCLK
I/O
Synchronous Serial Protocol Serial Clock
93
55 V_BATT
n/a
56 SSP4_SFRM
I/O
Synchronous Serial Protocol Serial Frame Indicator
94
57 DF_BA_0
O
DFI bus address 0
n/a
58 SSP4_TXD
O
Synchronous Serial Protocol Transmit Data
95
59 DF_BA_1
O
DFI bus address 1
n/a
60 SSP4_RXD
I
Synchronous Serial Protocol Receive Data
96
61 DF_BA_2
O
DFI bus address 2
n/a
62 GND
63 DF_BA_3
O
DFI bus address 3
n/a
64 USBH_N
I/O
USB Full Speed Host Port 1 Positive Line
n/a
65
N.C.
n/a
66 USBH_P
I/O
USB Full Speed Host Port 1 Negative Line
n/a
67 V_BATT
n/a
68 USBH_PEN
USB Full speed host power control.
2_2
69 LLA_N
O
Lower address latch
n/a
70 USBH_OVERC
USB Full speed host over currant indicator
3_2
71 LUA_N
O
Upper address latch
n/a
72 BE0_N
O
Data byte enable. BE0_N corresponds to DF_IO<0:7>
n/a
73 RESET_N
I
PMU Reset
n/a
74 GND
n/a
75
N.C.
n/a
76
N.C.
n/a
77
N.C.
n/a
78
N.C.
n/a
79 V_BATT
n/a
80 BE1_N
O
Data byte enable. BE1_N corresponds to DF_IO<8:15>
n/a
81
N.C.
n/a
82 HP_LOUT
Headphones, Right.
n/a
83 CF_nPIOR
O
CF Card interface I/O space output enable
5
84 HP_ROUT
O
Headphones, Left.
n/a
85 CF_nPIOW
O
CF Card interface I/O space write enable
6
86 GND
n/a
87 CF_nIOIS16
I
CF interface. 0 = 16-bit I/O space, 1 = 8-bit I/O space
7
88 TSPX
I/O
TSI interface X Plus
n/a
89 CF_nPWAIT
I
Card interface input for inserting wait states.
8
