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Variscite VAR-320SBC, Reference Manual

The VAR-320SBC Reference Manual is a comprehensive guide for the Variscite VAR-320SBC product, providing detailed instructions and information on its features and functionalities. This manual is available for free download from manualshive.com, allowing users to easily access and navigate through it.

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VAR-320SBC Reference Guide

 

 

Copyright © 2008 Variscite 

4.6. JTAG  Port 

JTAG provides a way of driving and sampling the external pins of the device regardless of the 
core state, as well as a mechanism for device debug. JTAG logic includes a test-access port 
(TAP) controller, TAP pins, an instruction register, and Test Data registers (TDRs). The JTAG 
interface is controlled through five dedicated TAP pins that interface to the TAP controller: TDI, 
TMS, TCK, nTRST, and TDO. 
 

 

Signal 

Pin number  Type 

Description 

NTRST P2-128 

I 

JTAG 

Test 

Reset 

TDI 

P2-130 

I 

JTAG Serial data input 

TMS P2-132  I  JTAG 

Test Mode Select 

TDO 

P2-136 

O 

JTAG Serial data output 

TCK P2-138  I  JTAG 

Test 

Clock 

19  

 

Summary of Contents for VAR-320SBC

Page 1: ...V VA AR R 3 32 20 0S SB BC C M Ma ar rv ve el ll l M Mo on na ah ha an ns s P P P PX XA A3 32 20 0 b ba as se ed d S Si in ng gl le e B Bo oa ar rd d C Co om mp pu ut te er r ...

Page 2: ...timedia co processor 11 3 1 4 Power Management 11 3 2 Memory 12 3 2 1 266MHZ 32bit DDR SDRAM 12 3 2 2 NAND flash 12 3 3 Power Management IC National LP3972 12 3 4 Wi2Wi WS2W0001 WIFI module 12 3 5 Davicom DM9000BEthernet controller 12 3 6 Connectors to base board 13 4 Interfaces 13 4 1 TouchScreen 13 4 2 SSP Interface 15 4 3 UART Ports 16 4 4 SD MMC Ports 17 4 5 LCD Interface 17 4 6 JTAG Port 19 4...

Page 3: ...ic Memory interface Compact Flash Nand flash host bus SRAM VLIO 25 4 13 Power 27 4 14 Audio 28 4 15 I2C Bus 29 5 Power supply and management 30 5 1 Power Supply 30 5 2 Power consumption 30 6 Connectors 31 6 1 P1 31 6 2 P2 34 7 Operational Characteristics 38 7 1 Absolute Maximum Rating Error Bookmark not defined 8 Mechanical drawing 39 SBC Height including BaseBoard connectors 9mm 39 40 9 Legal not...

Page 4: ...ce Guide Copyright 2008 Variscite 4 1 Revision History Revision No Draft Date Remarks 1 0 31 Aug 2007 Initial draft 1 1 20 Sept 2007 Ethernet controller revised 2 0 11 Feb 2008 Mechanical change Smaller form factor 6x4cm ...

Page 5: ...and easily integrates into any embedded solution It includes all vital peripherals interfaces and is ready to run any embedded operating system such as Linux WinCE and Windows Mobile Supporting products Windows CE 5 0 6 0 BSP Contact support for further information VAR 3xxBASEBOARD Evaluation board Package includes 9 Base board Compatible with VAR 320SBC 9 Windows CE 5 0 6 0 run time image 9 Schem...

Page 6: ...sh Disk 802 11 b g WIFI module Built In CRT LCD interface Using 2 D graphic accelerator Up to 800x600 resolution supported 2 SDcard SDIO MMC card interfaces A D Up to 7 channels 10KHZ 10Bit resolution Power National LP3972 management IC Supports SpeedStep technology to achieve the most efficient power consumption Lowest power solution down to 3mw in sleep mode Single 3 3 4 8V DC power supply Compa...

Page 7: ...00 Mbit Ethernet controller General purpose I O lines Audio HI FI stereo decoder Voice CODEC Mono output for Speaker Microphone input Headphones output USB 1 x full USB host interface 1 x USB Client interface Connects to an external USB 2 0 host controller Touch Screen interface Serial controller 2 x SSP interfaces 1 Wire I2C ...

Page 8: ...VAR 320SBC Reference Guide Copyright 2008 Variscite 2 3 Block Diagram 8 ...

Page 9: ... architecture with on the fly voltage and frequency scaling and sophisticated power management to provide industry leading MIPS mW performance across its wide range of operating frequencies The PXA320 processor complies with the ARM Architecture V5TE instruction set excluding floating point instructions and follows the ARM programmer s model The PXA320 processor Multimedia coprocessor provides enh...

Page 10: ...VAR 320SBC Reference Guide Copyright 2008 Variscite 3 1 2 Monahans P Block Diagram 10 ...

Page 11: ...ght bit operations 16 x 64 bit register file SIMD PSR flags with group conditional execution support SIMD instruction support for sum of absolute differences SAD and multiply accumulate MAC operations Instruction support for alignment and video operations Intel Wireless MMX 2 and SSE integer instruction compatibility Superset of existing core media processing instructions 3 1 4 Power Management Th...

Page 12: ... stable low noise supplies for all core voltage domains with additional regulators for supplying peripheral ICs All supplies are fed by high performance low dropout LDO voltage regulators and offering very low quiescent current consumption and high power supply rejection Three high efficiency DC DC buck converters provide high current low voltage supplies to the processor core and memory The main ...

Page 13: ...d connectors Connector on VAR 320SBC Manufacturer Tyco Electronics P N 1 353190 0 Description 0 6mm pitch Board to Board connector 140 pin Free height type Mating part to be used on base board Manufacturer Tyco Electronics P N 1 353180 0 Description 0 6mm pitch Board to Board connector 140 pin Free height type 4 Interfaces 4 1 TouchScreen Features 13 ...

Page 14: ... detection and nIRQ generation Supports several schemes of measurement averaging to filter noise Maximum X Y sample rate without averaging 5 kHz Signal Pin number Type Description TSPX P2 88 Analog TSI interface X Plus TSMY P2 90 Analog TSI interface Y Minus TSMX P2 92 Analog TSI interface X Minus TSPY P2 94 Analog TSI interface Y Plus 14 ...

Page 15: ...data formats from 8 16 18 and 32 bits of serial data Network mode for operation on a time slotted bus Master or slave operation for both clock and frame sync signals Receive without transmit operation Flexible clock source selection from the 13 MHz master clock the network clock input or the dedicated SSP External clock input Audio clock control to provide a 4x or 8x output clock to support most s...

Page 16: ...mmed IO or DMA transfers To minimize CPU overhead for UART communications device driver software can setup interrupts and DMA for data transfers to from memory All three UARTs support the 16550A and 167502 functions Full function UART FFUART signals Signal Pin number Type Description GPIO FFRXD P1 27 I FFUART RXD 41 FFTXD P1 29 O FFUART TXD 42 FFDCD P1 33 I FFUART DCD 44 FFDTR P1 35 O FFUART DTR 4...

Page 17: ... data transfer modes Interrupt based application interface to control software interaction Multiple MMC cards are supported when using the MMC communications protocol Only one SD or SDIO card is supported when using the SD or SDIO communications protocol per controller Up to two MMC or SD SDIO cards are supported when using the SPI communications protocol Mixed card types are supported only by the...

Page 18: ...AS P2 9 O LCD AC bias Data enable 17_2 L_DD_0 P2 11 O LCD Data line 6_2 L_DD_1 P2 13 O LCD Data line 7_2 L_DD_2 P2 15 O LCD Data line 8_2 L_DD_3 P2 17 O LCD Data line 9_2 L_DD_4 P2 21 O LCD Data line 10_2 L_DD_5 P2 23 O LCD Data line 11_2 L_DD_6 P2 25 O LCD Data line 12_2 L_DD_7 P2 27 O LCD Data line 13_2 L_DD_8 P2 29 O LCD Data line 63 L_DD_9 P2 33 O LCD Data line 64 L_DD_10 P2 35 O LCD Data line...

Page 19: ...s a test access port TAP controller TAP pins an instruction register and Test Data registers TDRs The JTAG interface is controlled through five dedicated TAP pins that interface to the TAP controller TDI TMS TCK nTRST and TDO Signal Pin number Type Description NTRST P2 128 I JTAG Test Reset TDI P2 130 I JTAG Serial data input TMS P2 132 I JTAG Test Mode Select TDO P2 136 O JTAG Serial data output ...

Page 20: ...te control of the 1 Wire bus through eight bit commands The 1 Wire bus serial operation uses an open drain wired AND bus structure that allows multiple devices to drive the bus lines and to communicate status on events such as arbitration wait states and error conditions Signal Pin number Type Description GPI O ONE_WIRE P1 64 I O Open drain 1 Wire bidirectional data bus 0_2 20 ...

Page 21: ...480 1280 x 1024 1600 x 1200 2048 x 1536 2048 x 2048 2560 x 2048 Programmable sensor clock output from 187 kHz to 52 MHz Pixel clock received from 187 kHz to 52 MHz Programmable interrupts for FIFO overflow end of line and end of frame Support for 8 and 10 bit RAW RGGB CMYG etc capture modes Support for master mode operation Programmable interface timing signals for external synchronization signali...

Page 22: ...ne correction Programmable coefficients for color space conversion from RGB to YCbCr 4 2 2 Signal Pin number Type Description GPIO CIF_DD0 P1 66 I Quick Capture Interface Data Signal 49 CIF_DD1 P1 68 I Quick Capture Interface Data Signal 50 CIF_DD2 P1 70 I Quick Capture Interface Data Signal 51 CIF_DD3 P1 72 I Quick Capture Interface Data Signal 52 CIF_DD4 P1 76 I Quick Capture Interface Data Sign...

Page 23: ...om DM9000B Ethernet controller Features Fully compliant with IEEE 802 3 802 3u standards Integrated Ethernet MAC and PHY 10BASE T and 100BASE TX support Full and Half duplex support Full duplex flow control Backpressure for half duplex flow control Preamble generation and removal Automatic 32 bit CRC generation and checking Automatic payload padding and pad removal Auto negotiation Automatic polar...

Page 24: ...t Controller The Universal Serial Bus USB supports serial data exchanges between a host computer and a variety of simultaneously accessible peripherals The attached peripherals share USB bandwidth through a host scheduled token based protocol Peripherals can be attached configured used and detached while the host and other peripherals continue operation Features USB Rev 1 1 compatible Supports bot...

Page 25: ... Data bus n a DF_IO_5 P2 105 I O Data bus n a DF_IO_6 P2 107 I O Data bus n a DF_IO_7 P2 109 I O Data bus n a DF_IO_8 P2 111 I O Data bus n a DF_IO_9 P2 113 I O Data bus n a DF_IO_10 P2 117 I O Data bus n a DF_IO_11 P2 119 I O Data bus n a DF_IO_12 P2 121 I O Data bus n a DF_IO_13 P2 123 I O Data bus n a DF_IO_14 P2 125 I O Data bus n a DF_IO_15 P2 129 I O Data bus n a DF_BA_0 P2 57 O DFI bus addr...

Page 26: ...a Compact Flash specific Signal Pin number Type Description GPIO CF_nPIOR P2 83 O Card interface I O space output enable 5 CF_nPIOW P2 85 O Card interface I O space write enable 6 CF_nIOIS16 P2 87 I 0 16 bit I O space 1 8 bit I O space 7 CF_nPWAIT P2 89 I Card interface input for inserting wait states 8 CF_RESET P2 112 I CF card reset n a CF_BVD1 P2 116 I CF card BVD1 n a CF_RDY P2 118 I CF_RDY n ...

Page 27: ...plies RESET_IN_N P2 20 I Master reset input active low to force complete system reset RESET_OUT_N P2 124 I Reset out line from PXA320 to peripheral devices nONKEY P2 22 I On switch activates the LP3972 PMIC EXT_WAKEUP1 P2 40 I Wake up signal from Deep Sleep VDD_DDR_EXT P1 34 36 I DDR 1 8V supply for Deep sleep BACKUP BATTERY P2 46 48 I Backup battery charger output V_BATT P1 7 19 31 43 55 6 7 79 9...

Page 28: ...CODEC_MONO_OUTP1 47 O Loudspeaker mono output for Ext Amp HP_LOUT P2 82 O Headphones Right HP_ROUT P2 84 O Headphones Left CODEC_LINEOUTL P2 32 O Codec audio line out L CODEC_LINEOUTR P2 34 O Codec audio line out R CODEC_MIC P2 131 I Audio codec mic in CODEC_BIAS P2 133 O Audio codec mic bias voltage AUD_GND P2 135 137 139O Audio low noise output GND for MIC 28 ...

Page 29: ...face and is dedicated for connection to an external voltage regulator for hard coded power management communication If PWR_EN or SYS_EN change state for example during a power state change the appropriate I2C commands are transmitted to the PMIC as well No configuration or software interaction is required The Power I2C interface cannot be used as a general purpose I2C interface The Power I2C is us...

Page 30: ...DC buck converters provide high current low voltage supplies to the processor core and memory The main converter features Dynamic Voltage Management DVM with programmable voltage and slew rate control 5 2 Power consumption VAR 320SBC power consumption depends on the active components and peripherals BSP implements Dynamic Voltage Management Core changes its own frequency Voltage according to CPU u...

Page 31: ...eral purpose IO pin 0 14 NC n a 15 GPIO1 I O General purpose IO pin 1 16 ETH_V_1P8V O Analog 1 8v for Ethernet magnetics 40 17 GPIO16 I O General purpose IO pin 16 18 ETH_V_1P8V O Analog 1 8v for Ethernet magnetics 34 19 V_BATT n a 20 ETH_V_1P8V I Analog 1 8v for Ethernet magnetics 39 21 NC n a 22 BT_TXD O BT UART TXD 111 23 NC n a 24 BT_RXD I BT UART RXD 110 25 NC n a 26 GND n a 27 FFRXD I FFUART...

Page 32: ...2C_SCL O Serial clock for the standard I2C controller n a 62 GND n a 63 GPIO88 General purpose IO pin 88 64 ONE_WIRE I O Open drain 1 Wire bidirectional data bus 0_2 65 GPIO75 I O General purpose IO pin 75 66 CIF_DD0 I Quick Capture Data Signal 49 67 V_BATT I 68 CIF_DD1 I Quick Capture Data Signal 50 69 NC 70 CIF_DD2 I Quick Capture Data Signal 51 71 NC n a 72 CIF_DD3 I Quick Capture Data Signal 5...

Page 33: ...neral purpose IO pin 118 110 GND n a 111 GPIO119 I O General purpose IO pin 119 112 MMC_DAT_0 I O SD MMC Data 18 113 GPIO120 I O General purpose IO pin 120 114 MMC_DAT_1 I O SD MMC Data 19 115 V_BATT I n a 116 MMC_DAT_2 I O SD MMC Data 20 117 GPIO121 I O General purpose IO pin 121 118 MMC_DAT_3 I O SD MMC Data 21 119 GPIO122 I O General purpose IO pin 122 120 MMC2_CLK O SD MMC Bus clock 28 121 GPI...

Page 34: ...a line 9_2 18 L_DD_17 O LCD Data line 72 19 V_BATT n a 20 RESET_IN_N I Master reset input 21 L_DD_4 O LCD Data line 10_2 22 nONKEY I On switch Activates the National PMIC n a 23 L_DD_5 O LCD Data line 11_2 24 N C n a 25 L_DD_6 O LCD Data line 12_2 26 GND n a 27 L_DD_7 O LCD Data line 13_2 28 ADC_IN1 A D line input 1 n a 29 L_DD_8 O LCD Data line 63 30 ADC_IN2 A D line input 2 n a 31 V_BATT n a 32 ...

Page 35: ...Receive Data 96 61 DF_BA_2 O DFI bus address 2 n a 62 GND 63 DF_BA_3 O DFI bus address 3 n a 64 USBH_N I O USB Full Speed Host Port 1 Positive Line n a 65 N C n a 66 USBH_P I O USB Full Speed Host Port 1 Negative Line n a 67 V_BATT n a 68 USBH_PEN USB Full speed host power control 2_2 69 LLA_N O Lower address latch n a 70 USBH_OVERC USB Full speed host over currant indicator 3_2 71 LUA_N O Upper a...

Page 36: ...1 n a 109 DF_IO_7 I O DFI Data bus n a 110 GND n a 111 DF_IO_8 I O DFI Data bus n a 112 CF_RESET O CF card reset n a 113 DF_IO_9 I O DFI Data bus n a 114 CF_CD_1n CF card detect n a 115 V_BATT n a 116 CF_BVD1 O CF card BVD1 n a 117 DF_IO_10 I O DFI Data bus n a 118 CF_RDY n a 119 DF_IO_11 I O DFI Data bus n a 120 WLAN_WAKEUP n a 121 DF_IO_12 I O DFI Data bus n a 122 GND n a 123 DF_IO_13 I O DFI Da...

Page 37: ...VAR 320SBC Reference Guide Copyright 2008 Variscite 37 138 TCK I JTAG Test Clock n a 139 AUD_GND O Audio low noise output GND for MIC n a 140 V_RTC O Permanent 2 9v output voltage n a ...

Page 38: ...acteristics Condition Min Max Supply Voltage V_BATT 0 3V 5 5V Commercial operating temperature range 0 C 65 C Extended operating temperature range 20Ẁ C 85 C 8 Absolute maximum Characteristics Min Max Supply Voltage V_BATT 0 3V 5 5V Storage temperature range 45 C 165 C 38 ...

Page 39: ...VAR 320SBC Reference Guide Copyright 2008 Variscite 9 Mechanical drawing SBC Height including BaseBoard connectors 9mm 39 ...

Page 40: ...s are not intended for use in life support systems appliances nuclear systems or systems where malfunction can reasonably be expected to result in personal injury death or severe property or environmental damage Any use of products by the customer for such purposes is at the customer s own risk Variscite does not grant any license express or implied under any patent right copyright mask work right...

Page 41: ...r damaged by accident misuse or abuse Disclaimer of Warranty THIS WARRANTY IS MADE IN LIEU OF ANY OTHER WARRANTY WHETHER EXPRESSED OR IMPLIED OF MERCHANTABILITY FITNESS FOR A SPECIFIC PURPOSE NON INFRINGEMENT OR THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION EXCEPT THE WARRANTY EXPRESSLY STATED HEREIN THE REMEDIES SET FORTH HEREIN SHALL BE THE SOLE AND EXCLUSIVE REMEDIES OF ANY PURCHASER WIT...

Page 42: ...t 2008 Variscite 42 12 Contact information Headquarters Variscite LTD 20 Galgalei Haplada st Hertzelia Israel Tel 972 9 9562910 Fax 972 9 9562912 Sales sales variscite com Technical support support variscite com Website www variscite com ...

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