VAR-320SBC Reference Guide
Copyright © 2008 Variscite
4.2. SSP Interface
The VAR-320SBC outputs one SSP interface.
The SSP controllers support these protocols:
9
Programmable serial protocol (PSP) with programmable frame sync and programmable
start and stop delays
9
Texas Instruments Synchronous Serial Protocol* (SSP)
9
Motorola Serial Peripheral Interface* (SPI) protocol
9
Inter-IC Sound (I2S) protocol
•
Up to 13-Mbps transfer rate with internal clock generation
•
Packed mode to 1w double-depth FIFOs if sample less than 16 bits wide
•
Sample data formats from 8, 16, 18, and 32 bits of serial data
•
Network mode for operation on a time-slotted bus
•
Master or slave operation for both clock- and frame-sync signals
•
Receive-without-transmit
operation
•
Flexible clock source selection from the 13-MHz master clock, the network clock input, or
the dedicated SSP
•
External clock input
•
Audio clock control to provide a 4x or 8x output clock to support most standard audio
frequencies
Signal
Pin
number
Type Description
GPIO
SSP4_SCLK
P2-54
I/O
Synchronous Serial Protocol Serial Clock
93
SSP4_SFRM P2-56 I/O Synchronous
Serial
Protocol Serial Frame Indicator
94
SSP4_TXD
P2-58
O
Synchronous Serial Protocol Transmit Data
95
SSP4_RXD
P2-60
I
Synchronous Serial Protocol Receive Data
96
15
