Vaisala RVP900, User Manual

Page: 84 / 484

Table 26 Bit Assignments for the IFDR Coax Uplink
Bit(s) Meaning
1 ... 4 Marker sequence (0,1,1,0). This fixed, 4-bit sequence identifies the start of a valid data
sequence following the variable-length burst window.
The first 0 in this pattern marks the end of the variable length burst window. You can check
the other three bits to verify that a valid bit sequence is being received.
5 ... 20 16-bit, multi-purpose data word, MSB is transmitted first
21 Reset Request. This bit sets in one transmitted sequence when an RVP900 reset occurs.
22 If set, then interpret the 16-bit data word as 4-bits of command and 12-bits of data, rather than
as a single 16-bit quantity
23 ... 24 Diagnostic select bits. These are used by the RVP900 power- up diagnostic routines; they are
both zero during normal operation.
25 Green LED Request.
• 0=Off
• 1=On
The state of this bit usually follows the Downlink Detect LED on the IFDR.
The period
Ʈ
s
of the serial data is ( 128/f
aq
) , where f
aq
is the acquisition clock frequency
given in the Mc section of the RVP900 setup menu. For the default clock frequency of
71.9502 MHz, the period of the serial data is 1.779 μsec. The logic that receives the serial data
should first locate the center of the first data bit at (0.5 ×
Ʈ
s
) past the falling edge at the end
of the burst window. Subsequent data bits are sampled at uniform
Ʈ
s
intervals.
The data sampling rate can be in error by as much as one part in 75 while still maintaining
accurate reception. This is because the data sequence is only 25-bits long, and therefore, the
last data bit would still be sampled within ±1/3 bit time of its center. This flexibility helps
when designing the receiving logic. For example, if a 5 MHz or 10 MHz clock were available,
then sampling at 1.8 μsec intervals (1:85 error) would be fine. Similarly, you could sample at
1.75 μsec based on a 4 MHz or 8 MHz clock (1:61 error), but only if the first sample were
moved slightly ahead of center, so that the sampling errors were equalized over the 25-bit
span.
Interpreting the Serial 16-bit Data Word
The serial 16-bit data word has different interpretations depending on the RVP900
configuration and whether
Bit #22
of the uplink stream is set or clear. The evolution of
these different formats is in response to the evolution of the IFDR and DAFC modules. See
4.2 RVP901 IFDR Hardware (page 54) and 3.6 Digital AFC (DAFC) (page 50) .
The original purpose of the uplink data word was to convey a 16-bit AFC level, generally for
use with a magnetron system.
Bit #22 is clear in this case, and the word is interpreted as a
linear signed binary value. While it is available to support backwards compatibility, this
format is not recommended for new hardware designs.
RVP900 User Guide M211322EN-J
82