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DNA/DNR-IRIG-650 IRIG Timing Layer

Chapter 3

Programming with the Low Level API

Tel: 508-921-4600

www.ueidaq.com

Vers:

4.6



Date: March 2019

DNx-IRIG-650 Chap3x.fm



United Electronic Industries, Inc.

one (Time Keeper measures and averages the number of base clock cycles
between externally derived 1PPS pulses when they are valid).

3. If external timebase is not derived from the timecode and if its external time-

base is slower than 1PPS, then use the

CT650_TKFLG_SUBPPS

flag.

4. If BCD data in the incoming timecode is corrupted, use the flag

CT650_TK-

FLG_USESBS

to force the use of SBS for TK hour/min decoding.

5. If you know that seconds, minutes or days information is invalid in the input

timecode, use the flags:

CT650_TKFLG_SEC_INVALID

CT650_TKFL-

G_MIN_INVALID

CT650_TKFLG_DAY_INVALID

This is an example of how to set the Time Keeper for internal timebase:

mode = CT650_TKPPS_INTERNAL;

flags = CT650_TKFLG_AUTOFOLLOW|CT650_TKFLG_USENOMINAL;

ret = DqAdv650ConfigTimekeeper(hd, devn, mode, flags);

3.2.1.2

Get time from
Time Keeper

Once that the Time Keeper is enabled the user can set and read time from it.
There are two functions available to read time.

The first function to read time is:

ret = DqAdv650GetTimeSBS(hd, devn, &seconds, &micro,

&dayofyear, &year, &tkstatus);

This function returns seconds from the beginning of the day, microseconds
within the last second at the moment of function call, day of the year, year and
the status of the Time Keeper.
The following Time Keeper status conditions are defined:
1.

CT650_TKSTS_BIN2BCD_ERR

- binary time code is invalid (sticky)

CT650_TKSTS_BCD2BIN_ERR

- BCD time code is invalid (sticky)

CT650_TKSTS_TK_ERR

- time code received mismatch current time (sticky)

CT650_TKSTS_1PPS_GEN

- 1pps was generated (sticky)

CT650_TKSTS_1PPS_RCV

- selected 1pps was received (sticky)

CT650_TKSTS_TC_RCV

- external time code was received and applied

(sticky)

CT650_TKSTS_1PPS_ADVAL

- 1pps output of adaptive PLL in TK is valid

CT650_TKSTS_PPS_LOST

- 1pps was not detected within last validation

interval

CT650_TKSTS_AVG_INVAL

- if averaged 1pps does not pass validation cri-

teria

10.

CT650_TKSTS_1PPS_INVAL

- last detected external 1pps was invalid

Bits marked as “sticky” are set when condition is met and cleared upon read
from the status register. Thus, if you call

DqAdv650GetTime…()

in a short

period of time between calls, only those bits that were detected will be present
on the second call.

CT650_TKSTS_TK_ERR

is always generated upon synchronization with external

timecodes or for IRIG codes with sub-PPS frame rates. For IRIG-B

0x700

code

normal, for sub-PPS and high frame rate codes, 1PPS invalid warnings might be
set.

Summary of Contents for DNA-IRIG-650

Page 1: ...l IRIG A B E and G Timing Generation and Synchronization board for the PowerDNA Cube and PowerDNR RACKtangle Release 4 6 March 2019 PN Man DNx IRIG 650 319 Copyright 1998 2019 United Electronic Industries Inc All rights reserved ...

Page 2: ...ueidaq com Website www ueidaq com FTP Site ftp ftp ueidaq com Product Disclaimer WARNING DO NOT USE PRODUCTS SOLD BY UNITED ELECTRONIC INDUSTRIES INC AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS Products sold by United Electronic Industries Inc are not authorized for use as critical components in life support devices or systems A critical component is any component of a life support d...

Page 3: ...n 10 2 2 Configuring the Resource String 10 2 2 1 Configuring Time Keeper Input 10 2 2 2 IRIG Output 12 2 2 3 IRIG Input 13 2 2 4 GPS Input 14 2 2 5 Driving the TTL outputs 14 2 3 Configuring the timing 15 2 4 Reading data 16 2 5 Cleaning up the Session 16 Chapter 3 Programming with the Low Level API 17 3 1 Low level Functions 18 3 2 Low level Programming Techniques 19 3 2 1 Time Keeper Programmin...

Page 4: ...ight 2019 United Electronic Industries Inc List of Figures Chapter 1 Introduction 1 1 1 Simplified Block Diagram of the IRIG 650 5 1 2 Functional Diagram of DNx IRIG 650 board 6 1 3 Pinout for the DNx IRIG 650 series layer 9 A 1 Pinout photo and schema of DNA CBL 650 accessory 50 A 2 Photo of DNA ACC 650 break out board and BNC 650 51 ...

Page 5: ...lse A generic digital input may also be used to directly capture event timing The DNx IRIG 650 can also be configured as an IRIG source which will provide timing and synchronization for other devices in the system The board provides both modulated analog and digital IRIG outputs as well as 10 MHz and 1 PPS synchronization and timing DCLS Manchester II signals The boards also include a built in GPS...

Page 6: ...ace generally represents text that should be entered verbatim For instance it can represent a command as in the following example You can instruct users how to run setup using a command such as setup exe Text formatted in fixed typeface generally represents source code or other text that should be entered verbatim into the source code initialization or other file Examples of Manual Conventions Bef...

Page 7: ...me base or slaved to external 10 MHz Protocols Supported IRIG A A00x ABx IRIG B B00x B12x B IEEE 1344 B TrueTime IRIG E E00x E11x E12x IRIG G G00x G14x Time Source The IRIG 650 s time keeper can be synchronized with the following sources IRIG AM modulated input timecode IRIG DCLS i e NRZ L code or Manchester II code GPS signal sync d with GPS 1 PPS clock time derived from GPRMC string Precise exte...

Page 8: ...RIG Output types A B E and G types supported Analog output 3 1 ratio 4 V P P output 50 ohm Digital output high voltage 1 1 V 50 Ω min 2 4V 1 Meg Ω min Digital output low voltage 0 3V 50 Ω max 0 7V 1 Meg Ω max Sync and Clock outputs TTL CMOS compatible Output timing signal selection Std 1 10 PPS PPM plus custom Output clock selection 1 5 and 10 MHz plus custom freqs On Board Clock Frequency 10 MHz ...

Page 9: ...ock diagram of the layer s architecture Figure 1 1 Simplified Block Diagram of the IRIG 650 DB 62 female 62 pin I O connector RDY LED STS LED DNA bus connector DB 62 female 62 pin I O connector RDY LED STS LED DNR bus connector 32 bit 66 MHz Internal bus On Board FPGA 20 MHz High Precision VETCXO Digital Calibration D A Programmable PLL Input Buﬀers Output Drivers AM Input Circuitry DC AC AM Outpu...

Page 10: ... of DNx IRIG 650 board PLL 100 MHz PLL DNA Bus SYNC lines 16 bit ADC AM2NRZ NRZ2TIME MII2NRZ Time Decoder UART GPS Receiver CLI Logic RFIn0 RFIn1 In0 In1 In2 In3 In4 GPSIn Out0 Out1 Out2 Out3 Output MUX Time Assembler Carrier Generator 14 bit DAC AMOut 1 PPS source Event detector recorder Input CL FIFO Aux D A clock fine tuning precise clock source 20 MHz Event Generator Time Keeper AMIn Inputs Ou...

Page 11: ...g data into double buffered time messages validate these messages using a validation table Each validated message is further processed to extract time information which is then copied into timing registers The current time is maintained in the Time Keeper module which receives time from the Time Decoder and keeps track of the time and or date increments If the current time does not match the time ...

Page 12: ...G 650 also provides event recording and event generating functions Event recording allows you to timestamp and store locations of up to four events from the following event sources SYNC bus lines of the Cube or RACKtangle External inputs Errors lost synchronization inputs invalid 1 PPS etc Start stop trigger broadcast commands The above recorded events may be streamed into the output FIFO which al...

Page 13: ...GPS antenna input pin 46 The remaining signals are brought out to a 37 pin Female connector at the end of the DNA CBL 650 as shown in the appendix This cable may be plugged into a DNA STP 37 screw terminal panel or other panel Please note that 12 of these signals are twisted pairs with their respective grounds as shown in the appendix 62 43 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 ...

Page 14: ...e first task is to create a session object 2 2 Configuring the Resource String UeiDaq Framework uses resource strings to select which device subsystem and channels to use within a session The resource string syntax is similar to a web URL device class IP address Device Id Subsystem Channel list For PowerDNA and RACKtangle the device class is pdna The IRIG 650 is programmed using the subsystem irig...

Page 15: ...k cycles between externally derived 1PPS pulses when they are valid 1PPS Source Value Description UeiIRIG1PPSInternal 1PPS signal is generated internally with precision oscillator UeiIRIG1PPSInputTimeCode 1PPS signal is derived from input timecode UeiIRIG1PPSGPS 1PPS signal is derived from GPS UeiIRIG1PPSRFIn 1PPS signal is derived from signal connected on RF input UeiIRIG1PPSExternalTTL0 External...

Page 16: ...e the time code UeiIRIGTimeCodeFormatA IRIG A UeiIRIGTimeCodeFormatB IRIG B UeiIRIGTimeCodeFormatE_100Hz IRIG E 100Hz UeiIRIGTimeCodeFormatE_1000Hz IRIG E 1000Hz UeiIRIGTimeCodeFormatG IRIG G In addition you can set the following parameter using the channel object methods under LabVIEW use property node Start when input is valid If selected the output time coder waits for the input time decoder to...

Page 17: ...ester II code on I O input 1 UeiIRIGDecoderInputNRZRF0 Time code is provided as a NRZ code on RF input 0 UeiIRIGDecoderInputNRZRF1 Time code is provided as a NRZ code on RF input 1 UeiIRIGDecoderInputNRZIO0 Time code is provided as a NRZ code on I O input 0 UeiIRIGDecoderInputNRZIO1 Time code is provided as a NRZ code on I O input 1 UeiIRIGDecoderInputGPS Time code is taken from GPS NMEA message T...

Page 18: ...LGPS_AntennaOK GPS Antenna Ok output UeiIRIGDOTTLGPSTxD1 GPS TXD1 COM1 output UeiIRIGDOTTLGPSTxD0 GPS TXD0 COM0 output UeiIRIGDOTTLManchesterIICarrier Recovered Manchester II carrier UeiIRIGDOTTLManchesterIItoNRZ Decoded Manchester II NRZ sequence UeiIRIGDOTTLSYNC3 Drive output from sync 3 UeiIRIGDOTTLSYNC2 Drive output from sync 2 UeiIRIGDOTTLSYNC1 Drive output from sync 1 UeiIRIGDOTTLSYNC0 Drive...

Page 19: ...e TTL pattern out of line 3 In addition you can set the following parameters using the channel object methods under LabVIEW use property node 40 ns pulse Set pulse width to 40ns instead of the default 60µs Use one or two TTL drivers Enables the second TTL driver provides stronger driving capabilities and sharper edges Drive Sync line Drive sync line instead of TTL output line 2 3 Configuring the t...

Page 20: ...he Session The session object will clean itself up when it goes out of scope or when it is destroyed To reuse the object with a different set of channels or parameters you can manually clean up the session as follows create a reader and link it to the IRIG session s stream CUeiIrigReade reader irigSession GetDataStream read current time in BCD format tUeiBCDTime bcdtime reader Read bcdtime read cu...

Page 21: ... other than Windows Please refer to the API Reference Manual document under Start Programs UEI PowerDNA Documentation for pre defined types error codes and functions for use with this layer The application developer is encouraged to first explore the existing source code examples The sample code provided with the Software Suite is self docu mented and the application developer will find it a good ...

Page 22: ...of latching it in BCD format DqAdv650GetInputTimecode Retrieves a processed block of decoded time code data as a struct DqAdv650GetTimeRegisters Retrieves a timekeeper time register sixteen registers DqAdv650ProgramPLL Sets PLL frequency and duty cycle returns actual frequency set DqAdv650ReadEventFifo Reads data from the event FIFO DqAdv650ReadGPS Reads data from GPS serial FIFO NMEA format DqAdv...

Page 23: ... be delivered from the following sources specified in mode parameter 1 Internal timebase from the precision oscillator CT650_TKPPS_INTERNAL 2 1PPS clock sources derived from input timecode CT650_TKPPS_TIME CODE 3 1PPS clock source CT650_TKPPS_GPS derived from integrated GPS device while the GPS device always produces 1PPS pulses user should read information from GPS device serial port to make sure...

Page 24: ... hd devn seconds micro dayofyear year tkstatus This function returns seconds from the beginning of the day microseconds within the last second at the moment of function call day of the year year and the status of the Time Keeper The following Time Keeper status conditions are defined 1 CT650_TKSTS_BIN2BCD_ERR binary time code is invalid sticky 2 CT650_TKSTS_BCD2BIN_ERR BCD time code is invalid sti...

Page 25: ...local time is set firmware will convert local time into UTC time to store in Time Keeper s registers and account for it when time is read The local offset must be set before setting or requesting the Time Keeper time The two functions DqAdv650GetTimeBCD and DqAdv650GetTimeRegisters read time straight from time decoder registers and Do not provide local time correction Do not work if time decoder c...

Page 26: ...nput CT650_IN_M2_RF1 Manchester II code on RFIn1 Rxt Trig In input CT650_IN_M2_IO0 Manchester II code on TTLIn0 input CT650_IN_M2_IO1 Manchester II code on TTLIn1 input CT650_IN_NRZ_RF0 NRZ code on RF0 Ext Clk In input CT650_IN_NRZ_RF1 NRZ code on RF1 Ext Clk In input CT650_IN_NRZ_IO0 NRZ code on TTLIn0 input CT650_IN_NRZ_IO1 NRZ code on TTLIn1 input The parameters pPrmDef and pDataDef are explain...

Page 27: ... case of AM it is the frequency of the sine signal In case of DCLS it is quantization frequency Number of cycles per bit is the character length in carrier periods here it is ten For character 0 each character consists of two high and eight low periods For character 1 each character consists of five high and five low periods For position identifier each char consists of eight high and two low peri...

Page 28: ...desc data description CT650_VALID_TABLE pCT650_VALID_TABLE For example IRIG B code is described as follows CT650_IRIG_CODE_DEF irig_b_bcd_cf_sbs IRIG B 100 Command Bit Register Description BCD seconds position 99 P0 CT650_VAL_P BCD_NoP_b BCD_NoP_r BCD_NoP_d position 0 Pr CT650_VAL_P BCD_NoP_b BCD_NoP_r BCD_NoP_d position 1 unit seconds CT650_VAL_01 BCD_SEC_b 0 BCD_SEC_r 0 BCD_SEC_d 0 position 2 CT...

Page 29: ...0 No operation for BCD section define BCD_SEC100_b B B 1 100 of a second define BCD_SEC10_b B B 8 1 10 of a second define BCD_SEC_b B B seconds define BCD_MIN_b B B 8 minutes define BCD_HOUR_b B B hours define BCD_DAYS_b B B days define BCD_YEAR_b B B year define BCD_LEAPYR_b 8 leap year flag define BCD_DLFLAG_b 9 DL flag SBS_SEC_b B 17th SBS second bit is stored in TREG2 BIT15 define SBS_SEC_b B ...

Page 30: ...fine BCD_LEAPYR_d BCD_SPEC_BIT 12 CT650_SECT_BCD 8 0 define BCD_DLFLAG_d BCD_SPEC_BIT 12 CT650_SECT_BCD 8 1 define SBS_SEC_d B BCD_SPEC_BIT 12 CT650_SECT_SBS 8 B define CF_BITS_d B BCD_SPEC_BIT 12 CT650_SECT_CF 8 B define CF_NoP_d CT650_SECT_CF 8 NOP or Positional char define SBS_NoP_d CT650_SECT_SBS 8 NOP or Positional char TREGs are logic registers where time data is collected There are two sets...

Page 31: ...firmware It needs to be called after DqAdv650SetTimecodeInput with the CT650_IN_DISABLED flag but before enabling layer input with DqAdv650Enable Bit Name Description Reset state 31 2 SP_RSV For first two characters Special bits Character 0 layer s timestamp bits 29 0 in 10us intervals Character 1 phase delay of the input bits 29 0 For all other characters reserved 0 1 0 CHAR Decoded characters CT...

Page 32: ...ef uint32 sigDefMask pPrmDef and pDataDef need to be set to the same tables as in DqA dv650SetTimecodeInput however most of the automatically calculated parameters can be overwritten Additionally pSigDef is defined as typedef struct user defined part double ppx time between time codes for most IRIG x 1pps uint32 pph pulses per hour 1PPS 3600PPH uint32 in_freq input carier frequency uint32 rx_ici c...

Page 33: ...efine CT650_MII_TOLWR 1L 11 define CT650_PPS_MINWR 1L 12 define CT650_PPS_MAXWR 1L 13 define CT650_PPSMAVWR 1L 14 3 2 2 3 Fine tuning Input Parameters Registers The following function may be useful for fine tuning input timecode parameters outside of the common timecodes prepackaged for ease of use Since the use of this function requires deep knowledge of processes inside time decoding algorithms ...

Page 34: ...e a combination of the following bits CT650_OUT_DISABLED start output in disabled state CT650_OUT_ENABLED start output in enabled state CT650_OUT_ONVALID Disable output waveform generation until time assembler restarts may take two minutes for sub PPS codes like IRIG E or H to avoid incorrect output during initial synchronization with exter nal time signal source CT650_OUT_EXTSYNCRQ External Resyn...

Page 35: ...50 Ohm termination is available on three input lines set by these flags CT650_OUT_RF1TERM Enable 50Ω termination for TTL RF1 TRIGIN input CT650_OUT_RF0TERM Enable 50Ω termination for TTL RF0 CLKIN input CT650_OUT_AMTERM Enable 50Ω termination for the AM input One or two buffers should be enabled to drive TTL output lines TTL0 to TTL3 CT650_OUT_TTLEN1 Enable buffer 1 applies to all lines CT650_OUT_...

Page 36: ...50_OUT_CFG_SRC_0_1S 0 1sec pulse CT650_OUT_CFG_SRC_0_01S 0 01sec pulse CT650_OUT_CFG_SRC_1 Drive output with 1 CT650_OUT_CFG_SRC_0 Drive output with 0 Note that to output a time code NRZ MII both the Time Encoder Decoder must have already been configured as in the above section DqAdv650AssignTTLOutputs can also be used to re route signals to the SYNCx line internal synchronization lines between th...

Page 37: ...ems eventually synchronize to the same time it doesn t make a significant difference when subsystems are enabled To configure a subsystem in enabled state so that it runs immediately after the function call set mode CT650_OUT_ENABLED in DqAdv650SetTimecodeInput or DqAdv650SetTimecodeOutput If subsystem needs to be configured but prevented from running use mode CT650_OUT_DISABLED In the latter case...

Page 38: ...can use four Event modules as channels 0 to 3 to create timed interrupts and provide synchronization signals to the outside world Additionally a dedicated event module is used to provide clocking to the input channel list allowing it to save timestamp information with 10µs resolution by default DQ_LN_10us_TIMESTAMP with the DQL_TMRCFG_TSTS_66M source or to a custom resolution by using the DqCmdRes...

Page 39: ...9 8 7 6 5 4 3 2 1 0 ICNTDIV Internal counter divider for the ESRC 4 DPLLF DPLL frequency of pulses between two intervals set by IRSRC source for the ESRC 6 SEC BCD seconds ESRC 2 MIN BCD minutes ESRC 2 HR BCD hour ESRC 2 DOY BCD day of year ESRC 2 SBS Straignt binary seconds of the day for the SB time mode ESRC 3 SBY Straignt binary year for the SB time mode ESRC 3 LSA Layer address DNA only DRD D...

Page 40: ..._EV1IRQ 1 Generate firmware IRQ based on sub event 1 26 CT650_EVT_CFG_EV0IRQ 1 Generate firmware IRQ based on sub event 0 25 CT650_EVT_CFG_DBL Number of sub events 0 single 1 dual 24 CT650_EVT_CFG_RPT Set repeat mode 0 one time 1 retriggerable 23 20 CT650_EVT_CFG_EVTPL N CT650_EVT_CFG_EVTPL_1MS 15 Specify event pulse length set to 60µs by default Special cases are EVTPL_1MS 15 to Use 1ms event pul...

Page 41: ...set time BCD time mode allows creation of the events that will repeat every year month day minute or second by masking unused parameters in CFG0 register For events with faster than 1sec repetition rate can be cascaded or internal counter can be used as an event source 1 CT650_EVT_CFG_ESRC_SWF Software only note that event sources 2 31 are ORed with software For the ESRC field software clock is re...

Page 42: ...f the year and SB microseconds when ESRC EVT_CFG_ESRC_BCDT microseconds ESRC EVT_CFG_ESRC_SBT 28 12 CT650_EVT_EMP0_SBS Straight binary seconds of the day 11 0 CT650_EVT_EMP0_SBY Straight binary year ESRC EVT_CFG_ESRC_BCDT 27 22 CT650_EVT_EMP0_SEC BCD seconds of the day 21 16 CT650_EVT_EMP0_MIN BCD minute of the hour 15 10 CT650_EVT_EMP0_HR BCD hour of the day 9 0 CT650_EVT_EMP0_DOY BCD day of the ...

Page 43: ...devn evt_chan flags event_sts Valid event channels evt_chan are 0 3 should correspond with event channels used in DqAdv650SetEvent to set up events Event status is stored in the following structure typedef struct uint32 event_sts event status uint32 event_tstamp event timestamp debug only uint32 event_ad event address data debug only EV650_STS pEV650_STS event_sts the event status register provide...

Page 44: ...n flags event param and then poll event status with ret DqAdv650GetEventStatus hd devn evt_chan flags event_sts printf EvtSts AD x STS x DNABTS x n event_sts event_ad event_sts event_sts event_sts event_tstamp Channel CT650_EVENT_CHD is a special channel which will store events into the layer FIFO which can be retrieved by calling DqAdv650ReadEventFifo periodically to make sure that FIFO does not ...

Page 45: ...0_t To set up asynchronous events on channels 0 thru 3 for EV650_EVENT the event should be configured using DqAdv650SetEvents Then asynchronous events should be set using the following call Notice that the event is configured with the handle received from DqAddIOMPort ret DqAdv650ConfigEvents a_handle DEVN evt_chan 0 EV650_PPS_CLK NULL Call the same function with EV650_CLEAR to disable the event F...

Page 46: ...le handle 0 1000 1000 pEvent size if ret 0 ret DQ_TIMEOUT_ERROR printf ERR s n DqTranslateError ret if ret 0 pEv650 pEV650_ID pEvent data for this packet do conversion in place ntoh_pEv650 pEv650 if print_msg printf Event x size d n pEvent event pEv650 size switch pEvent event case EV650_EVENT data contains two uint32 SBS seconds microseconds from TK this is where pacing and other types of events ...

Page 47: ...h_pEv650 pEV650_ID pEv650 uint32 i pEv650 chan ntohl pEv650 chan pEv650 evtype ntohl pEv650 evtype pEv650 size ntohl pEv650 size pEv650 tstamp ntohl pEv650 tstamp for i 0 i pEv650 size sizeof uint32 i pEv650 data i ntohl pEv650 data i return Note that all events configured by using DqAdv650SetEvents are received as EV650_EVENT Also error event is configured to be fired once If it is received it me...

Page 48: ...s data Sleep 1000 3 2 7 1 Retrieving GPS data The function DqAdv650GetGPSStatus returns the status of GPS receiver as These bits are returned as gsp_status in DqAdv650GetGPSStatus CT650_GPS_ACC_GPSANTSHRT 1 if antenna is shorted CT650_GPS_ACC_GPSANTOK 1 if antenna detected by the GPS CT650_GPS_ACC_GPSRXD1 Current value of GPS RXD1 pin CT650_GPS_ACC_GPSTXD1 Current value of GPS TXD1 pin CT650_GPS_A...

Page 49: ...lites used in position fix 00 12 Notice Fixed length field of two letters d d HDOP Horizontal Dilution Of Precision h h Altitude mean sea level geoid M Letter M g g Difference between the WGS 84 reference ellipsoid surface and the mean sea level altitude M Letter M a a xxxx GPRMC hhmmss dd S xxmm dddd N S yyymm dddd E W s s h h dd mmyy d d E W M hh CR LF hhmmss dd UTC time of the fix hh hours mm m...

Page 50: ...OP and Active Satellites GPS receiver operating mode satellites used in the navigation solution reported by the GGA sentence and DOP values Example GPGSA A 3 02 21 30 04 16 05 10 12 31 29 1 33 0 81 1 06 02 Format GPGSV n m ss xx ee aaa cn xx ee aaa cn hh CR LF n Total number of messages 1 to 9 m Message number 1 to 9 ss Total number of satellites in view xx Satellite ID PRN number ee Satellite ele...

Page 51: ...t call DqAdv650SetGPSTime to force GPS time to be written to the TimeKeeper registers by the interrupt service routine if status CT650_GPS_ACC_ACTIVE If GPS reception is active printf GPS is active Adjust board time to GPS time n ret DqAdv650SetGPSTime hd devn flags status If time has been applied another GPS status bit will be set CT650_GPS_ACC_GPSAPPLIED When it is set the timekeeper time matche...

Page 52: ...ed in EEPROM and needs to be programmed every time when IRIG 650 is configured by the user application Please contact UEI technical support for more detail and calibration advice 3 2 9 Custom PLL frequency generation The IRIG 650 has one or three for logics after 0x010210D8 on board PLL driven from precision temperature and oven controlled oscillator This PLL can be programmed to generate any freq...

Page 53: ...RIG 650 Chap3x fm Copyright 2019 United Electronic Industries Inc CT650_OUT_CFG_EVENTx for logic 0x010210D8 or newer and routing those clock lines into your receiving layer s with DqAdvRoute ClockIn hd LAYER_TO_BE_CLOCKED DQ_EXT_SYNCx and configuring the layer to use this input source instead it is possible to clock the layer from a IRIG 650 PLL ...

Page 54: ...IG cable providing BNC connections for Clock IRIG signals and 37 pin con nections for other I O 2ft long included with purchase of DNA DNR IRIG 650 Figure A 1 Pinout photo and schema of DNA CBL 650 accessory 1 GPS Gnd 2 GPS Gnd 3 4 ISGND 5 ISGND 6 ISGND 7 TTL IN2 8 ISGND 9 ISGND 10 11 ISGND 12 ISGND 13 ISGND 14 15 ISGND 16 ISGND 17 ISGND 18 19 20 21 22 23 TTL IN0 24 TTL IN1 25 ISGND 26 TTL IN3 27 ...

Page 55: ...9 United Electronic Industries Inc DNA ACC 650 Break out board connects to DNA IRIG 650 primary 62 pin connector and pro vides GPS AM IN AM OUT and EXTCLK IN to mini BNC connectors DNA BNC 650 Cable for DNA ACC 650 s mini BNC connector to BNC for external devices 1ft long Figure A 2 Photo of DNA ACC 650 break out board and BNC 650 ...

Page 56: ...9 United Electronic Industries Inc DNA DNR IRIG 650 IRIG Timing Layer 52 Index C Cable s 50 Cleaning up the Session 16 Cleaning up the session 16 Configuring the Resource String 10 Conventions 2 Creating a Session 10 D Data Representation 48 H High Level API 10 O Organization 1 S Screw Terminal Panels 50 Support ii Support email support ueidaq com ii Support FTP Site ftp ftp ueidaq com ii Support ...

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