LEXI-R422 - System integration manual
UBX-23007449 - R02
Design-in
Page 74 of 108
C1-Public
Providing 1 UART with TXD and RXD lines only
☞
Providing the
TXD
and
RXD
lines only is not recommended if the multiplexer functionality is used
in the application: providing also at least the HW flow control (
RTS
and
CTS
lines) is recommended,
and it is in paricular necessary if the low power mode is enabled by +UPSV AT command.
If functionality of the
CTS
,
RTS
,
DSR
,
DCD
,
RI
and
DTR
lines is not required in the application, then:
•
Connect the
RTS
input line to GND or to the
CTS
output line of the module, since the module
requires
RTS
active (low electrical level) if HW flow-control is enabled (AT&K3, default setting)
•
Connect the
DTR
input line to GND using a 0
series resistor, because it is useful to set
DTR
active
if not specifically handled, in particular to have URCs presented over the UART interface (see the
AT commands manual
, &D, S0, +CNMI AT commands)
•
Leave
DSR
,
DCD
and
RI
lines of the module floating
If RS-232 compatible signal levels are needed, the Maxim MAX13234E voltage level translator can be
used. This chip translates voltage levels from 1.8 V (module side) to the RS-232 standard.
If a 1.8 V Application Processor (DTE) is used, the circuit should be implemented as in
TxD
Application Processor
(1.8V DTE)
RxD
RTS
CTS
DTR
DSR
RI
DCD
GND
LEXI-R422
(1.8V DCE)
F1
TXD
K1
DTR
E1
RXD
H1
RTS
G1
CTS
M1
DSR
L1
RI
J1
DCD
GND
0
Ω
TP
0
Ω
TP
0
Ω
TP
TP
0
Ω
TP
Figure 54: UART interface application circuit with a 3-wire link in the DTE/DCE serial communication (1.8V DTE)
If a 3.0 V Application Processor (DTE) is used, then it is recommended to connect the 1.8 V UART
interface of the module (DCE) by means of appropriate unidirectional voltage translators using the
module
V_INT
output as 1.8 V supply for the voltage translators on the module side, as in
A11
V_INT
TxD
Application Processor
(3.0V DTE)
RxD
DTR
DSR
RI
DCD
GND
LEXI-R422
(1.8V DCE)
F1
TXD
K1
DTR
E1
RXD
M1
DSR
L1
RI
J1
DCD
GND
1V8
B1
A1
GND
U1
VCCB
VCCA
Unidirectional
voltage translator
C1
C2
3V0
DIR1
DIR2
OE
VCC
B2
A2
RTS
CTS
H1
RTS
G1
CTS
TP
0
Ω
TP
0
Ω
TP
0
Ω
TP
TP
0
Ω
TP
Figure 55: UART interface application circuit with a partial V.24 link (3-wire) in DTE/DCE serial communication (3.0 V DTE)
Reference
Description
Part number - Manufacturer
C1, C2
100 nF capacitor ceramic X7R 0402 10% 16 V
GRM155R61A104KA01 - Murata
U1
Unidirectional voltage translator
SN74AVC2T245
7
- Texas Instruments
Table 34: UART application circuit components with partial V.24 link (3-wire) in DTE/DCE serial communication (3.0 V DTE)
7
Voltage translator providing partial power down feature so that the DTE 3 V supply can be also ramped up before
V_INT
1.8 V supply