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S1571 D1181-001 http://www.tyan.com
Stands for Memory Address Drive Strength. Controls the strength of
the output buffers driving the MA and BA1 pins (first value) and
SCASx#, CKEx, MWEx#, and SRASx# pins (second value).
Because the PCI bus is so much faster than the ISA bus, the I/O
recovery mechanism adds bus clock cycles to the ISA bus between PCI-
originated I/O cycles. These two fields let you add recovery time (in bus
clock cycles) for both 8-bit and 16-bit I/O.
You can reserve this area of the system memory for ISA adapter ROM.
As long as it is reserved, however, it cannot be cached. Any peripherals
that require this area of system memory will likely have a note in their
user information to that effect.
The chipset has an embedded 32-bit posted write buffer to support
delay
transactions cycles. Select Enabled to support compliance with
PCI
specification version 2.1.
If your system contains a single bank of pipelined burst SRAM, select
Faster. If your system contains two banks of pipelined burst SRAM,
select Fastest.
s
8- and 16-Bit I/O Recovery Time
s
Memory Hole at 15M-16M
s
PCI Passive Release
s
PCI Delayed Transaction
s
Pipeline Cache Timing
If Disabled, NA# assertion depends upon cache size and type. If
Enabled, the NA# pin is never asserted. Further, the chipset will signal
the CPU for a new memory address before all the data transfers for the
current cycle are complete. This is called “pipelining.”
s
Chipset NA# Asserted
s
DRAM Refresh Rate
When Enabled, CPU to PCI bus accesses are allowed during passive
release. If Disabled, only another PCI master will have access to local
DRAM.
In accord with your DRAM specifications, designate the period required
to refresh the DRAMs.
BIOS Configuration
s
Mem. Drive Str. (MA/RAS)
