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S1571 D1181-001 http://www.tyan.com
BIOS Configuration
This function selects the optimal values for your chipset parameters. If
Disabled, the chipset parameters will revert to setup information stored
in CMOS. When Auto Configuration is Enabled, many of the options
below will not be available.
s
DRAM Timing
s
Auto Configuration
The value in this field is determined by the performance parameters of
the installed DRAM chips. Unless you install new memory that has a
different performance rating than the factory DRAMs, you should not
alter this field.
Select the combination of CPU clocks the DRAM on your board
requires before each read from or write to the memory. Beware:
changing the value from the setting determined by the board designer for
the installed DRAM may cause memory errors.
Sets the timing for reads from EDO (Extended Data Output) or FP[M]
(Fast Page Mode) memory. The lower you set the timing numbers, the
faster the system will address the memory. Selecting timing numbers
lower than the installed DRAM is able to support can result in memory
errors.
Sets the timing for writes to memory. As above, the lower the timing
numbers, the faster the system will address the memory. Note that
selecting timing numbers lower than the installed DRAM is able to
support can result in memory errors.
s
Fast EDO Leadoff
Unless you have EDO DRAMS in a synchronous cache or cahceless
system, select Disabled. Enabling will cause a 1-HCLK pull-in for all
read leadoff latencies for EDO DRAMs (i.e., page hits, page misses, and
row misses). You should also select Disabled if any of the DRAM rows
contain FPM DRAMs.
s
Refresh RAS# Assertion
Select the number of clock cycles in which RAS# is asserted for refresh
cycles.
s
DRAM Leadoff Timing
s
DRAM Read Burst
s
DRAM Write Burst Timing
