TELECOMMUNICATIONS TECHNIQUES CORPORATION
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jack. A clock signal via the EXT TX CLK IN jack may be
selected as the timing source for the transmitted data signal.
2.3.6 DIP Switch
Use DIP switch position 3, 4, and 5 to reduce the ampli-
tude noise level on the EXT TX CLK IN, RCV CLK, and RCV
DATA leads by changing the line to line termination to line to
ground termination. The 124 ohm line to line termination of
the external transmit clock input, receive clock, and receive
data may be split by placing a 62 ohm resistor from each line
to ground. Figure 2-2 illustrates the factory settings for the
DIP switches.
resistors are not terminated to ground allowing line to line
termination. In the opposite (CLOSED) position the
center of the resistors are terminated to ground allowing
line to ground termination.
2.4 MAINFRAME OPERATION WITH THE
RS-449/530/MIL INTERFACE
2.4.1 Emulating Synchronous DTE
The FIREBERD mainframe generator clock and pattern
selections must be configured for operation with the
RS-449/530/MIL Interface. Figure 2-3 illustrates a simplified
block diagram of the FIREBERD emulating synchronous
DTE. The diagram shows the relationship between the gene-
rator clock, test pattern generator, receiver, and RS-449/530/
MIL Interface transmit and receive data and clock leads. Two
sets of pin numbers are identified: the EIA-530/MIL-188C
connector and the RS-449/MIL 188-114 which is in parenthe-
sis. See Table 2-1 for pin out descriptions.
NOTE:
Only Category I circuits are identified. See Table 2-1
for corresponding Category II circuits.
The generator clock selection establishes which clock
source is used during testing: the internal (INTRNL), inter-
face (INTF), or external (BNC). When the generator clock is
set to INTRNL, the mainframe supplies the clock source from
the internal generator clock which is used to generate the test
pattern on Pin 2 Transmitted Data (Pin 4 Send Data) and
supply the external transmit clock on Pin 24 Transmit Clock
DTE source (Pin 17 Terminal Timing DTE source). The DCE
transmit clock on Pin 15 Transmit Clock DCE source (Pin 5
Send Timing DCE source) is ignored when the internal
mainframe clock is used.
With the generator clock set to INTF, the clock on Pin 15
(Pin 5) is used as the transmit timing source for transmitting
the test pattern on Pin 2 (Pin 4). It also supplies the external
transmit clock on Pin 24 (Pin 17). Typically, the DCE supplies
transmit timing to the DTE on Pin 15 (Pin 5) and the DTE
(FIREBERD) generates the data (test pattern) from that clock
and redistributes the timing signal on Pin 24 (Pin 17) to the
DCE. Setting the generator clock for INTF is the recom-
mended selection when the FIREBERD is emulating DTE.
With the generator clock set for BNC, the mainframe is
supplied with the clock source through the GEN CLK IN
connector on the rear panel. The received data is clocked in
on Pin 3 Received Data (Pin 6 Receive Data) with the receive
clock from the DCE on Pin 17 Receive Clock (Pin 8 Receive
Timing) supplying the timing. Signal analysis is performed
on the received data and receive clock signals.
Figure 2-2
DIP Switch Factory Settings
Position 1 and Position 2 are not used.
Position 3 External Tx Clock Input -
This switch allows
the center of the two EXT TX CLK IN 62 ohm resistors
to be connected to ground. In the normal (OPEN)
position the two 62 ohm resistors are not terminated to
ground allowing line to line termination. In the opposite
(CLOSED) position the center of the resistors are termi-
nated to ground allowing line to ground termination.
Position 4 Receive Clock -
This switch allows the center
of the two RCV CLK 62 ohm resistors to be connected to
ground. In the normal (OPEN) position the two 62 ohm
resistors are not terminated to ground allowing line to line
termination. In the opposite (CLOSED) position the
center of the resistors are terminated to ground allowing
line to ground termination.
Position 5 Receive Data -
This switch allows the center
of the two RCV DATA 62 ohm resistors to be connected
to ground. In the normal (OPEN) position the two 62 ohm
1 2 3 4 5 6
Open
Closed
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