7-4. EDS Block Diagram
Fig. 7-4-1
CG
V Lock
MSGR
FR
PH2
PH1
1 Drive
Control
OSC
O / S
SYNC
Buffer
CHAR
Control
Line &
Digital
10
V / I
Ref
17
3
2
18
CKT
POR
Output
Logic
Logic
CG
Lines
& MUX
Slicer
Dual
Clamp
II Logic
Data CLK
Recovery
Field
CIR
SS CTR
Generator
Character
Display
RAM
MUX
Address
Latch
Display
Control Port
Serial
14
15
4
6
Stetus Rag
Test Rag
Row
Command
Processor
CW
SLS
SFLD
LS
FLD
Line &
Field
Decodes
M.SYNC
8
7
Buffer
VIDEO IN
CSYNC
Slice Level
SIG
SYNC
COMP
DIV
CLK
DOT
CHAR CLK
DOT CLK
Slicer
Data
PG
Lock
16
Sliced Data
SMS
FEW
Data Bus
13
SEN
SCK
SDA
SDO
Row
Latch
4
8
13
4
6
10
DEC
ADDR
9
5
HSYNC
LPF
Loop
Filter
1
11
Vss
Vss(A)
VW
VIN
Intro
SCL 1
SDA 1
Addr Bus
ADDR
Decoder
FLD
BOX
BLUE
GREEN
RED
AW
Data Line
IC402 Z86131