Toshiba TXZ+ Series Reference Manual Download

Page: 61 / 88

TXZ+ Family

TMPM4G Group(1)

Clock Control and Operation Mode

2021-06-30

Rev. 1.1

61 / 88

Structure

Single chip mode

M0
M1
M2
M3
M4
M5
M6
M7
M8
M9

M10
M11
M12
M13
M14

M0
M1
M2
M3
M4
M5
M6
M7
M8
M9

M10
M11
M12
M13
M14

SM1
SM2
SM3
SM4
SM5
SM6
SM7
SM8
SM9

SM10
SM11
SM12
SM13

SM1
SM2
SM3
SM4
SM5
SM6
SM7
SM8
SM9

SM10
SM11
SM12
SM13

SS3

SS4

SS3

SS4

MDM

AC NBDIF

HDMAC

UnitA

Cortex-M4

with FPU

Sys

tem

Ins

uct

ion

Code Flash

Instruction

Data

System

Data Flash

BootROM

RAM0
RAM1
RAM2

APB BUS0

IO BUS0

SMIF

SFR

Direct Area

EBIF

HDMAC UnitA

RAM3
RAM4
RAM5

Backup RAM

AO BUS

APB BUS1

IO BUS1
IO BUS2

APB

TSPI(SFR)
EBIF(SFR)

IB(INTIF)

RLM

LVD

LTTMR

IA(INTIF)

DNF
EI2C

I2S

TSSI

FIR

TSPI(SFR)

T32A

NDB(SFR)

MDMAC(SFR)

ADC

I2C

SIWDT
UARTB
FUART

DACIF

M4GRPORTx

PMD

FLASH(SFR)

TRM

OFD

RTC

RMC

ISD

CEC

High speed clock domain

Middle speed clock domain

HDMAC UnitB

HDMAC

UnitB

TRGSEL

SM0

MDM

AC NBDIF

SyncUp

SS5

SyncDn

M15

Dat

Ins

uct

ion

HDMAC

UnitA

Cortex-M4

with FPU

HDMAC

UnitB

IMN(INTIF)

Note1: NBDIF is not connected to M2, M3.
Note2: Access between the high speed domain and the middle speed domain requires synchronization time

between domains.

Figure 2.5 Single chip mode

Summary of Contents for TXZ+ Series

Page 1: ...ol and Operation Mode 2021 06 30 Rev 1 1 1 88 2020 2021 Toshiba Electronic Devices Storage Corporation 2021 06 32 bit RISC microcontroller TXZ Family TMPM4G Group 1 Reference Manual Clock Control and Operation Mode CG M4G 1 C Revision 1 1 ...

Page 2: ...d of a system clock 20 Low speed clock 22 ELOSC Setting No Operation of External Low Speed Oscillator Operation 22 ELCLKIN Setting No Operation of External Low Speed Oscillator Operation 22 Clock supply setting function 23 Prescaler clock 23 Operation mode 24 Details of an Operation mode 24 The feature in each mode 24 Transition to and Return from Low Power Consumption mode 25 Selection of a Low P...

Page 3: ... supply and stop register B for fsysm 44 CGFSYSENA High speed clock supply and stop register A for fsysh 46 CGFCEN Clock supply and stop register for fc 47 CGSPCLKEN Clock supply for ADC and Debug circuit Register 47 CGEXTEND2 Function extension register 2 48 RLMLOSCCR Low speed oscillation and Internal High speed oscillation 2 clock control register 48 RLMSHTDNOP Power supply cut off control regi...

Page 4: ...elease 80 Starting in reset and single boot mode 80 Start up by RESET_N Pin Signal 80 Start up by Power On Reset Not Using RESET_N Pin Signal 81 Starting in the single boot mode when power supply is stable 82 Power On Reset Circuit 83 Operation at the time of a power on 83 Operation at the time of turn off 83 Precautions when turning off the power 84 About turn on power supply after turn off 85 Af...

Page 5: ...2 4 TMPM4GxFD 59 Figure 2 5 Single chip mode 61 Figure 2 6 Single boot mode 62 Figure 3 1 The reset operation by a Power On Reset Circuit 75 Figure 3 2 Reset operation by a RESET_N pin 1 76 Figure 3 3 Reset operation by a RESET_N pin 2 77 Figure 3 4 The reset operation by LVD reset 78 Figure 3 5 Warm reset Operation 79 Figure 3 6 Starting in power supply is on and single boot mode 80 Figure 3 7 St...

Page 6: ... Release source list 31 Table 1 12 Warming up 32 Table 1 13 CGFSYSENA register corresponding to each product 50 Table 1 14 CGFSYSMENA register corresponding to each product 51 Table 1 15 CGFSYSMENB register corresponding to each product 52 Table 1 16 CGFSYSMENC register corresponding to each product 53 Table 1 17 CGFCEN register corresponding to each product 54 Table 2 1 TMPM4GxF20 Single chip mod...

Page 7: ...ion Mode 2021 06 30 Rev 1 1 7 88 Preface Related document Document name Arm Documentation of Cortex M4 Exception Input Output Ports Voltage Detection Circuit Selective Clock Watch Dog Timer Flash Memory Datasheet of Products Electrical Characteristics ...

Page 8: ... Example T32A0RUNA T32A1RUNA T32A2RUNA T32AxRUNA The bit range of a register is written like as m n Example Bit 3 0 expresses the range of bit 3 to 0 The configuration value of a register is expressed by either the hexadecimal number or the binary number Example ABCD EFG 0x01 hexadecimal XYZn VW 1 binary Word and Byte represent the following bit length Byte 8 bits Half word 16 bits Word 32 bits Do...

Page 9: ...6 30 Rev 1 1 9 88 All other company names product names and service names mentioned herein may be trademarks of their respective companies Arm Cortex and Thumb are registered trademarks of Arm Limited or its subsidiaries in the US and or elsewhere All rights reserved ...

Page 10: ... of SYSTEM Clock IHOSC Internal High Speed Oscillator INT Interrupt ISD Interval Sensing Detector I2C Inter Integrated Circuit I2S Inter IC Sound LTTMR Long Term Timer LVD Voltage Detection Circuit MDMA Multi function Direct Memory Access NMI Non Maskable Interrupt NBDIF Non Break Debug Interface OFD Oscillation Frequency Detector POR Power On Reset Circuit PORF Power On Reset Circuit for FLASH an...

Page 11: ...lock selected by CGPLL0SEL PLL0SEL High speed clock ELCLKIN The low speed clock input from the external fs A clock output from an external low speed oscillator fsysh A high speed system clock selected by CGSYSCR GEAR 2 0 fsysm A middle speed system clock selected by CGSYSCR GEAR 2 0 MCKSEL 1 0 ΦT0h A high speed clock selected by CGSYSCR PRCK 3 0 High speed prescaler clock ΦT0m A middle speed clock...

Page 12: ...owing states by a reset action External high speed oscillator Stop Internal high speed oscillator 1 Oscillation Internal high speed oscillator 2 Stop Note External low speed oscillator Stop PLL multiplying circuit Stop Gear clock fc no frequency dividing Note The state after the initialization done by the reset from the pin depends on RLMLOSCCR POSCEN setting ...

Page 13: ...8 1 16 1 8 1 4 1 2 1 32 1 256 1 512 fc 1 2 1 4 1 8 1 16 fosc fsysh Source clock control CGSPCLKEN ADCKEN EHCLKIN fIHOSC2 fsysh CPU 1 4 ELOSC PLL0 CGSYSCR MCKSEL 1 0 1 4 1 2 ΦT0m 1 4 1 2 CGFSYSMENA IPMENAx CGFSYSENA IPENAx ΦT0h Peripheral function prescaler inputs Middle speed prescaler clock FUART UART T32A TSPI6 to 8 I2S TSSI fsysm UART FUART I2C EI2C TSSI I2S T32A ADC DAC TSPI6 to 8 A PMD PORT T...

Page 14: ...ation Also when setting it before changes to the STOP1 mode calculate with the following formula and set CGWUPHCR WUPT 15 4 to the upper 12 bits of the result Lower 4bits are ignored Formula Using external high speed oscillator Warming up timer setting value 16 bits warming up time s clock period s 16 Example When 5ms of warming up time is set up with 10 MHz 100 ns of clock periods of oscillator W...

Page 15: ...ming up function are explained 1 Selection of a clock In a high speed oscillation the clock classification an internal oscillation external oscillation counted with a warming up timer is selected by CGWUPHCR WUCLK 2 Calculation of a warming up timer setting value The warming up time can set any value to the timer for a high speed oscillation for a low speed oscillation Please compute and set up fr...

Page 16: ...c The formula and the example of a setting of a PLL multiplication value The details of the items of CGPLL0SEL PLL0SET 23 0 which set up a PLL multiplication value are shown below Table 1 1 Details of a CGPLL0SEL PLL0SET 23 0 setup The items of PLL0SET Function 23 17 Correction value setup The quotient of fOSC 450000 integer For detail refer to the Table 1 2 16 14 fosc setup 000 6 fosc 7 Unit MHz ...

Page 17: ...alue 400 MHz Table 1 3 PLL0SET setting value example fosc MHz Multiplication value Dividing value fPLL MHz PLL0SET 23 0 8 00 50 0000 1 2 200 0x245032 10 00 40 0000 1 2 200 0x2E9028 12 00 33 3150 1 2 199 89 0x36D521 16 00 25 0000 1 2 200 0x495019 16 00 12 5000 1 2 100 0x49580C 20 00 20 0000 1 2 200 0x5B9014 24 00 16 6575 1 2 199 89 0x6D9A10 Change of the PLL multiplication value under operation To ...

Page 18: ...k should be changed Note2 3 to 6 are unnecessary when the state before switching is CGPLL0SEL PLL0ON 1 When changing from the state where the PLL output clock is stable it can be changed to the PLL operation state by execution of only 7 and 8 2 fc setup conduct PLL PLL stop As an fc setup the example of switching procedure from the PLL operation state to a PLL stop state is as follows The example ...

Page 19: ... can be changed during operation after register writing before the clock actually changes a time interval shown in Table 1 5 is required The completion of the clock change should be checked by CGSYSCR GEARST 2 0 MCKSELGST 1 0 Table 1 4 Clock domains of CPU and peripherals Clock domain Block High speed system clock CPU Code FLASH Data FLASH HDMAC EBIF SMIF TSPI ch0 to 5 CG INTIF RAM0 to 2 BootROM M...

Page 20: ...dure to the external high speed oscillation EHOSC from an internal high speed oscillation 1 IHOSC1 is shown below The example of switching procedure 1 PYPDN bit 1 0 00 PYPUP bit 1 0 00 PYIE bit 1 0 00 Disable the pull down resistors of X1 and X2 pins Disable the pull up resistors of X1 and X2 pins Disable input control of X1 and X2 pins 2 CGOSCCR EOSCEN 1 0 01 It is an external oscillation EHOSC a...

Page 21: ...witching procedure 1 CGWUPHCR WUCLK 0 Set the warming up clock selection to internal high speed oscillator1 IHOSC1 2 CGWUPHCR WUPT 15 4 0x03C Set the high speed oscillation warming up timer setting value of 163 4 μs 0x3C or more 3 CGOSCCR IHOSC1EN 1 An internal high speed oscillator1 is oscillated 4 CGWUPHCR WUON 1 Start the high speed oscillation warming up timer 5 Read CGWUPHCR WUEF Wait until a...

Page 22: ...eed Oscillator Operation An example of setting procedure is shown as follows to use the external low speed clock input ELCLKIN The example of switching procedure 1 PYPDN bit 2 0 PYPUP bit 2 0 PYIE bit 2 1 Disable the pull down resistor on XT1pin Disable the pull up resistor on XT1 pin Enable input control of TX1 ELCLKIN pin 2 RLMLOSCCR DRCOSCL 0 The external low speed clock source is set to the ex...

Page 23: ...ler circuit can be divided by the CGSYSCR PRCK 3 0 to generate High speed prescaler clock And Middle speed prescaler clock is generated by dividing High speed prescaler clock using CGSYSCR MCKSEL 1 0 For ΦT0 clock after reset fc is chosen After register writing before a clock actually changes a time interval shown in Table 1 8 is required To confirm the completion of the clock change check the sta...

Page 24: ...scillator is oscillating and it shifts to STOP1 mode RTC CEC RMC and ISD operate If it shifts to STOP1 mode when the internal high speed oscillator2 IHOSC2 is oscillating and LTTMR is selected as a sample clock CEC and RMC operate If STOP1 mode is canceled the internal high speed oscillator1 IHOSC1 will start oscillation and the system will return to NORMAL mode Please disable interrupt which is n...

Page 25: ...pt command is executed When the transition to the low power consumption mode has been done by WFI instruction the return from the mode can be done by the reset or an interrupt generation To return by interrupt it is necessary to set up Please refer to interrupt chapter of a reference manual Exception for details Note1 This product does not support a return by events therefore do not make a transit...

Page 26: ...LTTMR Note5 Note5 Note5 Note5 Note5 Note5 RTC RMC Note4 CEC Note4 ISD SIWDT Note2 x x LVD OFD x x TRM Unavailable x x CG x x PLL x x External High speed oscillator EHOSC x x Internal High speed oscillator 1 IHOSC1 x x Internal High speed oscillator 2 IHOSC2 Note5 Note5 Note5 Note5 Note5 Note5 External Low speed oscillator ELOSC RLM Note7 Code Flash Access Possible Access Possible Note6 Data hold D...

Page 27: ...led by setting LTTMR as a sampling clock Note5 This function is enabled when RLMLOSCCR POSCEN is set to 1 Note6 It becomes a data hold when peripheral functions DMA etc which carry out data access R W except CPU are not connected on the bus matrix Note7 RLM means the registers to control the power the low speed oscillator and others in the region where the power is not cut off ...

Page 28: ...from STOP2 mode the MCU branches to the interrupt service routine triggered by reset When the MCU returns from STOP1 mode the MCU branches to the interrupt service routine triggered by interrupt events IDLE mode transition flow Set up the following procedure at switching to IDLE mode Because IDLE mode is released by an interrupt set the interrupt before switching to IDLE mode For the interrupts th...

Page 29: ... STBY 1 0 01 Low Power Consumption mode selection is set to STOP1 7 CGPLL0SEL PLL0SEL 0 Set PLL of fsys to fosc PLL no USE 8 CGPLL0SEL PLL0ST is read Wait until PLL status of fsys becomes off state 0 9 CGPLL0SEL PLL0ON 0 Stop PLL for fsys 10 CGOSCCR IHOSC1EN 1 Enable the internal high speed oscillator1 11 CGWUPHCR WUON 1 Start the high speed oscillation warming up timer 12 CGWUPHCR WUEF is read Wa...

Page 30: ...d oscillator 1 IHOSC1 Set the high speed oscillation warming up timer to 163 4 μs 0x03C or more 10 CGOSCCR IHOSC1EN 1 Enable the internal high speed oscillator 11 CGWUPHCR WUON 1 Start the high speed oscillation warming up timer 12 CGWUPHCR WUEF is read Wait until the warming up timer status flag becomes ends 0 13 CGOSCCR OSCSEL 0 High speed oscillation selection for fosc is set to the inside IHOS...

Page 31: ...NTMDMAxTC INTMDMAxBERR INTMDMAxDERR x x INT32Ax_A_CT INT32Ax_B_Cx_CPC x x INTADxCP0 INTADxCP1 INTADxTRG INTADxSGL INTADxCNT INTADxHP x x INTEMGx INTOVVx INTPWMx x x INTTxRX INTTxTX INTTxERR x x INTSMIx x x INTUARTxRX INTUARTxTX INTUARTxERR x x INTFUARTx x x INTFLCRDY INTFLDRDY x x INTI2CxNST INTI2CxATX INTI2CxBX INTI2CxNA x x INTI2SxSI INTI2SxSIERR INTI2SxSO INTI2SxSOERR x x INTFIR x x INTISSIxRX ...

Page 32: ...pter of a reference manual of Exception about the details of interrupt Warming up at the release of Low Power Consumption mode Warming up may be required because of stability of an internal oscillator at the time of mode transition When the transition from STOP1 mode to NORMAL mode is done the internal oscillation is selected automatically and the warming up timer starts up The Output of a system ...

Page 33: ...he case of interrupt and a reset pin Refer to 3 2 8 1 A reset factor and the reset range for detail Release factor generating Check reset flag Note1 RLMRSTFLGx xx it is checked by which factor reset has occurred Release the port state hold function Initial setting at the return of STOP2 and re setup of the port registers RLMSHTDNOP PTKEEP 0 possible to control a port It returns to NORMAL mode with...

Page 34: ...t point of the transition command WFI will be done after the interrupt processing by release source NORMAL STOP1 NORMAL Operation mode transition When returning to NORMAL mode from the STOP1 mode warming up is started automatically Please set warming up time 163 4 µs or more with CGWUPHCR WUPT 15 4 Note When releasing factor is RESET_N pin or LVD reset CPU operation is started after the internal p...

Page 35: ...in or LVD reset CPU operation is started after the internal processing time for reset and the waiting time till CPU running not the warming up time elapse When reset factor is not released after the internal processing time for reset elapses starts measuring elapsed time after releasing reset factor CPU operation is started after the waiting time till CPU running elapse Internal processing time fo...

Page 36: ...le speed clock supply and stop register C for fsysm CGFSYSMENC 0x0044 Middle speed clock supply and stop register A for fsysm CGFSYSMENA 0x0048 Middle speed clock supply and stop register B for fsysm CGFSYSMENB 0x004C High speed clock supply and stop register A for fsysh CGFSYSENA 0x0050 Clock supply and stop register for fc CGFCEN 0x0058 Clock supply for ADC and Debug circuit Register CGSPCLKEN 0...

Page 37: ...OSC1 1 External high speed oscillator EHOSC 8 OSCSEL 0 R W Selects a high speed oscillation for fosc Note1 0 Internal high speed oscillator 1 IHOSC1 1 External high speed oscillator EHOSC 7 4 0 R Read as 0 3 0 R W Write as 0 2 1 EOSCEN 1 0 00 R W Selects the operation of the external high speed oscillator EHOSC Note2 00 External oscillator is not used 01 Uses the external high speed oscillator EHO...

Page 38: ... GEAR 2 0 setting value is divided by 4 21 19 0 R Read as 0 18 16 GEARST 2 0 000 R High speed system clock fsysh gear selection status 000 fc 100 fc 16 001 fc 2 101 to 111 Reserved 010 fc 4 011 fc 8 15 12 0 R Read as 0 11 8 PRCK 3 0 0000 R W High speed prescaler clock ΦT0h selection 0000 fc 0100 fc 16 1000 fc 256 0001 fc 2 0101 fc 32 1001 fc 512 0010 fc 4 0110 fc 64 1010 to 1111 Reserved 0011 fc 8...

Page 39: ... CGPLL0SEL PLL selection register for fsys Bit Bit Symbol After reset Type Function 31 8 PLL0SET 23 0 0x000000 R W PLL multiplication setup About a multiplication setup refer to the 1 2 5 2The formula and the example of a setting of a PLL multiplication value 7 3 0 R Read as 0 2 PLL0ST 0 R Indicates PLL for fsys selection status 0 fosc 1 fPLL 1 PLL0SEL 0 R W Selects Clock selection for fsys 0 fosc...

Page 40: ...e 1 Warming up operation start Note1 Use the internal oscillator for warming up when the MCU returns from STOP1 mode Do not use an external oscillator when the MCU returns from STOP1 mode Note2 Do not modify the registers during the warming up WUEF 1 Set the registers when WUEF 0 CGWUPLCR Low speed oscillation warming up register Bit Bit Symbol After reset Type Function 31 27 0 R Read as 0 26 12 W...

Page 41: ...C ch2 0 Clock stop 1 Clock supply 6 IPMENC06 0 R W Clock enable of EI2C ch1 0 Clock stop 1 Clock supply 5 IPMENC05 0 R W Clock enable of EI2C ch0 0 Clock stop 1 Clock supply 4 IPMENC04 0 R W Clock enable of TSSI ch1 0 Clock stop 1 Clock supply 3 IPMENC03 0 R W Clock enable of TSSI ch0 0 Clock stop 1 Clock supply 2 IPMENC02 0 R W Clock enable of FIR 0 Clock stop 1 Clock supply 1 IPMENC01 0 R W Cloc...

Page 42: ... Clock supply 23 IPMENA23 1 R W Clock enable of UART ch0 0 Clock stop 1 Clock supply 22 IPMENA22 0 R W Clock enable of TSPI ch8 0 Clock stop 1 Clock supply 21 IPMENA21 0 R W Clock enable of TSPI ch7 0 Clock stop 1 Clock supply 20 IPMENA20 0 R W Clock enable of TSPI ch6 0 Clock stop 1 Clock supply 19 IPMENA19 0 R W Clock enable of T32A ch13 0 Clock stop 1 Clock supply 18 IPMENA18 0 R W Clock enable...

Page 43: ...ply 5 IPMENA05 0 R W Clock enable of DAC ch1 0 Clock stop 1 Clock supply 4 IPMENA04 0 R W Clock enable of DAC ch0 0 Clock stop 1 Clock supply 3 IPMENA03 0 R W Clock enable of ADC Unit A 0 Clock stop 1 Clock supply 2 IPMENA02 0 R W Clock enable of FUART ch1 0 Clock stop 1 Clock supply 1 IPMENA01 0 R W Clock enable of FUART ch0 0 Clock stop 1 Clock supply 0 IPMENA00 0 R W Clock enable of MDMAC Unit ...

Page 44: ...ock supply 20 IPMENB20 0 R W Clock enable of PORT W 0 Clock stop 1 Clock supply 19 IPMENB19 0 R W Clock enable of PORT V 0 Clock stop 1 Clock supply 18 IPMENB18 0 R W Clock enable of PORT U 0 Clock stop 1 Clock supply 17 IPMENB17 0 R W Clock enable of PORT T 0 Clock stop 1 Clock supply 16 IPMENB16 0 R W Clock enable of PORT R 0 Clock stop 1 Clock supply 15 IPMENB15 0 R W Clock enable of PORT P 0 C...

Page 45: ...f PORT C 0 Clock stop 1 Clock supply 3 IPMENB03 0 R W Clock enable of PORT B 0 Clock stop 1 Clock supply 2 IPMENB02 0 R W Clock enable of PORT A 0 Clock stop 1 Clock supply 1 IPMENB01 0 R W Clock enable of I2 C ch4 0 Clock stop 1 Clock supply 0 IPMENB00 0 R W Clock enable of I2 C ch3 0 Clock stop 1 Clock supply Note1 Even if the initial value of the register is set to stop of the clock the clock i...

Page 46: ...ck supply 5 IPENA05 0 R W Clock enable of TSPI ch1 0 Clock stop 1 Clock supply 4 IPENA04 0 R W Clock enable of TSPI ch0 0 Clock stop 1 Clock supply 3 IPENA03 0 R W Clock enable of EBIF 0 Clock stop 1 Clock supply 2 IPENA02 0 R W Clock enable of SMIF ch0 0 Clock stop 1 Clock supply 1 IPENA01 0 R W Clock enable of HDMAC Unit B 0 Clock stop 1 Clock supply 0 IPENA00 0 R W Clock enable of HDMAC Unit A ...

Page 47: ...n use the monitor clock of fc CGFSYSMENB IPMENB23 and CGFCEN FCIPEN23 should be enabled Note2 Even if the initial value of the register is set to stop of the clock the clock is supplied during the reset Note3 Write 0 for bit of function that does not exist in TMPM4GQ and TMPM4GN Refer to 1 5 Information according to product for detail CGSPCLKEN Clock supply for ADC and Debug circuit Register Bit B...

Page 48: ...ock fsysm or more should elapse before 0 is set Note When an error flag should be cleared it is necessary to assert the software reset RSV22 too RLMLOSCCR Low speed oscillation and Internal High speed oscillation 2 clock control register Bit Bit Symbol After reset Type Function 7 6 0 R Read as 0 5 POSCF 0 R Indicates the stability flag of internal oscillation for IHOSC2 0 Stopping or being in warm...

Page 49: ...Note1 It is a register accessed per byte Bit band access is not allowed Note2 When you rewrite please read the register and check rewriting RLMPROTECT RLM write protection register Bit Bit Symbol After reset Type Function 7 0 PROTECT 0xC1 R W RLM register write protection control 0xC1 Write enable to an RLM register protection release except 0xC1 Write disable to an RLM register The writing to RLM...

Page 50: ...heral circuit Channel No Port name M4GR M4GQ M4GN 31 IPENA31 x x x 30 IPENA30 x x x 29 IPENA29 x x x 28 IPENA28 x x x 27 IPENA27 x x x 26 IPENA26 x x x 25 IPENA25 x x x 24 IPENA24 x x x 23 IPENA23 x x x 22 IPENA22 x x x 21 IPENA21 x x x 20 IPENA20 x x x 19 IPENA19 x x x 18 IPENA18 x x x 17 IPENA17 x x x 16 IPENA16 x x x 15 IPENA15 x x x 14 IPENA14 x x x 13 IPENA13 x x x 12 IPENA12 x x x 11 IPENA11...

Page 51: ...NA30 1 29 IPMENA29 0 28 IPMENA28 UART 5 x x 27 IPMENA27 4 x 26 IPMENA26 3 x 25 IPMENA25 2 24 IPMENA24 1 23 IPMENA23 0 22 IPMENA22 TSPI 8 x x 21 IPMENA21 7 x 20 IPMENA20 6 x 19 IPMENA19 T32A 13 18 IPMENA18 12 17 IPMENA17 11 16 IPMENA16 10 15 IPMENA15 9 14 IPMENA14 8 13 IPMENA13 7 12 IPMENA12 6 11 IPMENA11 5 10 IPMENA10 4 9 IPMENA09 3 8 IPMENA08 2 7 IPMENA07 1 6 IPMENA06 0 5 IPMENA05 DAC 1 4 IPMENA0...

Page 52: ...Note x x x 28 IPMENB28 TRGSEL 0 27 IPMENB27 x x x 26 IPMENB26 x x x 25 IPMENB25 x x x 24 IPMENB24 A PMD 0 23 IPMENB23 OFD 22 IPMENB22 TRM 21 IPMENB21 PORT Y 20 IPMENB20 W x x 19 IPMENB19 V x 18 IPMENB18 U x x 17 IPMENB17 T 16 IPMENB16 R x 15 IPMENB15 P 14 IPMENB14 N 13 IPMENB13 M x 12 IPMENB12 L 11 IPMENB11 K 10 IPMENB10 J x x 9 IPMENB09 H 8 IPMENB08 G 7 IPMENB07 F 6 IPMENB06 E 5 IPMENB05 D 4 IPME...

Page 53: ...x 28 IPMENC28 x x x 27 IPMENC27 x x x 26 IPMENC26 x x x 25 IPMENC25 x x x 24 IPMENC24 x x x 23 IPMENC23 x x x 22 IPMENC22 x x x 21 IPMENC21 x x x 20 IPMENC20 x x x 19 IPMENC19 x x x 18 IPMENC18 x x x 17 IPMENC17 x x x 16 IPMENC16 T32A 15 15 IPMENC15 14 14 IPMENC14 x x x 13 IPMENC13 x x x 12 IPMENC12 x x x 11 IPMENC11 x x x 10 IPMENC10 x x x 9 IPMENC09 EI2C 4 x 8 IPMENC08 3 x 7 IPMENC07 2 6 IPMENC0...

Page 54: ...PEN28 x x x 27 FCIPEN27 DNF B 26 FCIPEN26 A 25 FCIPEN25 x x x 24 FCIPEN24 x x x 23 FCIPEN23 OFD 22 FCIPEN22 x x x 21 FCIPEN21 x x x 20 FCIPEN20 x x x 19 FCIPEN19 x x x 18 FCIPEN18 x x x 17 FCIPEN17 x x x 16 FCIPEN16 x x x 15 FCIPEN15 x x x 14 FCIPEN14 x x x 13 FCIPEN13 x x x 12 FCIPEN12 x x x 11 FCIPEN11 x x x 10 FCIPEN10 x x x 9 FCIPEN09 x x x 8 FCIPEN08 x x x 7 FCIPEN07 x x x 6 FCIPEN06 x x x 5 ...

Page 55: ...eripheral regions of the Cortex M4 with FPU respectively The special function register SFR means the control registers of all input output ports and peripheral functions The CPU register region is the processor core s internal register region For more information on each region see the Arm documentation set Cortex M4 Note that access to regions indicated as Fault causes a bus fault if bus faults a...

Page 56: ...1C0000 Bit Band Alias Bit Band Alias RAM Backup RAM RAM Backup RAM 0x22000000 0x22000000 0x20040000 0x20040800 0x20038000 Backup RAM 2 KB 0x20030000 Backup RAM 2 KB 0x20010000 0x20000000 Fault Fault Code Flash 0x00008000 2048 KB Boot ROM 0x00000000 0x00000000 32 KB Single chip Mode Single Boot Mode Fault Fault Fault Fault Fault Fault Fault Fault Flash SFR Flash SFR 0x5E200000 0x5E200000 Fault CPU ...

Page 57: ...Bit Band Alias RAM Backup RAM RAM Backup RAM 0x22000000 0x22000000 0x20040000 0x20040800 0x20038000 Backup RAM 2 KB 0x20030000 Backup RAM 2 KB 0x20010000 0x20000000 Fault Fault Code Flash 0x00008000 1536 KB Boot ROM 0x00000000 0x00000000 32 KB Single chip Mode Single Boot Mode Fault Fault Fault Fault Fault Fault Fault Fault Flash SFR Flash SFR 0x5E200000 0x5E200000 Fault CPU Register Region CPU Re...

Page 58: ...0 Bit Band Alias Bit Band Alias RAM Backup RAM RAM Backup RAM 0x22000000 0x22000000 0x20040000 0x20040800 0x20038000 Backup RAM 2 KB 0x20030000 Backup RAM 2 KB 0x20010000 0x20000000 Fault Fault Code Flash 0x00008000 1024 KB Boot ROM 0x00000000 0x00000000 32 KB Single chip Mode Single Boot Mode Fault Fault Fault Fault Fault Fault Fault Fault Flash SFR Flash SFR 0x5E100000 0x5E100000 Fault CPU Regis...

Page 59: ...21C0000 Bit Band Alias Bit Band Alias RAM Backup RAM RAM Backup RAM 0x22000000 0x22000000 0x20040000 0x20040800 0x20038000 Backup RAM 2 KB Backup RAM 2 KB 0x20010000 0x20000000 Fault Fault Code Flash 0x00008000 512 KB Boot ROM 0x00000000 0x00000000 32 KB Single chip Mode Single Boot Mode Fault Fault Fault Fault Fault Fault Fault Fault Flash SFR Flash SFR 0x5E100000 0x5E100000 Fault CPU Register Re...

Page 60: ...th and in the following figures mean connected and shows a connection to a mirror area The master ports are connected to sub master and peripheral devices The signals of the sub master are connected to the slave ports SS0 to SS2 of the bus matrix In the bus matrix the signals of the slave ports are selectively connected to the sub ports SM0 to SM6 Both and in the following figures mean connected T...

Page 61: ...M2 APB BUS0 IO BUS0 SMIF SFR Direct Area EBIF HDMAC UnitA RAM3 RAM4 RAM5 Backup RAM AO BUS APB BUS1 IO BUS1 IO BUS2 AO APB IO IO APB IO TSPI SFR EBIF SFR CG IB INTIF RLM LVD LTTMR IA INTIF DNF EI2C I2S TSSI FIR TSPI SFR T32A NDB SFR MDMAC SFR ADC I2C SIWDT UARTB FUART DACIF M4GRPORTx PMD FLASH SFR TRM OFD RTC RMC ISD CEC High speed clock domain Middle speed clock domain HDMAC UnitB HDMAC UnitB TRG...

Page 62: ...PB BUS0 IO BUS0 SMIF SFR Direct Area EBIF HDMAC UnitA RAM3 RAM4 RAM5 Backup RAM AO BUS APB BUS1 IO BUS1 IO BUS2 AO APB IO IO APB IO TSPI SFR EBIF SFR CG IB INTIF RLM LVD LTTMR IA INTIF DNF EI2C I2S TSSI FIR TSPI SFR T32A NDB SFR MDMAC SFR ADC I2C SIWDT UARTB FUART DACIF M4GRPORTx PMD FLASH SFR TRM OFD RTC RMC ISD CEC High speed clock domain Middle speed clock domain HDMAC UnitB HDMAC UnitB TRGSEL ...

Page 63: ...0x20010000 RAM1 M6 0x20020000 RAM2 M7 0x20028000 RAM3 SM1 Fault Fault 0x20030000 RAM4 SM2 Fault Fault 0x20038000 RAM5 SM3 Fault Fault 0x20040000 Backup RAM SM4 Fault Fault Fault 0x20040800 Fault Fault Fault Fault Fault Fault 0x22000000 Bit band alias 0x221C0000 Fault Fault Fault Fault Fault Fault 0x30000000 Data Flash M3 Fault 0x30008000 Fault Fault Fault Fault Fault Fault For the address of this ...

Page 64: ...lt 0x20040000 Backup RAM SM4 Fault Fault Fault 0x20040800 Fault Fault Fault Fault Fault Fault 0x22000000 Bit band alias Fault Fault Fault Fault Fault 0x221C0000 Fault Fault Fault Fault Fault Fault 0x30000000 Data Flash M3 Fault 0x30008000 Fault Fault Fault Fault Fault Fault Fault Fault 0x3F7F8000 Boot ROM Mirror M4 Fault Fault Fault Fault 0x3F800000 Fault Fault Fault Fault Fault Fault Fault Fault ...

Page 65: ... RAM2 M7 0x20028000 RAM3 SM1 Fault Fault 0x20030000 RAM4 SM2 Fault Fault 0x20038000 RAM5 SM3 Fault Fault 0x20040000 Backup RAM SM4 Fault Fault Fault 0x20040800 Fault Fault Fault Fault Fault Fault 0x22000000 Bit band alias 0x221C0000 Fault Fault Fault Fault Fault Fault 0x30000000 Data Flash M3 Fault 0x30008000 Fault Fault Fault Fault Fault Fault For the address of this area refer to Table 2 9 Perip...

Page 66: ...Fault 0x20040800 Fault Fault Fault Fault Fault Fault 0x22000000 Bit band alias Fault Fault Fault Fault Fault 0x221C0000 Fault Fault Fault Fault Fault Fault 0x30000000 Data Flash M3 Fault 0x30008000 Fault Fault Fault Fault Fault Fault Fault Fault 0x3F7F8000 Boot ROM Mirror M4 Fault Fault Fault Fault 0x3F800000 Fault Fault Fault Fault Fault Fault Fault Fault For the address of this area refer to Tab...

Page 67: ...M7 0x20028000 RAM3 SM1 Fault Fault 0x20030000 RAM4 SM2 Fault Fault 0x20038000 RAM5 SM3 Fault Fault 0x20040000 Backup RAM SM4 Fault Fault Fault 0x20040800 Fault Fault Fault Fault Fault Fault 0x22000000 Bit band alias 0x221C0000 Fault Fault Fault Fault Fault Fault 0x30000000 Data Flash M3 Fault 0x30008000 Fault Fault Fault Fault Fault Fault For the address of this area refer to Table 2 9 Peripheral ...

Page 68: ...lt 0x20040000 Backup RAM SM4 Fault Fault Fault 0x20040800 Fault Fault Fault Fault Fault Fault 0x22000000 Bit band alias Fault Fault Fault Fault Fault 0x221C0000 Fault Fault Fault Fault Fault Fault 0x30000000 Data Flash M3 Fault 0x30008000 Fault Fault Fault Fault Fault Fault Fault Fault 0x3F7F8000 Boot ROM Mirror M4 Fault Fault Fault Fault 0x3F800000 Fault Fault Fault Fault Fault Fault Fault Fault ...

Page 69: ...eserved Reserved Reserved Reserved Reserved Reserved 0x20030000 RAM4 SM2 Fault Fault 0x20038000 RAM5 SM3 Fault Fault 0x20040000 Backup RAM SM4 Fault Fault Fault 0x20040800 Fault Fault Fault Fault Fault Fault 0x22000000 Bit band alias 0x221C0000 Fault Fault Fault Fault Fault Fault 0x30000000 Data Flash M3 Fault 0x30008000 Fault Fault Fault Fault Fault Fault For the address of this area refer to Tab...

Page 70: ...Fault Fault Fault 0x20040800 Fault Fault Fault Fault Fault Fault 0x22000000 Bit band alias Fault Fault Fault Fault Fault 0x221C0000 Fault Fault Fault Fault Fault Fault 0x30000000 Data Flash M3 Fault 0x30008000 Fault Fault Fault Fault Fault Fault Fault Fault 0x3F7F8000 Boot ROM Mirror M4 Fault Fault Fault Fault 0x3F800000 Fault Fault Fault Fault Fault Fault Fault Fault For the address of this area ...

Page 71: ...6 Fault Fault 0x400A0400 TRGSEL SM6 Fault Fault 0x400A0600 SIWDT SM6 Fault Fault 0x400A2000 NBDIF SM6 Fault Fault 0x400A4000 MDMAC SM6 Fault Fault 0x400A8000 FUART ch0 1 SM6 Fault Fault 0x400BA000 ADC SM6 Fault Fault 0x400BC800 DAC ch0 1 SM6 Fault Fault 0x400C1000 T32A ch0 15 SM6 Fault Fault 0x400CB800 TSPI ch6 8 SM6 Fault Fault 0x400CD000 TSSI ch0 1 SM6 Fault Fault 0x400CE000 UART ch0 5 SM6 Fault...

Page 72: ... 5 Control Registers Change the setting according to the fsysh frequency Peripheral Function Channel Unit Base Address Type 1 FC 0x5DFF0000 Register Name Address Base Flash Key Code Register Note FCKCR 0x0018 RAM Access Control Register FCRACCR 0x1218 Note This register is same as the register of the reference manual Flash memory FCKCR Flash Key Code Register Bit Bit Symbol After reset Type Functi...

Page 73: ...h 160MHz Others Reserved 3 2 0 R Read as 0 1 0 00 R W Write as 00 Note1 Rewrite the contents of this register on the program code in the Flash memory Note2 To rewrite this register follow the procedure below 1 Write the specific code 0xA74A9D23 to FCKCR 2 Rewrite data of FCRACCR RAMLC1 1 0 within 16 clocks after Procedure 1 3 After wrote check read data is same as wrote data Note3 When using clock...

Page 74: ...2 mode STOP2REQ Reset pin Reset by a RESET_N pin LVD reset Reset when DVDD3 is equal or less than the voltage which is set on LVD circuit Single boot start up MCU is started by the internal boot ROM is used after the reset deassertion Function and Operation This section explain about power on power off and reset Note Refer to the Electrical Characteristics of a datasheet for the time and voltage o...

Page 75: ...uring the time of Internal initialization time When rising time of a supply voltage beyond Internal initialization time please refer to 3 2 1 3 Reset extension by LVD For example if the operating voltage of a circuit board is more than 2 7V after Power On Reset released increase a supply voltage to 2 7V before Internal initialization time is elapsed DVDD3 DVDD3A DVDD3B DVDD3C DVDD3D DVDD3E DVDD3F ...

Page 76: ...tinues After a supply voltage goes up into an operating voltage range if a RESET_N pin becomes High Internal reset is deasserted after CPU waiting time elapses DVDD3 DVDD3A DVDD3B DVDD3C DVDD3D DVDD3E DVDD3F DVDD3G DVDD3H AVDD3 DVDD3 Operating Voltage range LVD Release voltage VLVL0 POR release voltage VPREL 0V RESET_N pin LVD reset Internal reset Internal initialization time tIINIT CPU Operation ...

Page 77: ... operating voltage range before Internal initialization time elapses The CPU operates after internal reset release DVDD3 DVDD3A DVDD3B DVDD3C DVDD3D DVDD3E DVDD3F DVDD3G DVDD3H AVDD3 DVDD3 Operating Voltage range LVD Release voltage VLVL0 POR Release voltage VPREL 0V RESET_N pin LVD reset Internal reset Internal initialization time tIINIT CPU Operation start LVD detection release time tVDDT2 Power...

Page 78: ...ase time CPU operation wait time elapses the internal reset is deasserted And CPU starts operating Refer to Reference Manual Voltage detection circuit for detail of LVD DVDD3 DVDD3A DVDD3B DVDD3C DVDD3D DVDD3E DVDD3F DVDD3G DVDD3H AVDD3 DVDD3 Operating Voltage range LVD Release voltage VLVL0 POR Release voltage VPREL 0V RESET_N pin LVD reset Internal reset Internal initialization time tIINIT CPU O...

Page 79: ...reset is release after Internal processing time CPU waiting time has elapsed internal reset will be released DVDD3 DVDD3A DVDD3B DVDD3C DVDD3D DVDD3E DVDD3F DVDD3G DVDD3H AVDD3 DVDD3 Operating Voltage range RESET_N pin Internal reset Internal processing time tIRST CPU Operation start CPU waiting time tCPUWT RESET_N pin Internal reset CPU waiting time tCPUWT CPU Operation start When RESET_N pin res...

Page 80: ...ng in reset and single boot mode For the details of the single mode refer to the reference manual Flash memory Start up by RESET_N Pin Signal When Low is inputted to a BOOT_N pin reset release single boot mode will be started When turn on power supply input Low to the RESET_N pin longer than Internal initialization time to reset And deassert RESET_N pin to High after a supply voltage goes up into ...

Page 81: ...de starts up DVDD3 DVDD3A DVDD3B DVDD3C DVDD3D DVDD3E DVDD3F DVDD3G DVDD3H AVDD3 DVDD3 Operating Voltage Rage LVD Release Voltage VLVL0 POR Release Voltage VPREL 0V RESET_N pin LVD reset Internal reset Internal initialization time tIINIT CPU Operation start Control internal Pull up of BOOT_N pin BOOT_N pin ON Single boot mode OFF OFF Low level input Single boot mode Open LVD detection release time...

Page 82: ...cessing time while Low is inputted to the BOOT_N pin And deassert RESET_N pin to High DVDD3 DVDD3A DVDD3B DVDD3C DVDD3D DVDD3E DVDD3F DVDD3G DVDD3H AVDD3 DVDD3 Operating Voltage range RESET_N pin Internal reset CPU Operation start CPU waiting time tCPUWT Internal processing time tIRST Control internal Pull up of BOOT_N pin BOOT_N pin ON Single Boot Mode OFF OFF Low level input Single Boot Mode Ope...

Page 83: ...ction Voltage generation circuit Reference voltage generation circuit PORHV Power on Reset detection Comparator Supply voltage Figure 3 9 Power On Reset Circuit Operation at the time of a power on When turn on power supply while the power supply voltage is lower than Power On Reset Circuit release voltage VPREL the Power On Reset detection signal is generated Refer to Figure 3 1 The reset operatio...

Page 84: ... voltage DVDD3 DVDD3A DVDD3B DVDD3C DVDD3D DVDD3E DVDD3F DVDD3G DVDD3H AVDD3 DVDD3 Operation Voltage range LVD detection voltage VLVL1 POR detection voltage VPRED 0V Power off falling gradient VPOFF PORF detection voltage VPORFD Figure 3 10 Falling gradient when turning off the power Flash memory and circuits that include debug are reset by PORF reset Refer to 3 2 8 1 A reset factor and the reset ...

Page 85: ...and hold it for 200μs or more After that please follow the same constraints as when turning on the power and turned on the power supply voltage When the power supply voltage drops below the Power On Reset detection voltage VPDET and cannot be held for 200μs or more or when the same constraints as at power on cannot keep the CPU may not operate properly After reset release All of the control regist...

Page 86: ...URR RTCDAYR RTCDATER RTCMONTHR RTCYEARR RTCADJCTL RTCADJDAT RTCADJSIGN RTCPAGER Note2 Except the above Low speed oscillation Power control Reset flag RLMSHTDNOP RLMPROTECT RLMLOSCCR RLMRSTFLG0 RLMRSTFLG1 Interrupt Control IAIMCxx IANIC00 IBIMCxxx IBNIC00 FLASH FCSBMR Note4 Note4 Port All the registers OFD LVD LTTMR ISD RMC CEC Debugging interface Note4 Note4 Except the above It is initialized It i...

Page 87: ...n from the STOP2 mode Change Note2 to Note3 and Note3 is corrected Added Note2 1 3 4 2 NORMAL ISTOP1 INORMAL Operation mode transition Added Note 3 1 Outline Table Added LVD reset factor 3 2 3 Reset by STOP2 mode release Changed description Table 3 1 A reset factor and the initialized range Added Note3 in STOP2 Release Reset pin column Added Note4 to FLASH FCSBMR and Debugging interface in Warm re...

Page 88: ...d or life supporting medical equipment equipment used for automobiles trains ships and other transportation traffic signaling equipment equipment used to control combustions or explosions safety devices elevators and escalators and devices related to power plant IF YOU USE PRODUCT FOR UNINTENDED USE TOSHIBA ASSUMES NO LIABILITY FOR PRODUCT For details please contact your TOSHIBA sales representati...

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