TXZ+ Family
TMPM4G Group(1)
Clock Control and Operation Mode
2021-06-30
Rev. 1.1
46 / 88
[CGFSYSENA]
(High speed clock supply and stop register A for fsysh)
Bit
Bit Symbol
After
reset
Type
Function
31:10
-
0
R
Read as “0”
9
IPENA09
0
R/W
Clock enable of TSPI ch5
0: Clock stop
1: Clock supply
8
IPENA08
0
R/W
Clock enable of TSPI ch4
0: Clock stop
1: Clock supply
7
IPENA07
0
R/W
Clock enable of TSPI ch3
0: Clock stop
1: Clock supply
6
IPENA06
0
R/W
Clock enable of TSPI ch2
0: Clock stop
1: Clock supply
5
IPENA05
0
R/W
Clock enable of TSPI ch1
0: Clock stop
1: Clock supply
4
IPENA04
0
R/W
Clock enable of TSPI ch0
0: Clock stop
1: Clock supply
3
IPENA03
0
R/W
Clock enable of EBIF
0: Clock stop
1: Clock supply
2
IPENA02
0
R/W
Clock enable of SMIF ch0
0: Clock stop
1: Clock supply
1
IPENA01
0
R/W
Clock enable of HDMAC Unit B
0: Clock stop
1: Clock supply
0
IPENA00
0
R/W
Clock enable of HDMAC Unit A
0: Clock stop
1: Clock supply
Note1: Even if the initial value of the register is set to stop of the clock, the clock is supplied during the reset.
Note2: Write “0” for bit of function that does not exist in TMPM4GQ and TMPM4GN. Refer to “1.5. Information
according to product” for detail.