Toshiba TLCS-900 Family Data Book Download | Manualshive

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TMP92CZ26A

92CZ26A-318

(2) Baud rate generator

The baud rate generator is the circuit which generates transmission/receiving clock

and determines the transfer rate of the serial channels.

The input clock to the baud rate generator,

φ

T0,

φ

T2,

φ

T8 or

φ

T32, is generated by

the 6-bit prescaler which is shared by the timers. One of these input clocks is selected
using the BR0CR<BR0CK1:0> field in the baud rate generator control register.

The baud rate generator includes a frequency divider, which divides the frequency

by 1 or N

+

(16

−

K)/16 to 16 values, determining the transfer rate.

The transfer rate is determined by the settings of BR0CR<BR0ADDE, BR0S3:0>

and BR0ADD<BR0K3:0>.

•

In UART mode

When BR0CR<BR0ADDE>

=

0

The settings BR0ADD<BR0K3:0> are ignored. The baud rate generator divides

the selected prescaler clock by N, which is set in BR0CK<BR0S3:0>. (N

=

1, 2, 3 ...

16)

When BR0CR<BR0ADDE>

=

1

The N

+

(16

−

K)/16 division function is enabled. The baud rate generator

divides the selected prescaler clock by N

+

(16 – K)/16 using the value of N set in

BR0CR<BR0S3:0> (N

=

2, 3 ... 15) and the value of K set in BR0ADD<BR0K3:0>

(K

=

1, 2, 3 ... 15)

Note: If N

=

1 or N

=

16, the N

+

(16

−

K)/16 division function is disabled. Clear

BR0CR<BR0ADDE> to 0.

•

In I/O interface mode

The N

+

(16

−

K)/16 division function is not available in I/O interface mode. Clear

BR0CR<BR0ADDE> to 0 before dividing by N.

The method for calculating the transfer rate when the baud rate generator is used is

explained below.

•

In UART mode

Baud rate

=

÷

16

•

In I/O interface mode

Baud

rate

=

÷

2

Input clock of baud rate generator

Frequency divider for baud rate generator

Input clock of baud rate generator

Frequency divider for baud rate generator

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Summary of Contents for TLCS-900 Family

Page 1: ...CS 900 H1 series TMP92CZ26AXBG Rev0 2 09 Dec 2005 TENTATIVE It s first version technical data sheet Since this revision 0 2 is still under working there may be some mistakes in it When you will start to design please order the latest one ...

Page 2: ...1 3 7 4 Port 6 92CZ26A 123 3 7 5 Port 7 92CZ26A 125 3 7 6 Port 8 92CZ26A 128 3 7 7 Port 9 92CZ26A 130 3 7 8 Port A 92CZ26A 133 3 7 9 Port C 92CZ26A 135 3 7 10 Port F 92CZ26A 139 3 7 11 Port G 92CZ26A 143 3 7 12 Port J 92CZ26A 145 3 7 13 Port K 92CZ26A 148 3 7 14 Port L 92CZ26A 150 3 7 15 Port M 92CZ26A 152 3 7 16 Port N 92CZ26A 155 3 7 17 Port P 92CZ26A 157 3 7 18 Port R 92CZ26A 161 3 7 19 Port T ...

Page 3: ...C 92CZ26A 508 3 20 Touch screen interface TSI 92CZ26A 564 3 21 Real time clock RTC 92CZ26A 574 3 22 Melody Alarm generator 92CZ26A 589 3 23 Analog Digital Converter 92CZ26A 595 3 24 Watch dog timer 92CZ26A 615 3 25 Power Management Circuit PMC 92CZ26A 619 3 26 Multiply and Accumulate Calculation unit MAC 92CZ26A 628 3 27 Debug mode 92CZ26A 633 4 Electrical Characteristics 92CZ26A 640 5 Table of Sp...

Page 4: ... 1 CPU 32 bit CPU High speed 900 H1 CPU Compatible with TLCS 900 L1 instruction code 16Mbytes of linear address space General purpose register and register banks Micro DMA 8channels 62 5ns 4 bytes at fSYS 80MHz best case 2 Minimum instruction execution time 12 5ns at fSYS 80MHz 3 Internal RAM 288K byte can be used for program data and display memory Internal ROM 8 K byte memory for Boot only It en...

Page 5: ...ntrol 64 bytes 1 FIFO Endpoint 1 BULK output 64 bytes 2 FIFO Endpoint 2 BULK input 64 bytes 2 FIFO Endpoint 3 Interrupt input 8 bytes 1 FIFO Descriptor RAM 384 bytes 11 I2S Inter IC Sound interface 2 channel I2S bus mode selectable Master transmission only Data Format is supported Left Right Justify Built in FIFO buffer of 128 bytes 64 bytes 2 every each channels 12 LCD controller Supported up to ...

Page 6: ... 9 external interrupts Seven selectable priority levels 8 interrupt selectable negative positive of edge 22 DMAC function 6 channels High speed data transfer enable by controlling which convert micro DMA function and this function 23 Input Output ports 136 pins Except Data bus 16bit Address bus 24bit and RD pin 24 Nand_Flash interface 2 channel Available to connect directly with NAND flash Support...

Page 7: ...29 Clock controller Built in two blocks of clock doubler PLL PLL supplies 48 MHz for USB and 80 MHz for CPU from 10MHz Clock gear function Selectable high frequency clock fc to fc 16 Clock for Timer fs 32 768 kHz 30 Operating voltage Internal VCC 1 5V External I O Vcc 3 0 to 3 6 V 2 power supplies Internal power supply 1 4 to 1 6 External power supply 3 0 to 3 6 31 Package 228 pin FBGA P FBGA228 1...

Page 8: ...WAIT RTC MELODY ALARM OUT KEY BOARD I F PA0 to PA7 KI0 to KI7 PN0 to PN7 KO0 to KO7 PC7 KO8 PM2 ALARM MLDALM I 2 S I2 S0 PLL NAND FLASH I F 2ch I2S0DO PF1 I2S0CKO PF0 PC4 EA26 PC5 EA27 PC6 EA28 SBI I 2 Cbus I2S0WS PF2 SPI Controller SPDO PR1 SPDI PR0 SPCLK PR3 SPCS PR2 AN4 to AN5 PG4 to PG5 I 2 S I2 S1 I2S1DO PF4 I2S1CKO PF3 I2S1WS PF5 TA0IN INT1 PC1 TA2IN INT3 PC3 8BIT TIMER TMRA4 8BIT TIMER TMRA...

Page 9: ... L1 L2 L3 L4 L6 L12 L14 L15 L16 L17 M1 M2 M3 M4 M6 M7 M8 M9 M10 M11 M12 M14 M15 M16 M17 N1 N2 N3 N4 N14 N15 N16 N17 P1 P2 P3 P5 P6 P7 P8 P9 P10 P11 P12 P13 P15 P16 P17 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 U1 U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 U12 U13 U14 U15 U16 U17 Figure 2 1 1 Pin assignment diagram P FBGA228 4 balls o...

Page 10: ...SRWR F14 PU5 LD21 M4 P90 TXD0 T7 PL4 LD4 B11 PJ0 SDRAS SRLLB F15 PU2 LD18 M6 DVCC3A3 T8 PL5 LD5 B12 P86 CSZD CE 0 ND F16 P55 A13 M7 DVSS4 T9 PR1 SPDO B13 P82 2 CS CSZA SDCS F17 P54 A12 M8 DVCC3A4 T10 PL6 LD6 B14 P75 R W NDR B G1 DVCC3B1 M9 DVSS5 T11 PK1 LLOAD B15 P71 WRLL NDRE G2 PW7 M10 DVCC3A5 T12 P00 D0 B16 P64 A20 G3 PV0 SCLK0 M11 DVSS6 T13 P02 D2 B17 DVCC1A4 G4 PV1 M12 DVCC3A6 T14 P04 D4 C1 A...

Page 11: ... 1 I O Output Port 74 I O port Expanded address 25 P75 R W NDR B 1 I O Output Input Port 75 I O port Read Write High represents read or dummy cycle and Low write cycle NAND Flash Ready 1 Busy 0 input P76 WAIT 1 I O Input Port 76 I O port Wait Signal used to request CPU bus wait P80 0 CS 1 Output Output Port 80 Output port Chip select 0 Outputs Low when address is within specified address area P81 ...

Page 12: ...d to X pin for Touch Screen I F P97 PY 1 Input Output Port 97 Input port schmitt input Y Plus Pin connected to Y pin for Touch Screen I F PA0 to PA7 KI0 to KI7 8 Input Input Port A0 to A7 Input port Key input 0 to 7 For key on wake up 0 to 7 Schmitt input with pull up resistor PC0 INT0 1 I O Input Port C0 I O port Schmitt input Interrupt request pin 0 Interrupt request pin with programmable rising...

Page 13: ...input pin 3 Input pin of A D converter Y Minus Pin connected to Y pin for Touch Screen I F A D Trigger Request signal of A D start PG4 to PG5 AN4 to AN5 2 Input Input Port G4 to G5 Input port Analog input pin 4 to 5 Input pin of A D converter PJ0 SDRAS SRLLB 1 Output Output Output Port J0 Output port Outputs strobe signal of SDRAM row address Data enable signal for D0 to D7 of SRAM PJ1 SDCAS SRLUB...

Page 14: ... of external power supply In stand by mode outputs L level In other than stand by mode outputs H level PN0 to PN7 KO0 to KO7 8 I O Output Port N I O port Key output 0 to 7 Key scan strobe pin programmable open drain output PP1 TA3OUT 1 I O Output Port P1 I O port Timer A3 output Output pin of 8 bit timer 3 PP2 TA5OUT 1 I O Output Port P2 I O port Timer A5 output Output pin of 8 bit timer 5 PP3 INT...

Page 15: ...ve data in I 2 C mode PV7 SCL 1 I O I O Port V7 I O port Input output clock in I 2 C mode PW0 to PW7 8 I O Port W0 to W7 I O port PX4 CLKOUT LDIV 1 Output Output Output Port X4 Output port Internal clock output pin Output pin for LCD driver PX5 X1USB 1 I O Input Port X5 I O port Clock input pin of USB PX7 1 I O Port X7 I O port PZ0 EI_PODDATA 1 I O Input Port Z0 I O port Schmitt input Debug mode i...

Page 16: ...converter H VREFL 1 Input Pin for reference voltage input to A D converter L AVCC 1 Power supply pin for A D converter AVSS 1 GND pin for AD converter 0V DVCC3A 12 Power supply pin for peripheral I O A Connect all DVCC3A pins to power supply pin DVCC3B 1 Power supply pin for peripheral I O B Connect all DVCC3B pins to power supply pin DVCC1A 5 Power supply pin for internal logic A Connect all DVCC...

Page 17: ...MHz Internal RAM 32 bit 2 1 1 1 clock access Internal Boot ROM 32 bit 2 clock access 8 bit 2 clock access INTC SDRAMC MEMC LCDC TSI PORT PMC 16 bit 2 clock access MMU USB NDFC SPIC DMAC 32 bit 2 clock access I2S MAC 32 bit 1 clock access MAC Internal I O 8 bit 5 to 6 clock access TMRA TMRB SIO RTC MLD ALM SBI CGEAR ADC WDT External memory SRAM MASKROM etc 8 16 bit 2 clock access can insert some wa...

Page 18: ...ctions according to the Program Counter settings Sets the Program Counter PC as follows in accordance with the Reset Vector stored at address FFFF00H FFFF02H PC 7 0 data in location FFFF00H PC 15 8 data in location FFFF01H PC 23 16 data in location FFFF02H When the Reset is accepted the CPU sets internal I O ports and other pins as follows Initializes the internal I O registers as table of Special...

Page 19: ... Reset timing chart R e a d W r i t e f sys A23 0 DATA IN D0 15 D0 15 Sampling After reset is released it is started from 1 wait read cycle High Z Sampling RESET RD WRxx SRWR 0FFFF00H DATA IN DATA OUT CS0 1 3 CS2 SRxxB SRxxB f SYS 15 5 16 5 Clock ...

Page 20: ...ct machinery connected with micro controller Note2 When setting to ON don t set 3 3V power supply earlier than 1 5V power supply When setting to OFF don t set to 3 3V power supply later than 1 5 V power supply Figure 3 1 2 Power on Reset Timing Example DVCC1A DVCC1B DVCC1C RESET AVCC DVCC3B DVCC3A Power supply is rising with in 100mS and stabilizes After 1 5V power supply is falling set 3 3V to OF...

Page 21: ...to system usage Table 3 1 2 Operation Mode Setup Table Mode Setup input pin RESET AM1 AM0 DBGE Operation Mode 0 Debug mode 0 1 1 16 bit external bus starting 0 1 0 1 Test mode Prohibit to set 0 Test mode Prohibit to set 1 1 1 BOOT 32 bit internal MROM starting BOOT mode 0 0 0 1 Test mode Prohibit to set ...

Page 22: ...g mode Note2 Don t use the last 16 byte area FFFFF0H to FFFFFFH This area is reserved as internal area 000000H 002000H 16Mbyte area R R R R R8 16 R d8 16 nnn Direct area n 64Kbyte area nn Internal I O 8 Kbyte Internal RAM 288 Kbyte 04A000H 010000H Internal area FFFF00H FFFFFFH Vector table 256 Byte External memory 000100H External memory F00000H F10000H Provisional Emulator Control Area 64kbyte No...

Page 23: ...ubler PLL 3 standby controller and 4 noise reducing circuit They are used for low power low noise systems This chapter is organized as follows 3 3 1 Block diagram of system clock 3 3 2 SFRs 3 3 3 System clock controller 3 3 4 Prescaler clock controller 3 3 5 Noise reducing circuit 3 3 7 Standby controller ...

Page 24: ...t instruction interrupt STOP mode Stops all circuits Instruction Note Note 1 If you shift from PLL ON mode to PLL OFF mode execute following setting in the same order 1 Change CPU clock Set 0 to PLLCR0 FCSEL 2 Stop PLL circuit Set 0 to PLLCR1 PLLON Note 2 It s prohibited to shift from PLL ON mode to STOP mode directly You should set PLL OFF mode once and then shift to STOP mode Figure 3 3 1 System...

Page 25: ...GEAR2 0 2 fSYS 2 φT0TMR fs φT0 High frequency Oscillator circuit 8 2 fIO Lock up timer PLL PLLCR1 PLLON PLLCR0 LUPFG 8 Clock Doubler1 PLL1 24 fUSB SYSCR0 USBCLK1 0 5 fPLLUSB X1USB TMRA0 7 TMRB0 1 fSYS CPU RAM Interrupt Controller I O ports Prescaler φT0TMR SIO0 RTC fs Prescaler MLD ALM SDRAMC fio LCDC Memory Controller NAND Flash Controller I 2 S TSI SPIC SBI Prescaler DMAC MAC fUSB USB ADC 2 fPLL...

Page 26: ... external oscillator range of input frequency is 6 to10MHz Don t input the clock over 10MHz Table 3 3 1 Setting example for fOSCH High frequency fOSCH System clock fSYS System clock fSYS USB clock fUSB a PLL USB PLL0 ON PLL1ON 10 0 MHz Max 80 MHz Max 60 MHz 48 MHz b PLL No USB PLL0 ON PLL1OFF Max 10 0 MHz Max 80 MHz Max 60 MHz c No PLL No USB PLL0 OFF PLL1OFF Max 10 0 MHz Max 10 MHz Max 10 MHz Not...

Page 27: ...ved 110 Reserved 111 Reserved 7 6 5 4 3 2 1 0 bit Symbol CKOSEL WUPTM1 WUPTM0 HALTM1 HALTM0 Read write R W R W R W R W R W R W After Reset 0 0 1 0 1 1 Function Always write 0 Select CLKOUT 0 fSYS 1 fS Warm Up Timer 00 reserved 01 28 inputted frequency 10 214 inputted frequency 11 216 inputted frequency HALT mode 00 Reserved 01 STOP mode 10 IDLE1 mode 11 IDLE2 mode Note1 SYSCR0 bit7 bit3 bit1 SYSCR...

Page 28: ...L 0 WEAK Bit symbol Read Write After reset Function Bit symbol Read Write After reset Function Switching the protect ON OFF by write to following 1 st KEY 2 nd KEY 1 st KEY EMCCR1 5AH EMCCR2 A5H in succession write 2 nd KEY EMCCR1 A5H EMCCR2 5AH in succession write Note In case restarting the oscillator in the stop oscillation state e g Restart the oscillator in STOP mode set EMCCR0 DRVOSCH DRVOSC...

Page 29: ...tput Input buffer drive register for standby mode Purpose and method of using This register is used to set each pin status at stand by mode All ports have this format s register x means port name For each register refer to 3 5 Function of Ports Before HALT instruction is executed set each register pin status They will be effective after CPU executes HALT instruction This register is effective in a...

Page 30: ...ect Register SYSCR1 GEAR2 0 to either fc fc 2 fc 4 fc 8 or fc 16 Using the clock gear to select a lower value of fSYS reduces power consumption Example Changing clock gear SYSCR1 EQU 10E1H LD SYSCR1 XXXXX001B Changes system clock fSYS to fc 2 LD DUMMY 00H Dummy instruction X don t care High speed clock gear changing To change the clock gear write the register value to the SYSCR1 GEAR2 to 0 registe...

Page 31: ...z measured by 13 stage binary counter Note1 Input frequency limitation for PLL The limitation of input frequency High frequency oscillation for PLL is following fOSCH X to X MHz Vcc 1 4 to 1 6V Note2 PLLCR0 LUPFG The logic of PLLCR0 LUPFG is different from 900 L1 s DFM Be careful to judge an end of lock up time Note3 PLLCR1 PLL0 PLLCR1 PLL1 It s prohibited to turn ON both PLL0 and PLL1 simultaneou...

Page 32: ...10 MHz to 60 MHz X Don t care Counts up by fOSCH During lock up PLL0 PLL output fPLL Lockup timer LUPFG System clock fSYS Starts PLL0 operation and Starts lock up Ends of lock up Changes from 10MHz to 60MHz After lock up FCSEL Example 2 PLL0 stopping PLLCR0 EQU 10E8H PLLCR1 EQU 10E9H LD PLLCR0 X0XXXXXXB Changes fc from 60 MHz to10 MHz LD PLLCR1 0XXXXXXXB Stop PLL X Don t care PLL0 PLL0 output fPLL...

Page 33: ...p lock up start LUP BIT 5 PLLCR0 JR Z LUP Check for the flag of lock up end LD PLLCR0 X1XXXXXXB Change the system clock fOSCH to fPLL X Don t care 2 Change Stop Control OK PLL0 use mode fPLL High frequency oscillator operation mode fOSCH PLL0 Stop LD PLLCR0 X0XXXXXXB Change the system clock fPLL to fOSCH LD PLLCR1 0XXXXXXXB Stop PLL0 X Don t care OK PLL0 use mode fPLL Set the STOP mode High freque...

Page 34: ...et in EMCCR0 to EMCCR2 registers 1 Reduced drivability for high frequency oscillator circuit Purpose Reduces noise and power for oscillator when a resonator is used Clock diagram resonator C2 C1 Enable oscillation X1 pin EMCCR0 DRVOSCH fOSCH X2 pin Setting method The drivability of the oscillator is reduced by writing 0 to EMCCR0 DRVOSCH register By reset DRVOSCH is initialized to 1 and the oscill...

Page 35: ...CL register By Reset DRVOSCL is initialized to 1 3 Single drive for high frequency oscillator circuit Purpose Not need twin drive and protect mistake operation by inputted noise to X2 pin when the external oscillator is used Block diagram X1 pin X2 pin Enable oscillation EMCCR0 DRVOSCH fOSCH Setting method The oscillator is disabled and starts operation as buffer by writing 1 to EMCCR0 EXTIN regis...

Page 36: ... MEMCR0 CSTMGCR WRTMGCR RDTMGCR0 RDTMGCR1 BROMCR 2 MMU LOCALPX PY PZ LOCALLX LY LZ LOCALRX RY RZ LOCALWX WY WZ LOCALESX ESY ESZ LOCALEDX EDY EDZ LOCALOSX OSY OSZ LOCALODX ODY ODZ 3 Clock gear SYSCR0 SYSCR1 SYSCR2 EMCCR0 4 PLL PLLCR0 PLLCR1 5 PMC PMCCTL Operation explanation Execute and release of protection write operation to specified SFR becomes possible by setting up a double key to EMCCR1 and ...

Page 37: ...DLE2 IDLE1 or STOP This register is effective when using PMC function For details refer to PMC section The truth table to control Output Input buffer is below OE PxnD Output buffer Input buffer 0 0 OFF OFF 0 1 OFF ON 1 0 OFF OFF 1 1 ON OFF Note1 OE means an output enable signal before stand by mode Basically PxCR is used as OE Note2 n in PxnD means bit number of PORTx The subsequent actions perfor...

Page 38: ...tatus executing an instruction that follows the HALT instruction When the interrupt request level set before executing the HALT instruction is less than the value of the interrupt mask register releasing the halt mode is not executed in non maskable interrupts interrupt processing is processed after releasing the halt mode regardless of the value of the mask register However only for INT0 to INT5 ...

Page 39: ...used to release the halt mode The priority level interrupt request level of non maskable interrupts is fixed to 7 the highest priority level There is not this combination type 1 Releasing the halt mode is executed after passing the warmming up time 2 6 interrupts of all 24 INTUSB sources can release Halt state from IDLE1 mode Therefore the system of low power dissipation can be built However the w...

Page 40: ... Mode Address 8200H LD PCFC 02H Sets PC1 to INT0 interrupt 8203H LD IIMC0 00H Select INT0 interrupt rising edge 8206H LD INTE0 06H Sets INT0 interrupt level to 6 8209H EI 5 Sets CPU interrupt level to 5 820BH LD SYSCR2 28H Sets Halt mode to IDLE1 mode 820EH HALT Halts CPU INT0 INT0 interrupt routine RETI 820FH LD XX XX ...

Page 41: ... In IDLE1 Mode only the internal oscillator and the RTC and MLD continue to operate The system clock stops In the Halt state the interrupt request is sampled asynchronously with the system clock however clearance of the Halt state i e restart of operation is synchronous with it Figure 3 3 9 illustrates the timing for clearance of the IDLE1 Mode Halt state by an interrupt Figure 3 3 9 Timing chart ...

Page 42: ... to allow oscillation to stabilize Figure 3 3 10 illustrates the timing for clearance of the STOP Mode Halt state by an interrupt Figure 3 3 10 Timing chart for STOP Mode Halt state cleared by interrupt Table 3 3 5 Example of warming up time after releasing STOP mode fOSCH 10 MHz SYSCR2 WUPTM1 0 01 28 10 214 11 216 25 6 us 1 6384 ms 6 5536 ms Interrupt for releasing Halt Data Data STOP mode Warm u...

Page 43: ...OFF P97 PA0 PA7 1 KI0 7 PC0 INT0 PC1 INT1 TA0IN PC2 INT2 PC3 INT3 TA2IN ON ON OFF PC4 PC7 PF0 PF5 ON ON ON PG0 PG2 PG4 PG5 2 PG3 2 ADTRG OFF ON ON upon port read ON OFF ON PJ5 PJ6 PN0 PN7 PP1 PP2 PP3 INT5 PP4 INT6 TB0IN0 PP5 INT7 TB1IN0 PR0 SPDI ON ON OFF PR1 PR3 PT0 PT7 PU0 PU4 PU6 PU7 PU5 PV0 PV2 PV6 PV7 SDA SCL PW0 PW7 PX5 X1USB PX7 OFF PZ0 PZ5 EI_PODDATA EI_SYNCLK EI_PODREQ EI_REFCLK EI_TRGIN ...

Page 44: ...6 A23 16bit Start ON Boot Start OFF P70 RD ON P71 WRLL NDRE P72 WRLU NDWE P73 EA24 P74 EA25 P75 R W ON ON OFF P76 OFF P80 0 CS P81 1 CS SDCS P82 2 CS CSZA SDCS P83 3 CS CSXA P84 CSZB P85 CSZC P86 CSZD CE 0 ND P87 CSXB CE 1 ND ON P90 TXD0 ON ON OFF P91 P92 SCLK0 OFF ON ON OFF P96 PX P97 PY ON ON OFF PC0 PC3 PC4 EA26 PC5 EA27 PC6 EA28 PC7 KO8 PF0 I2S0CKO PF1 I2S0DO PF2 I2S0WS PF3 I2S1CKO PF4 I2S1DO ...

Page 45: ...T ON ON OFF PP4 PP5 OFF PP6 TB0OUT0 PP7 TB1OUT0 ON ON ON OFF PR0 PR1 SPDO PR2 SPCS PR3 SPCLK PT0 PT7 LD8 LD15 PU0 PU6 LD16 LD22 LD23 OFF PU7 EO_TRGOUT ON PV0 SCLK0 ON ON OFF PV1 PV2 OFF PV3 PV4 ON PV6 SDA PV7 SCL ON ON OFF PW0 PW7 OFF PX4 CLKOUT LDIV ON ON ON OFF PX5 PX7 PZ0 PZ5 PZ6 PZ7 EO_MCUDATA EO_MCUREQ OFF ON ON ON ON ON OFF D D OFF ON OF depend on USBC operation X2 IDLE2 1 ON STOP output H X...

Page 46: ...instructions from internal boot ROM and executes them The boot ROM loads a user program into internal RAM from USB or via UART and then branches to the internal RAM In this way the user program starts boot operation Table 3 4 2 shows an outline of boot operation Table 3 4 1 Operation Modes Mode Setting Pins RESET AM1 AM0 Operation Mode 0 1 MULTI Start from external 16 bit bus memory 1 0 TEST Setti...

Page 47: ...when multi mode Figure 3 4 1 Memory Map of BOOT Mode 2 Switching the boot ROM area to an external area After the boot sequence is executed in BOOT mode an application system program may start running without a reset being asserted In this case it is possible to switch the boot ROM area to an external area Internal I O A Reset Interrupt Note Vector Area 256 bytes 000000H 001FF0H 400000H FFFF00H Int...

Page 48: ...on to all the downloading methods Note 1 To download a user program via USB a USB device driver and special application software are needed on the PC Note 2 To download a user program via UART special application software is needed on the PC Note 3 The a b in the above flowchart indicate points where the settings of external port pins are changed For details see Table 3 4 3 Figure 3 4 2 Flowchart ...

Page 49: ...A 92CZ26A 46 Figure 3 4 3 How the Boot Program Uses Internal RAM Work Area for Boot Program 4 Kbytes Download Area for User Program 282 Kbytes Stack Area for Boot Program 2 Kbytes 002000H 049800H 003000H 049FFFH ...

Page 50: ...n the table below other ports are left as they are after reset or at startup of the boot program Table 3 4 3 Port Settings by the Boot Program Description Port Name Function Name I O a b c P90 TXD0 Output No change from after reset state input port Set as TXD0 output pin UART P91 RXD0 Input Set as RXD0 input pin No change from a No change from b D I O D I O No change USB PU6 PUCTL Output No change...

Page 51: ...o prevent flow through current on the D D pins Connect to the USB connector by adding a dumping resistor 27Ω recommended When USB is not accessed the pin level should be fixed with a resistor to prevent flow through current USB PU6 PUCTL Output This pin is used to control ON OFF of the D pin s pull up resistor Add a switch externally so that the pull up is turned on when 1 Reset sets this pin as a...

Page 52: ...gs by Boot Program Register Name Set Value Description WDMOD 00H Watchdog timer not active WDCR B1H Watchdog timer disabled SYSCR0 70H High frequency and low frequency oscillators operating SYSCR1 00H Clock gear 1 1 SYSCR2 2CH Initial value PLLCR0 00H PLL clock not used PLLCR1 00H or 60H Normally PLL is disabled However only in the case of booting via USB PLL is activated for USB INTEUSB 04H USB i...

Page 53: ...ifications SIO channel 0 is used for downloading a user program The UART communication format in BOOT mode is shown below Before booting the PC must also be set up with the same conditions Although the default baud rate is 9600 bps this can be changed as shown in Table 3 4 8 Serial transfer mode UART asynchronous mode full duplex Data length 8 bits Parity bit None STOP bit 1 bit Handshake None Bau...

Page 54: ... byte Matching data 5AH Frequency measurement and baud rate auto setting OK Echo back data 5AH Error No transfer 3rd byte to 6th byte Version management information See Table 3 4 10 7th byte Frequency information 8th byte 9th byte Baud rate modification command See Table 3 4 8 9600 bps OK Echo back data Error Error code x 3 10th byte to n 4 th byte User program Intel Hex format binary NG Operation...

Page 55: ...When UART is used to download a user program the maximum allowed program size is 282 Kbytes 3000H 49800H The extended Intel Hex format is supported a Operation procedure 1 Connect the serial cable This must be done before the microcontroller is reset 2 Set the AM1 and AM0 pins to 1 and reset the microcontroller 3 The receive data in the 1st byte is matching data 5AH Upon starting in BOOT mode the ...

Page 56: ...The boot program executes the SUM calculation routine upon detecting the end record Thus after sending the end record the PC should be placed in a state in which it waits for SUM data 10 The n 3 th and n 2 th bytes are used to send the SUM value to the PC in the order of upper byte and lower byte For details on how to calculate SUM see SUM calculation to be described later SUM calculation is perfo...

Page 57: ...ter sending an error code the boot program stops operation c SUM calculation 1 Calculation method SUM is calculated by adding data in bytes and is returned in words as explained below Example A1H B2H C3H D4H If the data to be calculated consists of the 4 bytes shown to the left SUM is calculated as follows A1H B2H C3H D4H 02EAH SUM HIGH 02H SUM LOW EAH 2 Data to be calculated SUM is calculated fro...

Page 58: ...are allocated as the user program download area 6 A user program in Intel Hex format ASCII codes must be converted into binary data in advance as explained in the example below Example How to convert an Intel Hex file into binary format The following shows how an Intel Hex format file is displayed on a text editor 103000000607F100030000F201030000B1F16010B7 00000001FF However the actual data consis...

Page 59: ...on frequency If an error is within plus or minus 3 the boot program decides on that frequency Each baud rate includes a setting error as shown in Table 3 4 13 For example in the case of 10 00 MHz 9600 bps the baud rate is actually set at 9615 38 bps To establish communication the sum of the baud rate setting error and the measured frequency error must be within plus or minus 3 Table 3 4 13 Baud Ra...

Page 60: ...he TMP92CZ26A the boot program does not use it for transfer control b RS 232C connector The RS 232C connector must not be connected or disconnected while the boot program is running c Software on the PC When downloading a user program via UART special application software is needed on the PC ...

Page 61: ...lthough the level setting is not specified in the above diagram be sure to fix the level of the D and D pins by referring to the chapter on USB Figure 3 4 5 USB Connection Example 2 USB interface specifications When a user program is downloaded via USB the oscillation frequency should be set to 10 00 MHz The transfer speed should be fixed to full speed 12 Mbps The boot program uses the following t...

Page 62: ...end a user program Convert Intel Hex format data into binary data Check data Send data Transfer End Processing Transmit the transfer result command 2 seconds after completion of user program transfer Check data Send the transfer result command Send transfer result data TMP92CZ26A Prepare microcontroller information data Prepare microcontroller information data Load the received data into the speci...

Page 63: ... bulk OUT transfer after the setup stage is completed User program transfer result command 04H Send the transfer result Transfer result data is sent by bulk IN transfer after the setup stage is completed Table 3 4 16 Setup Command Data Structure Field Name Value Meaning bmRequestType 40H D7 0 Host to Device D6 D5 2 Vendor D4 D0 0 Device bRequest 00H 02H 04H 00H Microcontroller information 02H User...

Page 64: ... Ignored Table 3 4 18 Information Returned by GET_DISCRIPTOR DeviceDescriptor Field Name Value Meaning Blength 12H 18 bytes BdescriptorType 01H Device descriptor BcdUSB 0110H USB Version 1 1 BdeviceClass 00H Device class Not in use BdeviceSubClass 00H Sub command Not in use BdeviceProtocol 00H Protocol Not in use BmaxPacketSize0 40H EP0 maximum packet size 64 bytes IdVendor 0930H Vendor ID IdProdu...

Page 65: ... 04H Interface descriptor bInterfaceNumber 00H Interface number 0 bAlternateSetting 00H Alternate setting number 0 bNumEndpoints 02H There are two endpoints bInterfaceClass FFH Specified device bInterfaceSubClass 00H bInterfaceProtocol 50H Bulk only protocol iIinterface 00H Index value of string descriptor indicating interface name Not in use EndpointDescriptor Field Name Value Meaning Endpoint1 b...

Page 66: ...l Hex format 04H The first data of a user program is not 3AH User program size error 06H The size of a received user program is larger than the value set in wIndex of the user program transfer start command Download address error 08H The specified user program download address is not in the designated area The user program size is over 10 Kbytes Protocol error or other error 0AH The user program t...

Page 67: ...receiving the microcontroller information command the boot program prepares microcontroller information in ASCII code 6 The PC prepares the user program to be loaded by converting an Intel Hex file into binary format 7 The PC sends the user program transfer start command by control transfer vendor request After the setup stage is completed the PC transfers the user program by bulk OUT transfer 8 A...

Page 68: ...e maximum allowed record length is 250 bytes Example Transfer data when writing 16 byte data in Intel Hex format from address 3000H The following shows how an Intel Hex format file is displayed on a text editor 103000000607F100030000F201030000B1F16010B7 00000001FF However the actual data consists of ASCII codes as shown below 3A3130333030303030303630374631303030333030303046323031303330303030 42314...

Page 69: ... USB connector The USB connector must not be connected or disconnected while the boot program is running b Software on the PC To download a user program via USB a USB device driver and special application software are needed on the PC ...

Page 70: ...ter than or equal to the value in the interrupt mask register the CPU accepts the interrupt However software interrupts and illegal instruction interrupts generated by the CPU and are processed irrespective of the value in IFF2 0 The value in the interrupt mask register IFF2 0 can be changed using the EI instruction EI num sets IFF2 0 to num For example the command EI3 enables the acceptance of al...

Page 71: ...d interrupt 1 INTNEST INTNEST 1 PC FFFF00H V Interrupt processing program RETI instruction POP SR POP PC INTNEST INTNEST 1 End Clear interrupt request flag YES NO Data transfer by micro DMA COUNT COUNT 1 COUNT 0 NO Clear vector register generating micro DMA transfer end interrupt INTTC0 YES Micro DMA processing General purpose interrupt processing DMA soft start request Start specified by HDMA YES...

Page 72: ...d decrements the interrupt nesting counter INTNEST by 1 Non maskable interrupts cannot be disabled by a user program Maskable interrupts however can be enabled or disabled by a user program A program can set the priority level for each interrupt source A priority level setting of 0 or 7 will disable an interrupt request If an interrupt request is received for an interrupt with a priority level equ...

Page 73: ...F4CH 13H 21 INTP0 Protect 0 Write to SFR 0050H FFFF50H 14H 22 Reserved 0054H FFFF54H 15H 23 INTTA0 0 0058H FFFF58H 16H 24 INTTA1 8 bit timer 1 005CH FFFF5CH 17H 25 INTTA2 8 bit timer 2 0060H FFFF60H 18H 26 INTTA3 8 bit timer 3 0064H FFFF64H 19H 27 INTTB0 16 bit timer 0 0068H FFFF68H 1AH 28 INTTB1 16 bit timer 0 006CH FFFF6CH 1BH 29 INTKEY Key wakeup 0070H FFFF70H 1CH 30 INTRTC RTC Alarm interrupt ...

Page 74: ...MA1 HDMA1 end 00D4H FFFFD4H 35H 55 INTTC2 INTDMA2 Micro DMA2 HDMA2 end 00D8H FFFFD8H 36H 56 INTTC3 INTDMA3 Micro DMA3 HDMA3 end 00DCH FFFFDCH 37H 57 INTTC4 INTDMA4 Micro DMA4 HDMA4 end 00E0H FFFFE0H 38H 58 INTTC5 INTDMA5 Micro DMA5 HDMA5 end 00E4H FFFFE4H 39H 59 INTTC6 Micro DMA6 end 00E8H FFFFE8H 3AH 60 INTTC7 Micro DMA7 end 00ECH FFFFECH 3BH to Maskable Reserved 00F0H 00FCH FFFFF0H FFFFFCH to No...

Page 75: ...at once When micro DMA is accepted the interrupt request flip flop assigned to that channel is cleared Data in 1byte or 2byte or4byte blocks is automatically transferred at once from the transfer source address to the transfer destination address set in the control register and the transfer counter is decremented by 1 If the value of the counter after it has been decremented is not 0 DMA processin...

Page 76: ...fer of data from memory to memory from I O to memory from memory to I O and from I O to I O For details of the various transfer modes see section 3 5 2 4 Detailed description of the transfer mode register Since a transfer counter is a 16 bit counter up to 65536 micro DMA processing operations can be performed per interrupt source Provided that the transfer counter for the source is initially set t...

Page 77: ...transfer counter is 0 Note1 If it is started by software don t set any channels to start in same time Note2 If be started sequentially restart it after confirming micro DMA of all channels is completed all micro DMA are set to 0 Symbol NAME Address 7 6 5 4 3 2 1 0 DREQ7 DREQ6 DREQ5 DREQ4 DREQ3 DREQ2 DREQ1 DREQ0 R W 0 0 0 0 0 0 0 0 DMAR DMA Request 109H Prohibit RMW 1 Start DMA 3 Transfer control r...

Page 78: ...nd destination DEC mode DMADn DMASn DMACn DMACn 1 If DMACn 0 then INTTCn 6 states 1 1 0 z z Destination and fixed mode DMADn DMASn DMACn DMACn 1 If DMACn 0 then INTTCn 5 states 1 1 1 00 Counter mode DMASn DMASn 1 DMACn DMACn 1 If DMACn 0 then INTTCn 5 states ZZ 00 1 byte transfer 01 2 byte transfer 10 4 byte transfer 11 Reserved Note 1 n stands for the micro DMA channel number 0 to 7 DMADn DMASn P...

Page 79: ...rity or in other words the interrupt with the lowest vector value is used to determine which interrupt request is accepted first The 3rd and 7th bits of the interrupt priority setting register indicate the state of the interrupt request flag and thus whether an interrupt request for a given channel has occurred If several interrupts are generated simultaneously the interrupt controller sends the i...

Page 80: ...H D Q CLR Y1 Y2 Y3 Y4 Y5 Y6 A B C Dn Dn 1 Dn 2 Interrupt request F F Interrupt vector read Micro DMA acknowledge Interrupt request F F Dn 3 A B C Interrupt vector read D2 D3 D4 D5 D6 D7 Selector S Q R 0 1 2 7 A B C D0 D1 Interrupt vector read Interrupt mask F F Micro DMA request HALT release INTRQ2 0 IFF 2 0 then 1 INTRQ2 to 0 IFF2 to 0 Interrupt mask detect RESET EI 1 to 7 DI Interrupt request si...

Page 81: ...R W R R W INTETA01 INTTA0 INTTA1 enable D4H 0 0 0 0 0 0 0 0 INTTA3 TMRA3 INTTA2 TMRA2 ITA3C ITA3M2 ITA3M1 ITA3M0 ITA2C ITA2M2 ITA2M1 ITA2M0 R R W R R W INTETA23 INTTA2 INTTA3 enable D5H 0 0 0 0 0 0 0 0 INTTA5 TMRA5 INTTA4 TMRA4 ITA5C ITA5M2 ITA5M1 ITA5M0 ITA4C ITA4M2 ITA4M1 ITA4M0 R R W R R W INTETA45 INTTA4 INTTA5 enable D6H 0 0 0 0 0 0 0 0 INTTA7 TMRA7 INTTA6 TMRA6 ITA7C ITA7M2 ITA7M1 ITA7M0 ITA...

Page 82: ... INTSPIRX ISPITC ISPITM2 ISPITM1 ISPITM0 ISPIRC ISPIRM2 ISPIRM1 ISPIRM0 R R W R R W INTESPI INTSPI enable E1H 0 0 0 0 0 0 0 0 INTUSB IUSBC IUSBM2 IUSBM1 IUSBM0 R R W INTEUSB INTUSB enable E3H Always write 0 0 0 0 0 INTALM IALMC IALMM2 IALMM1 IALMM0 R R W INTEALM INTALM enable E5H Always write 0 0 0 0 0 INTRTC IRC IRM2 IRM1 IRM0 R R W INTERTC INTRTC enable E8H Always write 0 0 0 0 0 INTKEY IKC IKM2...

Page 83: ...ECH 0 0 0 0 0 0 0 0 INTP0 IP0C IP0M2 IP0M1 IP0M0 R R W R R W INTEP0 INTP0 enable EEH Always write 0 0 0 0 INTADHP INTAD IADHPC IADHPM2 IADHPM1 IADHPM0 IADC IADM2 IADM1 IADM0 R R W R W R W 0INTEAD INTAD INTADHP enable EFH 0 0 0 0 0 0 0 0 lxxM2 lxxM1 lxxM0 Function Write 0 0 0 Disables interrupt requests 0 0 1 Sets interrupt priority level to 1 0 1 0 Sets interrupt priority level to 2 0 1 1 Sets int...

Page 84: ...MA5C ITC5M2 IDMA5M2 ITC5M1 IDMA5M1 ITC5M0 IDMA5M0 ITC4C IDMA4C ITC4M2 IDMA4M2 ITC4M1 IDMA4M1 ITC4M0 IDMA4M0 R R W R R W INTETC45 INTEDMA45 INTTC4 INTDMA4 INTTC5 INTDMA5 enable F3H 0 0 0 0 0 0 0 0 INTTC7 DMA7 INTTC6 DMA6 ITC7C ITC7M2 ITC7M1 ITC7M0 ITC6C ITC6M2 ITC6M1 ITC6M0 R R W R R W INTETC67 INTTC6 INTTC7 enable F4H 0 0 0 0 0 0 0 0 INTWD ITCWD R R W R INTWDT INTWD enable F7H Always write 0 0 lxx...

Page 85: ... edge LD INTCLR 0AH Clears interrupt request flag NOP Wait EI execution NOP NOP EI Note 2 X Don t care No change Note 3 See electrical characteristics in section 4 for external interrupt input pulse width Note 4 In port setting if 16 bit timer input is selected and capture control is executed INT6 and INT7 don t depend on IIMC1 register setting INT6 and INT7 operate by setting TBnMOD TBnCPM1 0 Set...

Page 86: ...ro DMA transfer end interrupt always write 1 INTRX0 edge enable 0 Edge detect INTRX0 1 H level INTRX0 Symbol Name Address 7 6 5 4 3 2 1 0 IR0LE W W W 0 0 1 SIMC SIO interrupt mode control F5H Prohibit RMW Always write 0 Note Always write 0 0 INTRX0 edge mode 1 INTRX0 level mode ...

Page 87: ... or HDMA transfer counter B HDMACBn value reaches 0 the micro DMA HDMA transfer end interrupt corresponding to the channel is sent to the interrupt controller the micro DMA HDMA start vector register is cleared and the micro DMA HDMA start source for the channel is cleared Therefore in order for micro DMA HDMA processing to continue the micro DMA HDMA start vector register must be set again during...

Page 88: ...W 0 0 0 0 0 0 DMA5V DMA5 start vector 105H DMA5 start vector DMA6V5 DMA6V4 DMA6V3 DMA6V2 DMA6V1 DMA6V0 R W 0 0 0 0 0 0 DMA6V DMA6 start vector 106H DMA6 start vector DMA7V5 DMA7V4 DMA7V3 DMA7V2 DMA7V1 DMA7V0 R W 0 0 0 0 0 0 DMA7V DMA7 start vector 107H DMA7 start vector 6 Micro DMA HDMA select register This register selectable that is started either Micro DMA or HDMA processing Micro DMA HDMA star...

Page 89: ...e transfer counter register reaches 0 Setting any of the bits in the register DMAB which correspond to a micro DMA channel as shown below to 1 specifies that any micro DMA transfer on that channel will be a burst transfer Symbol Name Address 7 6 5 4 3 2 1 0 DBST7 DBST6 DBST5 DBST4 DBST3 DBST2 DBST1 DBST0 R W 0 0 0 0 0 0 0 0 DMAB DMA burst 108H 1 DMA request on Burst mode ...

Page 90: ...eral interrupt request passes through the S input of the flip flop and becomes the Q output If the interrupt input mode is changed from edge mode to level mode the interrupt request flag is cleared automatically If the CPU enters the interrupt response sequence as a result of INT0 going from 0 to 1 INT0 must then be held at 1 until the interrupt response sequence has been completed If INT0 is set ...

Page 91: ...d interrupt Two count registers are provided to execute multiple DMA transfers by one DMA request and to generate multiple DMA requests at a time The DMA end interrupt INTDMA0 to INTDMA5 is also provided so that a general purpose interrupt routine can be used to prepare for the next processing 6 Priorities among DMA channels the same as the micro DMA acceptance specifications of the INTC DMA reque...

Page 92: ...ro DMA transfer count setting 15 0 DMAMn Micro DMA mode setting 7 0 CPU HDMASn DMA source address setting 31 0 HDMADn DMA destination address setting HDMACAn DMA transfer count A setting 15 0 HDMAMn DMA mode setting 7 0 DMAC HDMACBn DMA transfer count B setting HDMAE DMA operation enable disable Micro DMA REQ Micro DMA Channel Micro DMA ACK INTTCn Bus REQ Bus ACK DMA REQ DMA Channel DMA ACK INTDMA...

Page 93: ...l DnSA7 DnSA6 DnSA5 DnSA4 DnSA3 DnSA2 DnSA1 DnSA0 Read Write R W After reset 0 0 0 0 0 0 0 0 Function Source address 7 0 for DMAn 15 14 13 12 11 10 9 8 bit Symbol DnSA15 DnSA14 DnSA13 DnSA12 DnSA11 DnSA10 DnSA9 DnSA8 Read Write R W After reset 0 0 0 0 0 0 0 0 Function Source address 15 8 for DMAn 23 22 21 20 19 18 17 16 bit Symbol DnSA23 DnSA22 DnSA21 DnSA20 DnSA19 DnSA18 DnSA17 DnSA16 Read Write ...

Page 94: ... R W After reset 0 0 0 0 0 0 0 0 Function Destination address 7 0 for DMAn 15 14 13 12 11 10 9 8 bit Symbol DnDA15 DnDA14 DnDA13 DnDA12 DnDA11 DnDA10 DnDA9 DnDA8 Read Write R W After reset 0 0 0 0 0 0 0 0 Function Destination address 15 8 for DMAn 23 22 21 20 19 18 17 16 bit Symbol DnDA23 DnDA22 DnDA21 DnDA20 DnDA19 DnDA18 DnDA17 DnDA16 Read Write R W After reset 0 0 0 0 0 0 0 0 Function Destinati...

Page 95: ... 5 4 3 2 1 0 bit Symbol DnCA7 DnCA6 DnCA5 DnCA4 DnCA3 DnCA2 DnCA1 DnCA0 Read Write R W After reset 0 0 0 0 0 0 0 0 Function Transfer count A 7 0 for DMAn 15 14 13 12 11 10 9 8 bit Symbol DnCA15 DnCA14 DnCA13 DnCA12 DnCA11 DnCA10 DnCA9 DnCA8 Read Write R W After reset 0 0 0 0 0 0 0 0 Function Transfer count A 15 8 for DMAn Transfer count A 15 8 Transfer count A 7 0 Channel 0 0909H HDMACA0 0908H Cha...

Page 96: ... Symbol DnCB7 DnCB6 DnCB5 DnCB4 DnCB3 DnCB2 DnCB1 DnCB0 Read Write R W After reset 0 0 0 0 0 0 0 0 Function Transfer count B 7 0 for DMAn 15 14 13 12 11 10 9 8 bit Symbol DnCB15 DnCB14 DnCB13 DnCB12 DnCB11 DnCB10 DnCB9 DnCB8 Read Write R W After reset 0 0 0 0 0 0 0 0 Function Transfer count B 15 8 for DMAn Transfer count B 15 8 Transfer count B 7 0 Channel 0 090BH HDMACB0 090AH Channel 1 091BH HDM...

Page 97: ...e DEC MEM I O 100 Source destination INC MEM MEM 101 Source destination DEC MEM MEM 110 Source destination fixed I O I O 111 Reserved Note 2 Transfer data size 00 1 byte 01 2 bytes 10 4 bytes 11 Reserved Transfer mode 7 0 Channel 0 HDMAM0 090CH Channel 1 HDMAM1 091CH Channel 2 HDMAM2 092CH Channel 3 HDMAM3 093CH Channel 4 HDMAM4 094CH Channel 5 HDMAM5 095CH Note 1 Read modify write instructions ca...

Page 98: ...bus occupancy by using this timer register When the DMAC occupies the bus for the duration of time set in this register it releases the bus even if the specified DMA operation has not been completed yet After waiting for 16 states the DMAC asserts a bus request again to execute the rest of the DMA operation The DMAC counts the bus occupancy time regardless of which channel is occupying the bus To ...

Page 99: ...ted Figure 3 6 9 Overall Flowchart Interrupt specified by DMA start vector Yes No Bus ACK No Yes HDMASn read HDMADn write Timer match No Yes HDMACAn 1 0 No Yes Bus REQ deassert Internal timer start HDMACBn 1 0 Yes No INTDMAn assert END Interrupt request F F clear bus REQ assert To general purpose interrupt or micro DMA processing flow Interrupt DMA request ...

Page 100: ...destination memory setting Either internal or external memory can be set as the source and destination memory or I O to be accessed by the DMAC Even when the MMU is used in external memory the addresses to be accessed by the DMAC should be specified using logical addresses The DMAC accesses the specified source and destination addresses according to the bus width and number of waits set in the mem...

Page 101: ...2 Kbytes have been transferred the INTDMA0 interrupt routine shall be activated to prepare for the next processing a Main routine No Instruction Comments 1 ldl hdmas0 2000H Source address 2000H 2 ldl hdmad0 i2sbuf Destination address i2sbuf 3 ldw hdmaca0 16 Counter A 16 4 ldw hdmacb0 512 Counter B 512 32768 64 5 ldb hdmam0 0AH Transfer mode source INC 4 bytes 6 set 0 hdmae Enable DMA channel 0 7 l...

Page 102: ...sion start is to set to 1 DMAR register However DMAR register can t be used to confirm flag of transmission end DMAR register reset to 0 when HDMA release bus occupation once with HDMATR function We recommend to use HDMACBn register counter value to confirm flag of transmission end ...

Page 103: ...o estimate the CPU stop time defined as tSTOP HDMA based on the transfer time transfer start interval and number of channels to be used CPU bus stop rate tSTOP HDMA s HDMA start interval s HDMA start interval s HDMA start interrupt period s Note The HDMA start interval depends on the period of the HDMA start interrupt source However it is also possible to start HDMA by software tSTOP HDMA s Source...

Page 104: ...4 byte units the transfer count is calculated as follows 5 Kbytes 4 bytes 1280 times Since I2S generates an interrupt for every 64 bytes the DMAC s counter A is set to 16 64 bytes 4 bytes 16 times and counter B is set to 80 Since an interrupt is generated 80 times the first read to internal RAM which requires 1 additional state occurs 80 times requiring additional 80 states in total In addition fr...

Page 105: ...ers data for one line is defined as tSTOP LDMA which is calculated as shown below for each display mode tSTOP LDMA SegNum K 8 tLRD 16 bit external SRAM tLRD 2 wait count fSYS Hz 2 Internal RAM tLRD 1 fSYS Hz 4 16 bit external SDRAM tLRD 1 fSYS Hz 2 SegNum Number of segments to be displayed K Number of bits needed for displaying 1 pixel Monochrome K 1 4 gray scales K 2 16 gray scales K 4 256 colors...

Page 106: ...S Hz 640 16 67 ns 4 16 67 ns 2 68 μs LHSYNC period s 1 70 Hz COM 20 260 54 95 μs CPU bus stop rate tSTOP LCD s LHSYNC period s 2 68 μs 54 95 μs 4 88 Conditions 2 CPU operation speed fSYS 10 MHz Display RAM 16 bit external SRAM 0 waits Display size QVGA 240seg 320com Display quality 4096 colors STN Refresh rate 100 Hz 0 dummy cycles Calculation example 2 tSTOP LDMA SegNum K 8 tLRD 240 12 8 2 wait c...

Page 107: ...eleases the bus The priorities among the three bus masters should be set in the order of LCDC SDRAMC CPU The time the CPU stops operation while the LCD controller and SDRAM controller are transferring data for one line is defined as tSTOP LDMA ARDMA which is calculated as follows tSTOP LDMA ARDMA tSTOP LDMA s tSTOP LDMA s AR interval s 2 fSYS Hz CPU bus stop rate tSTOP LDMA ARDMA s LHSYNC period s...

Page 108: ...te 70 Hz including 20 clocks of dummy cycles SDRAM auto refresh Every 936 states 15 6 μs Calculation example tSTOP LDMA SegNum K 8 tLRD 8 fSYS Hz 320 16 8 1 fSYS Hz 2 8 fSYS Hz 640 16 67 ns 2 133 33 ns 5 47 μs LHSYNC period s 1 70 Hz COM 20 260 54 95 μs Since SDRAM is auto refreshed once or less in 5 47 μs tSTOP ARDMA 2 fSYS Hz 33 33 ns CPU bus stop rate tSTOP LDMA ARDMA s LHSYNC period s 5 47 μs ...

Page 109: ...ransfer operation LDMA1 for reading data from the display RAM into the FIFO buffer in the LCD controller LDMA is started immediately after data has been transferred to the LCD driver If HDMA is started immediately before LDMA1 is started LDMA must wait until HDMA has finished before it can be started LDMA2 LDMA2 must finish operation before the LCD driver output for the next stage is started LHSYN...

Page 110: ...gNum 1 fSYS LD bus transfer speed 320 1 60 MHz 16 85 μs Since LHSYNC period s LCD driver data transfer time s this setting is not possible When the transfer speed is changed to x4 the LCD driver data transfer time is calculated as follows The transfer speed should be adjusted according to the required specifications LCD driver data transfer time s SegNum 1 fSYS LD bus transfer speed 320 1 60MHz 4 ...

Page 111: ... time is set to 29 9 μs 256 7 1 fSYS Since HDMA start interval period s 83 33 ms is longer than LHSYNC period s 54 95 μs it is assumed that HDMA transfer occurs once during LHSYNC period s Since SDRAM is auto refreshed once or less in 5 47 μs tSTOP ARDMA 2 fSYS Hz 33 33 ns The time LDMA ARDMA and HDMA all occupy the bus is defined as tSTOP LDMA ARDMA HDMA Based on the above the CPU bus stop rate i...

Page 112: ...er LCD display the maximum time HDMA can occupy the bus at a time maximum HDMA time must be set to 19 8875 μS or less Although transferring all 225 Kbytes from the internal RAM to SDRAM requires tSTOP HDMA 9180 μs the maximum HDMA time should be limited by using the HDMATR register HDMATR register 7 6 5 4 3 2 1 0 Bit Symbol DMATE DMATR6 DMATR5 DMATR4 DMATR3 DMATR2 DMATR1 DMATR0 Read Write R W Afte...

Page 113: ...t EA25 P75 1 I O bit R W NDR B Port 7 P76 1 I O bit WAIT P80 1 Output Fixed 0 CS P81 1 Output Fixed 1 CS SDCS P82 1 Output Fixed 2 CS CSZA P83 1 Output Fixed 3 CS CSXA P84 1 Output Fixed CSZB P85 1 Output Fixed CSZC P86 1 Output Fixed CSZD CE 0 ND Port 8 P87 1 Output Fixed CSXB CE 1 ND P90 1 I O bit TXD0 P91 1 I O bit RXD0 P92 1 I O bit SCLK0 0 CTS P96 1 Input PD Fixed INT4 PX Port 9 P97 1 Input F...

Page 114: ...put Fixed LD0 to LD7 PM1 1 Output Fixed MLDALM TA1OUT PM2 1 Output Fixed ALARM MLDALM Port M PM7 1 Output Fixed PWE Port N PN0 to PN7 8 I O bit KO0 to KO7 PP1 1 I O bit TA3OUT PP2 1 I O bit TA5OUT PP3 1 I O bit INT5 TA7OUT PP4 1 I O bit INT6 TB0IN0 PP5 1 I O bit INT7 TB1IN0 PP6 1 Output Fixed TB0OUT0 Port P PP7 1 Output Fixed TB1OUT0 PR0 1 I O bit SPDI PR1 1 I O bit SPDO PR2 1 I O bit SPCS Port R ...

Page 115: ...Name Number of Pins I O R I O Setting Pin Name for built in function PZ0 1 I O bit EI_PODDATA PZ1 1 I O bit EI_SYNCLK PZ2 1 I O bit EI_PODREQ PZ3 1 I O bit EI_REFCLK PZ4 1 I O bit EI_TRGIN PZ5 1 I O bit EI_COMRESET PZ6 1 I O bit EO_MCUDATA Port Z PZ7 1 I O bit EO_MCUREQ ...

Page 116: ...Output X X 1 None P70 to P76 Output port X 1 0 P71 to P76 Input port X 0 0 P70 RD Output X None 1 WRLL Output 1 P71 NDRE Output 0 1 1 WRLU Output 1 P72 NDWE Output 0 1 1 P73 EA24 Output X 1 1 P74 EA25 Output X 1 1 R W Output X 1 1 P75 NDR B Input X 0 1 Port 7 P76 WAIT Input X 0 1 None P80 to P87 Output port X 0 0 P80 0 CS Output X 1 None 1 CS Output X 1 0 P81 SDCS Output X X 1 2 CS Output X 1 0 CS...

Page 117: ... Input X None 1 None Input port X 0 Port A PA0 to PA7 KI0 to KI7 Input X None 1 None Input port X 0 0 PC0 to PC7 Output port X 1 0 PC0 INT0 Input X 0 1 INT1 Input X 0 1 PC1 TA0IN Input X 1 1 PC2 INT2 Input X 0 1 INT3 Input X 0 1 PC3 TA2IN Input X 1 1 PC4 EA26 Output X 0 1 PC5 EA27 Output X 0 1 PC6 EA28 Output X 0 1 Port C PC7 KO8 Output Open drain X 1 1 None PF0 to PF5 Input port X 0 0 PF0 to PF5 ...

Page 118: ...utput X 1 PK2 LFR output X 1 PK3 LVSYNC output X 1 PK4 LHSYNC output X 1 PK5 LGOE0 output X 1 PK6 LGOE1 output X 1 Port K PK7 LGOE2 output X None 1 None PL0 to PL7 Output port X 0 Port L PL0 to PL7 LD0 to LD7 Output X None 1 None PM1 to PM2 Output port X 0 TA1OUTOutput 0 1 PM1 MLDALM Output 1 1 MLDALM Output 0 1 PM2 ALARM Output 1 1 Port M PM7 PWE Output X None 1 None Input port X 0 0 Output port ...

Page 119: ... 0 0 PV6 to PV7 Output port X 1 0 0 PV6 to PV7 Output port Open drain X 1 0 1 PV0 SCLK0 Output X 1 1 None SDA I O X 1 1 0 PV6 SDA I O Open drain X 1 1 1 SCL I O X 1 1 0 Port V PV7 SCL I O Open drain X 1 1 1 PW0 to PW7 Input port X 0 0 Port W PW0 to PW7 Output port X 1 0 None PX5 PX7 Input port X 0 0 PX4 Output port X None 0 PX5 PX7 Output port X 1 0 CLKOUT Output 0 1 PX4 LDIV Output 1 None 1 Port ...

Page 120: ...as a data bus D8 to D15 Setting the AM1 and AM0 pins as shown below and resetting the device initialize port 1 to the following function pins AM1 AM0 Function Setting after reset is released 0 0 1 1 0 1 0 1 Don t use this setting Data bus D8 to D15 Don t use this setting Input port P10 to P17 Figure 3 7 1 Port1 P1CR Register P1FC Register P1 Register S 0 1 Selector S 1 0 Selector External write en...

Page 121: ...nction 0 Input 1 Output Port 1 Function register 7 6 5 4 3 2 1 0 bit Symbol P1F Read Write W After reset Note2 0 1 Function 0 Port 1 Data bus D8 to D15 Port 1 Drive register 7 6 5 4 3 2 1 0 bit Symbol P17D P16D P15D P14D P13D P12D P11D P10D Read Write R W After reset 1 1 1 1 1 1 1 1 Function Input Output buffer drive register for standby mode Note1 Read modify write is prohibited for P1CR P1FC Not...

Page 122: ...bit can be set individually for function Setting the AM1 and AM0 pins as shown below and resetting the device initialize port 4 to the following function pins AM1 AM0 Function Setting after reset is released 0 0 1 1 0 1 0 1 Don t use this setting Address bus A0 to A7 Don t use this setting Output port P40 to 47 Figure 3 7 3 Port4 P4FC Register P4 Register S 0 1 Selector A0 to A7 Read data P40 to P...

Page 123: ... After reset Note2 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Function 0 Port 1 Address bus A0 to A7 Port 4 Drive register 7 6 5 4 3 2 1 0 bit Symbol P47D P46D P45D P44D P43D P42D P41D P40D Read Write R W After reset 1 1 1 1 1 1 1 1 Function Input Output buffer drive register for standby mode Note1 Read modify write is prohibited for P4FC Note2 It is set to Port or Data bus by AM pins state Figure 3 7 4 Regi...

Page 124: ...bit can be set individually for function Setting the AM1 and AM0 pins as shown below and resetting the device initialize port 5 to the following function pins AM1 AM0 Function Setting after reset is released 0 0 1 1 0 1 0 1 Don t use this setting Address bus A8 A15 Don t use this setting Output port P50 P57 Figure 3 7 5 Port5 P5FC Register P5 Register S 0 1 Selector A8 to A15 Read data P50 to P57 ...

Page 125: ... After reset Note2 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Function 0 Port 1 Address bus A8 to A15 Port 5 Drive register 7 6 5 4 3 2 1 0 bit Symbol P57D P56D P55D P54D P53D P52D P51D P50D Read Write R W After reset 1 1 1 1 1 1 1 1 Function Input Output buffer drive register for standby mode Note1 Read modify write is prohibited for P5FC Note2 It is set to Port or Data bus by AM pins state Figure 3 7 6 Reg...

Page 126: ... I O port port6 can also function as an address bus A16 to A23 Setting the AM1 and AM0 pins as shown below and resetting the device initialize port 6 to the following function pins AM1 AM0 Function Setting after reset is released 0 0 1 1 0 1 0 1 Don t use this setting Address bus A16 A23 Don t use this setting Input port P60 P67 Figure 3 7 7 Port6 P6CR Register P6FC Register P6 Register S 0 1 Sele...

Page 127: ...on register 7 6 5 4 3 2 1 0 bit Symbol P67F P66F P65F P64F P63F P62F P61F P60F Read Write W After reset Note2 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Function 0 Port 1 Address bus A16 to A23 Port 6 Drive buffer register 7 6 5 4 3 2 1 0 bit Symbol P67D P66D P65D P64D P63D P62D P61D P60D Read Write R W After reset 1 1 1 1 1 1 1 1 Function Input Output buffer drive register for standby mode Note Read modify ...

Page 128: ... pin to output port mode and P71 to P76 pins to input port mode Setting the AM1 and AM0 pins as shown below and resetting the device initialize port 7 to the following function pins Initial setting of P70 pin AM1 AM0 Function Setting after reset is released 0 0 1 1 0 1 0 1 Don t use this setting RD pin Don t use this setting Output port P70 Figure 3 7 9 Port7 P7 register S 0 1 Selector Port read d...

Page 129: ...r S 1 0 Selector P7CR register P7FC register S 0 1 Selector P73 EA24 P74 EA25 EA24 EA25 Selector P7 register Port read data P7CR register P7FC register S 1 0 S 0 1 NDR B P75 R W B NDR R W Selector P76 WAIT P7 register P7CR register P7FC register WAIT Port read data ...

Page 130: ...P74D P73D P72D P71D P70D Read Write R W After reset 1 1 1 1 1 1 1 Function Input Output buffer drive register for standby mode Note1 Read modify write is prohibited for P7CR P7FC Note2 When NDRE and NDWE are used set registers by following order to avoid outputting negative glitch Order Registser bit2 bit1 1 P7 0 0 2 P7FC 1 1 3 P7CR 1 1 Note3 Note2 It is set to Port or Data bus by AM pins state Fi...

Page 131: ...ing 1 in the corresponding bit of P8FC P8FC2 enables the respective functions Resetting resets P8FC to 0 and P8FC2 to 0 sets all bits to output ports Figure 3 7 12 Port 8 P80 0 CS P81 1 CS SDCS P82 2 CS CSZA SDCS P83 3 CS CSXA P84 CSZB P85 CSZC P86 CSZD CE 0 ND P87 CSXB CE 1 ND Function control Output latch P8 read Reset 0 CS 1 CS 2 CS 3 CS CSZB CSZC CSZD CSXB Selector P8FC write P8 write S Functi...

Page 132: ...ad Write R W After reset 1 1 1 1 1 1 1 1 Function Input Output buffer drive register for standby mode Note1 Read modify write is prohibited for P8FC and P8FC2 Note2 Don t write 1 to P8 P82 register before setting P82 pin to CS2 or CSZA because of P82 pin output 0 as CE for program memory by reset Note3 If it is started at boot mode AM 1 0 11 output latch of P82 is set to 1 Note4 When CE 0 ND and C...

Page 133: ... and sets all bits to input ports 1 Port 90 TXD0 Port 91 RXD0 Port 92 SCLK0 0 CTS Port 90 to 92 are general purpose I O port They are also used either SIO0 Each pin is below SIO mode SIO0 module UART IrDA mode SIO0 module P90 TXD0 Data output TXD0 Data output P91 RXD0 Data input RXD0 Data input P92 SCLK0 Clock input or output 0 CTS Clear to send Figure 3 7 14 P90 Internal data bus Selector A B S S...

Page 134: ...ion control on bit basis S Output latch P9 write Reset P9FCwrite RXD0 input SCLK0 input 0 CTS input TSICR0 PXEN PYEN IIMC I4EDGE P96 INT4 PX P97 PY P9 read Function control Reset P9FC write INT4 Rising Falling edge ditection TSICR0 TSI7 TSICR0 PXEN TSICR0 TSI7 Selector De bounce Circuit A S TSICR1 DBC7 Only for P96 AVCC Switch for TSI typ 10Ω Pull down resistor typ 50KΩ B TSICR0 TWIEN TSI7 Interna...

Page 135: ...open drain Port 9 drive register 7 6 5 4 3 2 1 0 bit Symbol P97D P96D P92D P91D P90D Read Write R W R W After reset 1 1 1 1 1 Function Input Output buffer drive register for standby mode Note 1 Read modify write is prohibited for P9CR P9FC and P9FC2 Note 2 When setting P96 pin to INT4 input set P9DR P96D to 0 prohibit input and when driving P96 pin to 0 execute HALT instruction This setting genera...

Page 136: ... enabled by writing a 1 to the corresponding bit of the Port A Function Register PAFC Resetting resets all bits of the register PAFC to 0 and sets all pins to be input port Figure 3 7 18 Port A When PAFC 1 if either of input of KI0 KI7 pins falls down INTKEY interrupt is generated INTKEY interrupt can release all HALT mode Internal data bus PA0 to PA7 KI0 to KI7 INTKEY Rising edge ditection KEY ON...

Page 137: ... PA4F PA3F PA2F PA1F PA0F Read Write W After reset 0 0 0 0 0 0 0 0 Function 0 KEY IN disable 1 KEY IN enable Port A Drive register 7 6 5 4 3 2 1 0 bit Symbol PA7D PA6D PA5D PA4D PA3D PA2D PA1D PA0D Read Write R W After reset 1 1 1 1 1 1 1 1 Function Input Output buffer drive register for standby mode Note 1 Read modify write is prohibited for PAFC Figure 3 7 19 Register for Port A PAFC 002BH PA 00...

Page 138: ... input pin for external interruption INT0 to INT3 Extension address function EA26 EA27 EA28 and output pin for Key KO8 Above setting is used the function register PCFC Edge select of external interruption establishes it with IIMC register which there is in interruption controller 1 PC0 INT0 PC2 INT2 Figure 3 7 20 Port C0 C2 PC0 INT0 PC2 INT2 Internal data bus Direction control Reset PCCR write PCw...

Page 139: ...1 Port C1 C3 PC1 INT1 TA0IN PC3 INT3 TA2IN Internal data bus Direction control Reset PCCR write PCwrite PC read Function control PCFCwrite S Output latch S B Selector A Level edge selection and Rising Falling selection IIMC I1LE I1EDGE I3LE I3EDGE INT1 INT3 TA0IN TA2IN ...

Page 140: ...O8 PC read Direction control PCCR write Function control PCFC write S Output latch PC write Open drain enable Internal data bus Selector A B S PC4 EA26 PC5 EA27 PC6 EA28 PC read Direction control on bit basis PCCRwrite Function control on bit basis PCFC write S Output latch PC write Reset Selector A B S Internal data bus C EA26 EA27 EA28 ...

Page 141: ...te 2 When setting PC3 PC0 pins to INT3 INT0 input set PCDR PC3D PC0D to 0000 prohibit input and when driving PC3 PC0 pins to 0 execute HALT instruction This setting generates INT3 INT0 inside If don t use external interrupt in HALT condition set like an interrupt don t generated e g change port setting Figure 3 7 24 Register for Port C PCFC 0033H PC 0030H PCCR 0032H PCDR 008CH PC0C PC0F 0 1 0 Inpu...

Page 142: ...ort F Function Register PFFC Port F7 is 1 bit general purpose output port In addition to functioning as general purpose output port PF7 can also function as the SDCLK output Resetting sets PF7 to be a SDCLK output port 1 Port F0 I2S0CKO Port F1 I2S0DO Port F2 I2S0WS Port F3 I2S1CKO Port F4 I2S1DO Port F5 I2S1WS Port F0 to F5 are general purpose I O port They are also used either I2S Each pin is be...

Page 143: ...utput PF read Direction control on bit basis PFCR write Function control on bit basis S Output latch PF write Reset PFFC write Internal data bus Selector A B S Selector A B S PF1 I2S0DO PF2 I2S0WS PF4 I2S1DO PF5 I2S1WS I2S0DO I2S1DO output I2S0WS I2S1WS output PF read Direction control on bit basis PFCRwrite Function control on bit basis S Output latch PF write Reset PFFC write ...

Page 144: ...se output port In addition to functioning as general purpose output port PF7 can also function as the SDCLK output Figure 3 7 27 Port F7 SDCLK Selector A B S PF7 SDCLK PF read Function control on bit basis PFFC write S Output latch PF write Reset Internal data bus ...

Page 145: ...ister 7 6 5 4 3 2 1 0 bit Symbol PF7D PF6D PF5D PF4D PF3D PF2D PF1D PF0D Read Write R W After reset 1 1 1 1 1 1 1 1 Function Input Output buffer drive register for standby mode Note 1 Read Modify Write is prohibited for the registers PFCR PFFC and PFFC2 Figure 3 7 28 Register for Port F PFFC 003FH PF 003CH PFCR 003EH PFDR 008FH PF0C PF0F 0 1 0 Input port Output port 1 I2S0CKOoutput PF0 setting PF1...

Page 146: ...screen interface PG register is prohibited to access by byte All the instruction Arithmetic Logical Bit operation and rotate shift instruction access by byte are prohibited Word access is always needed Figure 3 7 29 Port G AD read Conversion Result Register AD Converter Channel Selector Port G read PG0 AN0 PG1 AN1 PG2 AN2 MX PG3 AN3 MY ADTRG PG4 AN4 PG5 AN5 ADTRG for PG3 only TSICR0 MXEN MYEN TSIC...

Page 147: ... 6 5 4 3 2 1 0 Bit Symbol PG3D PG2D Read Write R W After reset 1 1 Function Input Output buffer drive register for standby mode Figure 3 7 30 Register for Port G Note 1 Read Modify Write is prohibited for the registers PGFC Note 2 PG register is prohibited to access by byte All the instruction Arithmetic Logical Bit operation and rotate shift instruction access by byte are prohibited Word access i...

Page 148: ...d SRLUB and NAND Flash NDALE and NDCLE Above setting is used the function register PJFC But Output signal either SDRAM or SRAM for PJ0 to PJ2 are selected automatically according to the setting of memory controller Figure 3 7 31 Port J0 to J4 and J7 S Function control on bit basis Selector PJ read Reset PJ0 SDRAS SRLLB PJ1 SDCAS SRLUB PJ2 SDWE SRWR PJ3 SDLLDQM PJ4 SDLUDQM PJ7 SDCKE SDRAS SDCAS SDW...

Page 149: ...Z26A 146 Figure 3 7 32 Port J5 J6 Internal data bus Selector A B S Selector A B S PJ5 NDALE PJ6 NDCLE NDALE NDCLE output PJ read Direction control PJCR write Function control S Output latch PJ write Reset PJFC write ...

Page 150: ...7F PJ6F PJ5F PJ4F PJ3F PJ2F PJ1F PJ0F Read Write W After reset 0 0 0 0 0 0 0 0 Function 0 Port 1 SDCKE 0 Port 1 NDCLE 0 Port 1 NDALE 0 Port 1 SDLUDQM 0 Port 1 SDLLDQM 0 Port 1 SDWE SRWR 0 Port 1 SDCAS SRLUB 0 Port 1 SDRAS SRLLB Port J drive register 7 6 5 4 3 2 1 0 bit Symbol PJ7D PJ6D PJ5D PJ4D PJ3D PJ2D PJ1D PJ0D Read Write R W After reset 1 1 1 1 1 1 1 1 Function Input Output buffer drive regis...

Page 151: ... function as output pins for LCD controller LCP0 LHSYNC LLOAD LFR LVSYNC and LGOE0 to LGOE2 Above setting is used the function register PKFC Figure 3 7 34 Port K0 to K7 Function control on bit basis Output latch PK read Reset Output buffer PKFC write PK write S A B Selector Internal data bus LCP0 LLOAD LFR LVSYNC LHSYNC LGOE0 to LGOE2 PK0 LCP0 PK1 LLOAD PK2 LFR PK3 LVSYNC PK4 LHSYNC PK5 LGOE0 PK6 ...

Page 152: ...0 0 0 0 0 0 0 Function 0 Port 1 LGOE2 0 Port 1 LGOE1 0 Port 1 LGOE0 0 Port 1 LHSYNC 0 Port 1 LVSYNC 0 Port 1 LFR 0 Port 1 LLOAD 0 Port 1 LCP0 Port K drive register 7 6 5 4 3 2 1 0 bit Symbol PK7D PK6D PK5D PK4D PK3D PK2D PK1D PK0D Read Write R W After reset 1 1 1 1 1 1 1 1 Function Input Output buffer drive register for standby mode Note 1 Read Modify Write is prohibited for the registers PKFC Fig...

Page 153: ...utput 0 In addition to functioning as a general purpose output port Port L can also function as a data bus for LCD controller LD0 to LD7 Above setting is used the function register PLFC Figure 3 7 36 Port L0 to L7 Selector A B S PL0 to PL7 LD0 to LD7 Function control PLFC write R Output latch PL write Reset LD0 to LD7 PL read Internal data bus ...

Page 154: ...L2F PL1F PL0F Read Write W After reset 0 0 0 0 0 0 0 0 Function 0 Port 1 Data bus for LCDC LD7 toLD0 Port L drive register 7 6 5 4 3 2 1 0 bit Symbol PL7D PL6D PL5D PL4D PL3D PL2D PL1D PL0D Read Write R W After reset 1 1 1 1 1 1 1 1 Function Input Output buffer drive register for standby mode Note 1 Read Modify Write is prohibited for the registers PLFC Figure 3 7 37 Register for Port L PL 0054H P...

Page 155: ...ins for RTC alarm ALARM output pin for melody alarm generator MLDALM MLDALM and Power control pin PWE Above setting is used the function register PMFC PM1 has two output function which MLDALM and TA1OUT and PM2 has two output function which ALARM and MLDALM This selection is used PM PM1 PM PM2 Figure 3 7 38 Port M1 MLDALM Reset S Output latch PM write PM Reset Function control PMFC write S A Y Sel...

Page 156: ... S Output latch PM write PM read Function control on bit basis PMFC write S A Y Selector B PM7 PWE Internal data bus MLDALM Reset S Output latch PM write PM read Function control on bit basis PMFC write S A Y Selector B ALARM PM2 ALARM MLDALM A S Y Selector B Internal data bus ...

Page 157: ...t 1 PWE 0 Port 1 ALARM at PM2 1 MLDALM at PM2 0 0 Port 1 MLDALM at PM1 1 TA1OUT at PM1 0 Port M drive register 7 6 5 4 3 2 1 0 bit Symbol PM7D PM2D PM1D Read Write R W R W After reset 1 1 1 Function Input Outp ut buffer drive register for standby mode Input Output buffer drive register for standby mode Note 1 Read Modify Write is prohibited for the registers PMFC Figure 3 7 41 Register for Port M ...

Page 158: ...n addition to functioning as a general purpose I O port Port N can also function as interface pin for key board KO0 to KO7 This function can set to open drain type output buffer Figure 3 7 42 Port N Selector A B S PN0 KO0 to PN7 KO7 PC read Direction control on bit basis PNCR write Function control on bit basis PNFC write S Output latch PN write Reset Open drain enable Internal data bus ...

Page 159: ...nput 1 Output Port N function register 7 6 5 4 3 2 1 0 bit Symbol PN7F PN6F PN5F PN4F PN3F PN2F PN1F PN0F Read Write W After reset 0 0 0 0 0 0 0 0 Function 0 CMOS output 1 Open drain output Port N drive register 7 6 5 4 3 2 1 0 bit Symbol PN7D PN6D PN5D PN4D PN3D PN2D PN1D PN0D Read Write R W After reset 1 1 1 1 1 1 1 1 Function Input Output buffer drive register for standby mode Note 1 Read Modif...

Page 160: ...to functioning as output port PP6 and PP7 can also function as output pin for timers TB0OUT0 TB1OUT1 Above setting is used the control register PPCR and function register PPFC Edge select of external interruption establishes it with IIMC register which there is in interruption controller In port setting if 16 bit timer input is selected and capture control is executed INT6 and INT7 don t depend on...

Page 161: ...R Output latch S B Selector A Level edge selection and Rising Falling selection IIMC I1LE I1EDGE I3LE I3EDGE INT6 INT7 TB0IN0 TB1IN0 from TMRB0 INT6 from TMRB1 INT7 Selector A B S PP3 INT5 TA7OUT PP read Direction control on bit basis PPCR write Function control on bit basis R Output latch PP write Reset PPFC write Level edge selection and Rising Falling selection INT5 IIMC I5LE I5EDGE Selector B ...

Page 162: ...P92CZ26A 92CZ26A 159 Figure 3 7 47 Port P6 P7 Selector A B S PP6 TB0OUT0 PP7 TB1OUT0 TB0OUT0 output TB1OUT0 output Function control on bit basis R Output latch PP write Reset PPFC write Internal data bus ...

Page 163: ...r drive register for standby mode Note1 Read Modify Write is prohibited for the registers PPCR PPFC Note2 When setting PP5 PP4 PP3 pins to INT7 INT6 INT5 input set PPDR PP5D 3D to 0000 prohibit input and when driving PP5 PP4 PP3 pins to 0 execute HALT instruction This setting generates INT7 INT6 and INT5 inside If don t using external interrupt in HALT condition set like an interrupt don t generat...

Page 164: ...to 0 In addition to functioning as general purpose I O port pins PR0 to PR3 can also function as SPI controller pin SPCLK SPCS SPDO and SPDI Above setting is used the control register PRCR and function register PRFC Figure 3 7 49 Port R0 Selector A B S PR0 SPDI PR read Direction control on bit basis PRCR write Function control on bit basis PRFC write R Output latch PR write Reset SPDI input Intern...

Page 165: ... 7 50 Port R1 to R3 Selector A B S PR1 SPDO PR2 SPCS PR3 SPCLK PR read Direction control on bit basis PRCR write Function control on bit basis PRFC write R Output latch PR write Reset Selector A B S SPDO SPCS SPCLK Internal data bus ...

Page 166: ...t 1 SPCS 0 Port 1 SPDO 0 Port 1 SPDI Port R drive register 7 6 5 4 3 2 1 0 bit Symbol PR3D PR2D PR1D PR0D Read Write R W After reset 1 1 1 1 Function Input Output buffer drive register for standby mode Note Read Modify Write is prohibited for the registers PRCR PRFC Figure 3 7 51 Register for Port R PR 0064H PRFC 0067H PRDR 0099H PRCR 0066H PR0C PR0F 0 1 0 Input port Output port 1 SPDI input Reser...

Page 167: ...to functioning as general purpose I O port pins PT0 to PT7 can also function as data bus pin for LCD controller LD8 to LD15 Above setting is used the control register PTCR and function register PTFC Figure 3 7 52 Port T0 to T7 Selector A B S Selector A B S PT0 to PT7 LD8 to LD15 PT read Direction control on bit basis PTCR write Function control on bit basis PTFC write S Output latch PT write Reset...

Page 168: ... register 7 6 5 4 3 2 1 0 bit Symbol PT7F PT6F PT5F PT4F PT3F PT2F PT1F PT0F Read Write W After reset 0 0 0 0 0 0 0 0 Function 0 Port 1 Data bus for LCDC LD15 to LD8 Port T drive register 7 6 5 4 3 2 1 0 bit Symbol PT7D PT6D PT5D PT4D PT3D PT2D PT1D PT0D Read Write R W After reset 1 1 1 1 1 1 1 1 Function Input Output buffer drive register for standby mode Note1 Read Modify Write is prohibited for...

Page 169: ...etting is used the control register PUCR and function register PUFC In addition to functioning as above function PU7 can also function as communication for debug mode EO_TRGOUT These functions are operated when it is started in debug mode In this case PU7 can not be used as LD23 function Figure 3 7 54 Port U0 to U4 U6 U7 Selector A B S Selector A B S PU read Direction control on bit basis PUCR wri...

Page 170: ...CZ26A 167 Figure 3 7 55 Port U5 Selector A B S Selector A B S PU5 LD21 PU read Direction control on bit basis PUCR wirte Function control on bit basis PUFC write R Output latch PU write Reset LD21 Internal data bus ...

Page 171: ...Write W After reset 0 0 0 0 0 0 0 0 Function 0 Port 1 LD23 0 Port 1 LD22 0 Port 1 LD21 PU5C 1 0 Port 1 LD20 0 Port 1 LD19 0 Port 1 LD18 0 Port 1 LD17 0 Port 1 LD16 Note When PU is used as LD23 to LD16 set applicable PUnC to 1 Port U drive register 7 6 5 4 3 2 1 0 Bit Symbol PU7D PU6D PU5D PU4D PU3D PU2D PU1D PU0D Read Write R W After reset 1 1 1 1 1 1 1 1 Function Input Output buffer drive registe...

Page 172: ...t for SIO SCLK0 Note Above setting is used the control register PVCR and function register PVFC Port V3 and V4 are 2 bit general purpose output ports Resetting clear port V3 and V4 to output latch to 0 Note SIO function support function that input clock from SCLK0 basically However if setting to PV0 pin this function supports only the output function Figure 3 7 57 Port V0 to V2 PV0 SCLK0 PV1 PV2 I...

Page 173: ...ctor A B S PV6 SDA PV7 SCL PV read Direction control on bit basis PVCR write Function control on bit basis PVFC write R Output latch PV write Reset SDA SCL output SDA SCL input Open drain enable PVFC2 PV6F2 PV7F2 Internal data bus Reset R Output latch PV write PV read PV3 PV4 Internal data bus ...

Page 174: ...l PV7F2 PV6F2 Read Write W W After reset 0 0 Function 0 CMOS 1 Open drain 0 CMOS 1 Open drain Port V drive register 7 6 5 4 3 2 1 0 bit Symbol PV7D PV6D PV4D PV3D PV2D PV1D PV0D Read Write R W R W After reset 1 1 1 1 1 1 1 Function Input Output buffer drive register for standby mode Figure 3 7 60 Register for Port V PVFC 00ABH PV 00A8H PVCR 00AAH PVDR 009DH PVFC2 00A9H PV0C PV0F 0 1 0 Input port O...

Page 175: ...or output Resetting sets port W0 to W7 to input port and output latch to 0 Above setting is used the control register PWCR and function register PWFC Figure 3 7 61 Port W0 to W7 Selector A B S PW0 to PW7 PW read Direction control on bit basis PWCR write Function control on bit basis PWFC write R Output latch PW write Reset Internal data bus ...

Page 176: ...Function 0 Input 1 Output Port W function register 7 6 5 4 3 2 1 0 bit Symbol PW7F PW6F PW5F PW4F PW3F PW2F PW1F PW0F Read Write W After reset 0 0 0 0 0 0 0 0 Function 0 Port 1 Reserved Port W drive register 7 6 5 4 3 2 1 0 bit Symbol PW7D PW6D PW5D PW4D PW3D PW2D PW1D PW0D Read Write R W After reset 1 1 1 1 1 1 1 1 Function Input Output buffer drive register for standby mode Note1 Read Modify Wri...

Page 177: ... Above setting is used the control register PXCR and function register PXFC Port X4 is 1 bit general purpose output port Resetting sets output latch to 0 In addition to functioning as general purpose output port PX4 can also function as system clock output pin CLKOUT and output pin LDIV This setting is used the PX register and function register PXFC Figure 3 7 63 Port X4 Selector A B S PX4 CLKOUT ...

Page 178: ...CZ26A 175 Figure 3 7 64 Port X5 X7 Selector A B S PX5 X1USB PX7 PX read Direction control on bit basis PXCR write Function control on bit basis PXFC write R Output latch PX write Reset Internal data bus X1USB input ...

Page 179: ...1 Output Port W function register 7 6 5 4 3 2 1 0 bit Symbol PX7F PX5F PX4F Read Write W W After reset 0 0 0 Function 0 Port 1 Reserved 0 Port 1 X1USB input 0 Port 1 CLKOUT at PX4 0 LDIV at PX4 1 Port W drive register 7 6 5 4 3 2 1 0 bit Symbol PXD7 PXD5 PXD4 Read Write R W R W After reset 1 1 1 Function Input Output buffer drive register for standby mode Note Read Modify Write is prohibited for t...

Page 180: ...EI_SYNCLK EI_PODREQ EI_REFCLK EI_TRGIN EI_COMRESET EO_MCUDATA and EO_MCUREQ These functions are operated when it is started in debug mode There is not Function register in this port When DBGE is set to 0 this port set to debug communication function Figure 3 7 66 Port Z0 to Z5 Selector A B S PZ0 EI_PODDATA PZ1 EI_SYNCLK PZ2 EI_PODREQ PZ3 EI_REFCLK PZ4 EI_TRGIN PZ5 EI_COMRESET PZ read Direction con...

Page 181: ...178 Figure 3 7 67 Port Z6 to Z7 Selector A B S PZ6 EO_MCUDATA PZ7 EO_MCUREQ PZ read Direction control on bit basis PZCR write R Output latch PZ write Reset Internal data bus Selector A B S EO_MCUDATA EO_MCUREQ Debug mode ...

Page 182: ... Symbol PZ7C PZ6C PZ5C PZ4C PZ3C PZ2C PZ1C PZ0C Read Write W After reset 0 0 0 0 0 0 0 0 Function 0 Input 1 Output Port Z drive register 7 6 5 4 3 2 1 0 bit Symbol PZ7D PZ6D PZ5D PZ4D PZ3D PZ2D PZ1D PZ0D Read Write R W After reset 1 1 1 1 1 1 1 1 Function Input Output buffer drive register for standby mode Note Read Modify Write is prohibited for the registers PZCR Figure 3 7 68 Register for Port ...

Page 183: ...set BROMCR CSDIS to 1 as external area for avoiding conflicting with other CS memory 2 Connecting memory specifications Specifies SRAM ROM SDRAM as memories to connect with the selected address areas 3 Data bus width selection Whether 8 bit or 16bit is selected as the data bus width of the respective block address areas 4 Wait control Wait specification bit in the control register and WAIT input p...

Page 184: ...the basic functions of the memory controller that is the connecting memory type the number of waits to be read and written Memory start address register MSARn n 0 to 3 Sets a start address in the selected address areas Memory address mask register MAMR n 0 to 3 Sets a block size in the selected address areas Page ROM control register PMEMCR Sets to control Page ROM Adjust the timing of control sig...

Page 185: ...Write R W After Reset 1 1 1 1 1 1 1 1 Bit symbol B2WW3 B2WW2 B2WW1 B2WW0 B2WR3 B2WR2 B2WR1 B2WR0 Read Write R W After Reset 0 0 1 0 0 0 1 0 Bit Symbol B2E B2M B2REC B2OM1 B2OM0 B2BUS1 B2BUS0 Read Write R W R W After Reset 1 0 0 0 0 0 0 Bit Symbol M2V22 M2V21 M2V20 M2V19 M2V18 M2V17 M2V16 M2V15 Read Write R W After Reset 1 1 1 1 1 1 1 1 Bit Symbol M2S23 M2S22 M2S21 M2S20 M2S19 M2S18 M2S17 M2S16 Rea...

Page 186: ... TAC1 TAC0 Read Write R W R W CSTMGCR 0168H After Reset 0 0 0 0 Bit Symbol TCWSEL1 TCWSEL0 TCWS1 TCWS0 TCWH1 TCWH0 Read Write R W R W R W WRTMGCR 0169H After Reset 0 0 0 0 0 0 Bit Symbol B1TCRS1 B1TCRS0 B1TCRH1 B1TCRH0 B0TCRS1 B0TCRS0 B0TCRH1 B0TCRH0 Read Write R W R W R W R W RDTMGCR0 016AH After Reset 0 0 0 0 0 0 0 0 Bit Symbol B3TCRS1 B3TCRS0 B3TCRH1 B3TCRH0 B2TCRS1 B2TCRS0 B2TCRH1 B2TCRH0 Read...

Page 187: ...er reset only control register B2CSH B2CSL of the block address area 2 is effective automatically B2CSH B2E is set to 1 by reset The data bus width which is specified by AM1 AM0 pin is loaded to the bit to specify the bus width of the control register in the block address area 2 The block address area 2 is set to address 000000H to FFFFFFH by reset B2CSH B2M is reset to 0 After releasing reset the...

Page 188: ...anently set to 0 Accordingly the start address can only be set in 64 Kbyte increments starting from 000000H Figure 3 8 2 shows the relationship between the start address and the start address register value Memory Start Address Registers for areas CS0 to CS3 7 6 5 4 3 2 1 0 Bit symbol S23 S22 S21 S20 S19 S18 S17 S16 Read Write R W After reset 1 1 1 1 1 1 1 1 Function Determines A23 to A16 of start...

Page 189: ...ss area 2 to addresses 000000H to FFFFFFH Setting B2M bit to 1 specifies the start address and the address area size as it is in the other block address area MemoryAddress Mask Register for CS0 area 7 6 5 4 3 2 1 0 Bit symbol V20 V19 V18 V17 V16 V15 V14 9 V8 Read Write R W After reset 1 1 1 1 1 1 1 1 Function Sets size of CS0 area 0 Used for address compare Range of possible settings for CS0 area ...

Page 190: ...ory start address CS0 area size 64 Kbytes Memory address mask register setting MSAR0 MSMR0 Setting of 07H specifies a 64 Kbyte area d Address area size specification Table 3 8 3 shows the relationship between CS area and area size Δ indicates areas that cannot be set by memory start address register and address mask register combinations When setting an area size using a combination indicated by Δ...

Page 191: ...ck address area Priority When the set block address area overlaps with the built in memory area or both two address areas overlap the block address area is processed according to priority as follows f Wait control for outside the block address area of CS0 to CS3 Also that any accessed areas outside the address spaces set by CS0 to CS3 are processed as the CSEX space Therefore settings of CSEX BEXC...

Page 192: ...BUS1 0 BnBUS1 BnBUS0 Function 0 0 8 bit bus mode Default 0 1 16 bit bus mode 1 0 Reserved 1 1 Don t use this setting Note1 SDRAM should be set to 01 16 bit bus This way of changing the data bus width depending on the address being accessed is called dynamic bus sizing The part where the data is output to is depended on the data width the bus width and the start address The number of external data ...

Page 193: ...0 2 4n 1 xxxxx xxxxx xxxxx b15 to b8 3 4n 2 xxxxx xxxxx xxxxx b23 to b16 8 4 4n 3 xxxxx xxxxx xxxxx b31 to b24 1 4n 0 xxxxx xxxxx b15 to b8 b7 to b0 16 2 4n 2 xxxxx xxxxx b31 to b24 b23 to b16 4n 0 32 4n 0 b31 to b24 b23 to b16 b15 to b8 b7 to b0 1 4n 0 xxxxx xxxxx xxxxx b7 to b0 2 4n 1 xxxxx xxxxx xxxxx b15 to b8 3 4n 2 xxxxx xxxxx xxxxx b23 to b16 8 4 4n 3 xxxxx xxxxx xxxxx b31 to b24 1 4n 1 xxx...

Page 194: ...e 1 1 0 0 11 states 9 waits access fixed mode 1 1 0 1 12 states 10 waits access fixed mode 1 1 1 0 14 states 12 waits access fixed mode 1 1 1 1 18 states 16 waits access fixed mode 0 1 0 0 22 states 20 waits access fixed mode 0 0 1 1 6 states WAIT pin input mode others Reserved Note 1 For SDRAM above setting is ineffective Refer to the section 3 18 SDRAM controller Note 2 For NAND flash this setti...

Page 195: ...this problem 1 dummy cycle can be inserted after CSm block access cycle by setting 1 to BmCSH BmREC register This 1 dummy cycle is inserted when the next cycle is for another CS block BnCSH BnREC 0 No dummy cycle is inserted Default 1 Dummy cycle is inserted When not inserting a dummy cycle 0 waits When inserting a dummy cycle 0 waits SDCLK A23 to A0 CSm CSn RD SDCLK A23 to A0 CSm CSn RD Dummy ...

Page 196: ... not be used together with BnCSH BnREC function For control signal of SDRAM it can be adjusted in SDRAM controller CSTMGCR TxxSEL1 0 WRTMGCR TxxSEL1 0 00 Change the timing of CS0 area 01 Change the timing of CS1 area 10 Change the timing of CS2 area 11 Change the timing of CS3 area CSTMGCR TAC1 0 00 TAC 0 fSYS Default 01 TAC 1 fSYS 10 TAC 2 fSYS 11 Reserved TAC The delay from A23 0 to CSn CSZx CSX...

Page 197: ...5 fSYS TCRS The delay from CSn to RD SRxxB Note TW cycle is inserted by setting BnCSL register If it is set to 0 Wait TW cycle is not inserted A23 to 0 CSn R W T1 T2 SDCLK 80MHz RD SRxxB Input D15 to 0 Read cycle T3 Tn TAC TCRS TCRH Tn 1 WRxx SRWR SRxxB D15 to 0 TCWS TCWH TAC Output Tn 2 Write cycle Output TCWS TW ...

Page 198: ...rite cycle 0 waits b External read write cycle 1 wait CSn WRxx RD SRxxB A23 to A0 Input Output Read Write SDCLK 60 MHz D15 to D0 D15 to D0 T1 T2 SRWR SRxxB CSn WRxx RD SRxxB A23 to A0 Output SDCLK 60 MHz D15 to D0 D15 to D0 T1 TW Input Read Write T2 SRWR SRxxB ...

Page 199: ... 5fSYS d External read write cycle 4 waits WAIT pin input mode Read T1 T6 Input Output Write T2 T3 T4 T5 TAC TAC TCRS TCRH TCWS TCWH TCWS TCWH D15 to 0 A23 to 0 D15 to 0 WRxx SDCLK 80 MHz RD SRxxB SRWR SRxxB CSn WAIT Write Sampling Read T1 T6 Input Output T2 T3 T4 T5 D15 to 0 A23 to 0 D15 to 0 WRxx SDCLK 80 MHz RD SRxxB SRWR SRxxB CSn WAIT ...

Page 200: ...External write bus cycle 4 waits WAIT pin input mode TAC 1fSYS TCWS H 1 5fSYS Sampling Read T1 T6 Input Output Write T2 T3 T4 T5 TW Sampling D15 to 0 A23 to 0 D15 to 0 WRxx SDCLK 80 MHz RD SRxxB SRWR SRxxB CSn WAIT Sampling Read T1 T9 Input Output Write T2 T3 T4 T7 TW Sampling T8 T10 D15 to 0 A23 to 0 D15 to 0 WRxx SDCLK 80 MHz RD SRxxB SRWR SRxxB CSn WAIT TCWS TCWS ...

Page 201: ...nnect external 16 bit SRAM and 16 bit NOR flash to the TMP92CZ26A Figure 3 8 4 Example of External 16 Bit SRAM and NOR Flash Connection TMP92CZ26A 16 bit SRAM RD SRLLB SRLUB SRWR 0 CS D 15 0 A0 A1 A2 A3 2 CS OE LDS UDS R W CE I O 16 1 A0 A1 A2 16 bit NOR flash OE WE CE DQ 15 0 A0 A1 A2 Not connect ...

Page 202: ... 1 2 state n 2 2 2 mode n 3 1 0 3 state n 3 3 3 mode n 4 1 1 4 state n 4 4 4 mode n 5 Note Set the number of waits n to the control register BnCSL in each block address area The page size the number of bytes of ROM in the CPU size is set to PMEMCR PR1 0 When data is read out until a border of the set page the controller completes the page reading operation The start data of the next page is read i...

Page 203: ...a is assigned FFFF00H to FFFFEFH A area in TLCS 900 H1 But because boot ROM is assigned to another area reset interrupt vector address conversion circuit is prepared In BOOT mode reset interrupt vector area is assigned 3FFF00H to 3FFFEFH B area area by it And after boot sequence its area can be changed to A area by setting BROMCR VACE to 0 So A area can be used only for application system program ...

Page 204: ... boot ROM can be disappered by setting BROMCR ROMLESS to 1 This ROMLESS is initialized to 0 in BOOT mode At another starting mode this bit is initialized to 1 If this bit has been set to 1 writing 0 is disabled 7 6 5 4 3 2 1 0 Bit symbol CSDIS ROMLESS VACE BROMCR 016CH Read Write R W After Reset 1 0 1 note 1 0 note Function Nand_Flash area CS output 0 Enable 1 Disable Boot ROM 0 use 1 not use Vect...

Page 205: ... correctly If the read signal in the cycle immediately preceding the access to the NOR flash does not go high in time as shown in Figure 3 8 7 an unintended read cycle like the one shown in b may occur Figure 3 8 7 NOR Flash Toggle Bit Read Cycle When the toggle bit reverse with this unexpected read cycle CPU always reads same value of the toggle bit and cannot read the toggle bit correctly To avo...

Page 206: ... 296 Kbytes in CS3 s memory can t be used Note2 16 byte area 001FF0H to 001FFFH for NAND Flash are fixed like a following without relationship to setting CS bock Therefore NAND flash area don t according to CS3 area setting NAND Flash area specification 1 bus width Depend on NDFMCR1 BUSW in NAND Flash controller 2 WAIT control Depend on NDFMCR SPLW1 0 SPHW1 0 in NAND Flash controller Figure 3 8 8 ...

Page 207: ... set as BANK is called COMMON area Basically one series of program should be closed within one bank Please don t jump to the same LOCAL area in the different bank directly by JP instruction and so on Refer to the examples as follows TMP92CZ26A has following external pins to connect external memory LSI Address bus EA28 EA27 EA26 EA25 EA24 and A23 to A0 Chip Select 0 CS to 3 CS CSXA to CSXB CSZA toC...

Page 208: ...N X 2MB Internal I O RAM CSZA pin Note 512MB 4MB 128 CSZB pin CSZD pin SDCS 64MB SDRAM case 2MB 32 or 1 CS pin 128MB 2MB 64 CSXA 512MB 2MB 256 CE 0 ND pin 512MB CE 1 ND pin 512MB CS3 area 4MB CS1 area 4MB CS2 area 8MB Memory controller setting Vector area 63 255 256 511 CSXB 512MB 2MB 256 Note1 CSZA is a chip select for not only bank0 to 127 of LOCAL Z but also COMMON Z Note2 In case of connect SD...

Page 209: ...AM LOCAL X LOCAL Y LOCAL Z CSZA to CSZD EA24 to 28 512MB 4 2048MB Bank0 92CZ26A CSZD CSZB CSZC CSZA Bank0 63 Bank0 127 Bank384 511 255 Bank256 383 255 511 CSXA CSXB Bank256 Bank128 Note In case of connect SDRAM to Y area 64MB 2MB 32 is maximum Figure 3 9 2 Recommendation memory map for maximum specification Physical address ...

Page 210: ...n 512MB CE 1 ND pin 512MB CS2 area 8MB Vector area SDCS pin 64MB 4MB 16 Internal Boot ROM 8KB 3FE000H Memory controller setting Note In case of connect SDRAM to Z area 64MB 4MB 16 is maximum Figure 3 9 3Recommendation memory map for simple system Logical address 000000H Internal I O and RAM LOCAL Z SDCS 4MB 16 64MB 92CZ26A SDCS Bank 0 15 3FE000H Internal Boot ROM Note In case of connect SDRAM to Z...

Page 211: ...Y or Z is disabled Program bank setting of each local area must change in common area But bank setting of data Read data Write and LCDC display data can change also in local area 3 After data bank number LOCALRn LOCALWn or LOCALLn LOCALEDn LOCALSn LOCALODn n means X Y or Z register is set by an instruction don t access its memory by next instruction because of some clocks are needed to be effectiv...

Page 212: ... to 111111111 CSXB LOCAL Y register for Program 7 6 5 4 3 2 1 0 bit Symbol Y5 Y4 Y3 Y2 Y1 Y0 Read Write R W After reset 0 0 0 0 0 0 Function Set BANK number for LOCAL Y 3 is disabled because of overlapped with Common area 15 14 13 12 11 10 9 8 bit Symbol LYE Read Write R W After reset 0 Function BANK for LOCALY 0 Disable 1 Enable LOCAL Z register for Program 7 6 5 4 3 2 1 0 bit Symbol Z7 Z6 Z5 Z4 ...

Page 213: ...A 100000000 111111111 CSXB LOCAL Y register for LCD 7 6 5 4 3 2 1 0 bit Symbol Y5 Y4 Y3 Y2 Y1 Y0 Read Write R W After reset 0 0 0 0 0 0 Function Set BANK number for LOCAL Y 3 is disabled because of overlapped with Common area 15 14 13 12 11 10 9 8 bit Symbol LYE Read Write R W After reset 0 Function BANK for LOCALY 0 Disable 1 Enable LOCAL Z register for LCD 7 6 5 4 3 2 1 0 bit Symbol Z7 Z6 Z5 Z4 ...

Page 214: ... 0 Disable 1 Enable Set BANK number for LOCAL X X8 X0 setting and CS 000000000 to 011111111 CSXA 100000000 to 111111111 CSXB LOCAL Y register for read 7 6 5 4 3 2 1 0 bit Symbol Y5 Y4 Y3 Y2 Y1 Y0 Read Write R W After reset 0 0 0 0 0 0 Function Set BANK number for LOCAL Y 3 is disabled because of overlapped with Common area 15 14 13 12 11 10 9 8 bit Symbol LYE Read Write R W After reset 0 Function ...

Page 215: ...sable 1 Enable Set BANK number for LOCAL X X8 X0 setting and CS 000000000 to 011111111 CSXA 100000000 to 111111111 CSXB LOCAL Y register for write 7 6 5 4 3 2 1 0 bit Symbol Y5 Y4 Y3 Y2 Y1 Y0 Read Write R W After reset 0 0 0 0 0 0 Function Set BANK number for LOCAL Y 3 is disabled because of overlapped with Common area 15 14 13 12 11 10 9 8 bit Symbol LYE Read Write R W After reset 0 Function BANK...

Page 216: ... bank controller is 2 type Even channel of DMA channel 0 2 and 4 become E group ES and ED group odd channel of DMA channel 1and 3 become O group OS and OD group Assignment every channel is disable in same group Following shows examples of setting bank for DMA_Source address to 1 in LOCALX area and setting bank for DMA_Destination address to 2 in LOCALY area If Source address which set to XXX by us...

Page 217: ...r reset 0 0 0 0 0 0 Function Set BANK number for LOCAL Y 3 is disabled because of overlapped with Common area 15 14 13 12 11 10 9 8 bit Symbol LYE Read Write R W After reset 0 Function BANK for LOCALY 0 Disable 1 Enable LOCAL Z register for even group DMA source 7 6 5 4 3 2 1 0 bit Symbol Z7 Z6 Z5 Z4 Z3 Z2 Z1 Z0 Read Write R W After reset 0 0 0 0 0 0 0 0 Function Set BANK number for LOCAL Z 3 is d...

Page 218: ...ter reset 0 0 0 0 0 0 Function Set BANK number for LOCAL Y 3 is disabled because of overlapped with Common area 15 14 13 12 11 10 9 8 bit Symbol LYE Read Write R W After reset 0 Function BANK for LOCALY 0 Disable 1 Enable LOCAL Z register for even group DMA destination 7 6 5 4 3 2 1 0 bit Symbol Z7 Z6 Z5 Z4 Z3 Z2 Z1 Z0 Read Write R W After reset 0 0 0 0 0 0 0 0 Function Set BANK number for LOCAL Z...

Page 219: ... reset 0 0 0 0 0 0 Function Set BANK number for LOCAL Y 3 is disabled because of overlapped with Common area 15 14 13 12 11 10 9 8 bit Symbol LYE Read Write R W After reset 0 Function BANK for LOCALY 0 Disable 1 Enable LOCAL Z register for odd group DMA source 7 6 5 4 3 2 1 0 bit Symbol Z7 Z6 Z5 Z4 Z3 Z2 Z1 Z0 Read Write R W After reset 0 0 0 0 0 0 0 0 Function Set BANK number for LOCAL Z 3 is dis...

Page 220: ...ter reset 0 0 0 0 0 0 Function Set BANK number for LOCAL Y 3 is disabled because of overlapped with Common area 15 14 13 12 11 10 9 8 bit Symbol LYE Read Write R W After reset 0 Function BANK for LOCALY 0 Disable 1 Enable LOCAL Z register for odd group DMA destination 7 6 5 4 3 2 1 0 bit Symbol Z7 Z6 Z5 Z4 Z3 Z2 Z1 Z0 Read Write R W After reset 0 0 0 0 0 0 0 0 Function Set BANK number for LOCAL Z ...

Page 221: ...0FFH CS1 400000 7fffff 4MB 5 ldw b1csl 8111H CS1 16bit RAM 0wait 5 1 ldw localpz 8000H Enable LOCAL Z Bank for program 5 2 ldw localrz 8000H Enable LOCAL Z Bank for read data 6 ld p8fc 02H 7 ld p8fc2 04H 9 ld xsp 48000H Stack Pointer 48000H 10 ldw localpy 8000H Bank0 in LOCAL Y is set as Program bank for sub routine 11 C000yyH 12 call 400000H Call Sub routine 13 14 15 From No 2 to No 8 instruction...

Page 222: ...ta from character ROM No 20 and No 21 are instructions to read data from character ROM When CPU outputs 800000H address this MMU will convert and output 000000H address to external address bus A23 to A0 And CSZA for NOR Flash will be asserted because of logical address is in an area for CS2 at the same time By these instructions CPU can read data from character ROM No 23 is an instruction which ch...

Page 223: ...Addressing mode Sequential Sequential Sequential CAS latency clock 2 2 2 Write mode Single Single or burst selectable 4 Access cycles CPU access cycles Read cycle 1 word 4 3 3 3 states minimum Write cycle Single 3 2 2 2 states minimum Data size 1 byte 1 word 1 long word HDMA access cycles Read cycle 1 word 4 3 3 3 states full page 4 1 1 1 states minimum Write cycle Single 3 2 2 2 states minimum bu...

Page 224: ...ing Register 7 6 5 4 3 2 1 0 Bit symbol STMRD STWR STRP STRCD STRC2 STRC1 STRC0 Read Write R W After reset 1 1 1 1 1 0 0 Function TMRD 0 1 CLK 1 2 CLK TWR 0 1 CLK 1 2 CLK TRP 0 1 CLK 1 2 CLK TRCD 0 1 CLK 1 2 CLK TRC 000 1 CLK 100 5 CLK 001 2 CLK 101 6 CLK 010 3 CLK 110 7 CLK 011 4 CLK 111 8 CLK SDRAM Refresh Control Register 7 6 5 4 3 2 1 0 Bit symbol SSAE SRS2 SRS1 SRS0 SRC Read Write R W R W Aft...

Page 225: ...ng the next command make sure that SCMM2 0 is 000 In the case of the Self Refresh Entry command however SCMM2 0 is not cleared to 000 by execution of this command Thus this register can be used as a flag for checking whether or not Self Refresh is being performed Note 2 The Self Refresh Exit command can only be specified while Self Refresh is being performed SDRAM HDMA Burst Length Select Register...

Page 226: ... each SDRAM access cycle generated by each bus master Table 3 10 1 shows the commands that are issued by the SDRAMC Table 3 10 1 Commands Issued by the SDRAMC Command CKEn 1 CKEn SDxxDQM A10 A15 11 A9 0 SDCS SDRAS SDCAS SDWE Bank Activate H H H RA RA L L H H Precharge All H H H H X L L H L Read H H L L CA L H L H Read with Auto Precharge H H L H CA L H L H Write H H L L CA L H L L Write with Auto ...

Page 227: ...A16 A17 A18 A8 A8 A17 A18 A19 A9 A9 A18 A19 A20 A10 A10 A19 A20 A21 AP A11 A20 A21 A22 A12 A21 A22 A23 A13 A22 A23 EA24 A14 A23 EA24 EA25 A15 EA24 EA25 EA26 Row Address AP Auto Precharge c Burst length When the CPU accesses the SDRAM the burst length is fixed to 1 word read single write When the LCDC accesses the SDRAM the burst length is fixed to full page The burst length can be selected for SDR...

Page 228: ...A0 D15 D0 RA Bank Active RA CA n CA n 2 D n Read tRCD 1CLK CAS Latency 2CLK D n 2 CAS Latency 2CLK D n 4 CAS Latency 2CLK 4CLK 3CLK 3CLK Read Read CA n 4 SDCLK SDCKE SDLUDQM SDLLDQM A10 A15 A0 D15 D0 RA Bank Active RA CA n D n Read tRCD 1CLK CAS Latency 2CLK D n 2 4CLK 1CLK D n 4 1CLK Burst Stop D dmy D dmy A10 A15 0 Burst Stop Cycle 2CLK SDCS SDRAS SDCAS SDWE ...

Page 229: ...D0 RA Bank Active RA CA n CA n 2 D n 2 Write tRCD 1CLK 3CLK 2CLK tWR 1CLK D n tWR 1CLK D n 4 tWR 1CLK CA n 4 2CLK Write Write SDCS SDRAS SDCAS SDWE SDCLK SDCKE SDLUDQM SDLLDQM A10 A15 A0 D15 D0 RA Bank Active RA CA n D n 2 Write tRCD 1CLK 2CLK 1CLK D n D n 4 1CLK Burst Stop A10 A15 0 Burst Stop Cycle 2CLK D n 6 D end CA n SDCS SDRAS SDCAS SDWE ...

Page 230: ... the SDRAM to be accessed at optimum cycles even if the operationg frequency is changed by clock gear Command intervals should be set in the SDCISR register according to the operating frequency of the TMP92CZ26A and the AC specifications of the SDRAM The SDCICR register must not be changed while the SDRAM is being accessed The timing waveforms for various cases are shown below a Mode Register Set ...

Page 231: ...LK SDCISR STRCD 1 TRC 6CLK SDCISR STRC2 0 101 READ NOP D15 D0 DIN TRCD ACTIVE A15 A0 Row Address Column Address Row Address Non MUX address NOP SDCLK COMMAND NOP ACTIVE NOP NOP TRC TRCD 2CLK SDCISR STRCD 1 TWR 2CLK SDCISR STWR 1 TRP 2CLK SDCISR STRP 1 TRC 6CLK SDCISR STRC2 0 101 WRITE PRECHARG D15 D0 DOUT TRCD TWR ACTIVE A15 A0 Row Address Column Address Row Address Non MUX address NOP TRP ...

Page 232: ...The timing waveforms for various cases are shown below a 1 word read the read data shift function disabled SDACR SRCS 0 b 1 word read the read data shift function enabled SDACR SRDS 1 SRDSCK 0 CPU data read SDCLK COMMAND ACTIVE NOP NOP READ NOP D15 D0 DIN1 ACTIVE A15 A0 Row Address ColumnAddress Internal system clock Internal dat bus DIN1 Row Address READ Column Address SDCLK COMMAND ACTIVE NOP NO...

Page 233: ...radation in performance as the Bank Active command is needed at every access cycle When SDACR SPRE is set to 0 the Read Write commands are executed without Auto Precharge In this case the SDRAM is not precharged at every access cycle and is always in a bank active state This increases the power consumption of the SDRAM but improves performance as there is no need to issue the Bank Active command a...

Page 234: ... The Auto Refresh function cannot be used in IDLE1 and STOP modes In these modes use the Self Refresh function to be explained next Note A system reset disables the Auto Refresh function Figure3 10 6 Auto Refresh Cycle Timing Table3 10 3 Auto Refresh Intervals Unit μs SDRCR SRS2 0 Frequency System Clock SRS2 SRS1 SRS0 Auto Refresh Interval states 6 MHz 10 MHz 20 MHz 40 MHz 60 MHz 80 MHz 0 0 0 47 7...

Page 235: ... are initialized and the Self Refresh state is exited Note that the Auto Refresh function is also disabled at this time Note 2 The SDRAM cannot be accessed while it is in the Self Refresh state Note 3 To execute the HALT instruction after the Self Refresh Entry command insert at least 10 bytes of NOP or other instructions between the instruction to set SDCMM SCMM2 0 to 101 and the HALT instruction...

Page 236: ...RCR SSAE to 0 disables automatic execution of the Self Refresh Exit command in synchronization with HALT release The auto exit function should also be disabled in cases where the SDRAM operation requirements cannot be met as the operation clock frequency is reduced by clock gear down as shown in Figure3 10 8 Figure3 10 8 Execution Flow for Executing HALT Instruction after Clock Gear Down HALT mode...

Page 237: ...CPU operation instruction fetch execution is halted Before executing the initialization sequence appropriate port settings must be made to enable the SDRAM control signals and address signals A0 to A15 After the initialization sequence is completed SDCMM SCMM2 0 is automatically cleared to 000 Figure3 10 9 Initialization Sequence Timing SDCLK SDCKE SDLUDQM SDLLDQM A10 A15 A0 Precharge All Eight Au...

Page 238: ... A10 A10 A10 A11 BS A11 A11 A11 A11 A12 BS0 BS0 A12 A12 A13 BS1 BS1 BS0 BS0 A14 BS1 BS1 A15 SDCS CS CS CS CS CS SDLUDQM UDQM UDQM UDQM UDQM UDQM SDLLDQM LDQM LDQM LDQM LDQM LDQM SDRAS RAS RAS RAS RAS RAS SDCAS CAS CAS CAS CAS CAS SDWE WE WE WE WE WE SDCKE CKE CKE CKE CKE CKE SDCLK CLK CLK CLK CLK CLK SDACR SMUXW 00 TypeA 00 TypeA 01 TypeB 01 TypeB 10 TypeC Command address pin of SDRAM Figure3 10 1...

Page 239: ... bytes Calculation example Transfer time SDRAM read time SRAM write time transfer count SDRAM burst start stop time Precharge time Auto Refresh time Auto Refresh count a Read write time SDRAM read 1 state 2 Internal RAM write 1 state 512 bytes 4 bytes 384 states 1 60 MHz 6 4 μs b Burst start stop time Start TRCD 2CLK 5 states Stop 2 states 7states 60 MHz 0 117 μs c Auto Refresh time Based on the a...

Page 240: ... Therefore to execute the HALT instruction after one of these commands be sure to insert at least 10 bytes of NOP or other instructions 3 Auto Refresh interval setting When SDRAM is used the system clock frequency must be set to satisfy the minimum operation frequency and minimum Auto Refresh interval of the SDRAM to be used In a system in which SDRAM is used and the clock is geared up and down th...

Page 241: ...ytes Although the NDFC has two channels channel 0 channel 1 all pins except for Chip Enable are shared between the two channels Only the operation of channel 0 is explained here The NDFC has the following features 1 Controls the NAND Flash memory interface through registers 2 Supports 8 bit and 16 bit NAND Flash memory devices 3 Supports page sizes of 512 bytes and 2048 bytes 4 Supports large capa...

Page 242: ..._ALE ND_CLE ND WE ND_RB DATA_IN 15 0 NAND Flash Controller Channel 0 NDFC0 DATA_OUT 15 0 NDCLE NDALE NDRE NDWE D15 D0 D15 D0 NDR B CE 0 ND Internal Data Bus Reed Solomon ECC Generator Hamming ECC Generator Reed Solomon ECC Calculator Timing Generator Control Register Address Data F F 80 bit ECC Code RS ECC Write ...

Page 243: ... section explains the operations for accessing the NAND Flash Since no dedicated sequencer is provided for generating commands to the NAND Flash the levels of the NDCLE NDALE and NDCE pins must be controlled by software Figure 3 11 2 Basic Timing for Accessing NAND Flash NDCLE NDALE NDCE NDRE NDR B D15 D0 ND0FMCR ALE 0 NDFMCR0 CLE 0 NDFMCR0 ALE 1 NDFMCR0 CLE 1 NDFMCR0 CE0 1 NDWE ...

Page 244: ...ng speed fSYS and the access time of the NAND Flash For details refer to the electrical characteristics The following shows an example of accessing the NAND Flash in 6 clocks by setting NDFMCR0 SPLW1 0 2 and NDFMCR0 SPHW1 0 2 In write cycles the data drive time also becomes longer Figure 3 11 3 Read Write Access to NAND Flash FF1234H IN Program 001FF0H FF1238H IN Program OUT NAND Flash Program Mem...

Page 245: ... The ECC is written to the redundant area in the NAND Flash separately from the valid data Read 1 When data is read from the actual NAND Flash memory the ECC generator in the NDFC simultaneously generates ECC for the read data 2 The ECC for the written data and the ECC for the read data are compared to detect and correct error bits Valid data write to NAND Flash END Data Write Data Read Valid data...

Page 246: ...ry 518 bytes When using Reed Solomon codes error bit detection calculation is supported by hardware and only error bit correction needs to be implemented by software The differences between Hamming codes and Reed Solomon codes are summarized in Table 3 11 1 Table 3 11 1 Differences between Hamming Codes and Reed Solomon Codes Hamming Reed Solomon Maximum number of correctable errors 1 bit 4 addres...

Page 247: ... error exists in the ECC data itself and the error correction process terminates here error not correctable 5 If each pair of bits 0 to 21 of the XOR result is either 01B or 10B it is determined that the error data is correctable and error correction is performed accordingly If the XOR result contains either 00B or 11B it is determined that the error data is not correctable and the error correctio...

Page 248: ...e of 008H to 20DH the actual error address is obtained by subtracting this address from 20 DH If the valid data is processed as 512 byte the actual error address is obtained by subtracting this address from 207H when the error address in the range of 008H to 207H Example 1 NDRSCAn 005H NDRSCDn 04H 00000100B As the error address 005H is in the range of 000H to 007H no correction is needed Although ...

Page 249: ...as 0 Reed Solomon ECC generator write control 0 Disable 1 Enable Figure 3 11 5 NAND Flash Mode Control 0 Register a ECCRST The ECCRST bit is used for both Hamming and Reed Solomon codes When NDFMCR1 ECCS 0 setting this bit to 1 clears the Hamming ECC in the ECC generator When NDFMCR1 ECCS 1 setting this bit to 1 clears the Reed Solomon ECC Note that this bit is ineffective when NDFMCR0 ECCE 0 Befo...

Page 250: ...by DMA transfer After valid data has been read DMA transfer should be stopped once to change the RSECGW bit from 0 to 1 before ECC can be read Note 2 Immediately after ECC is read from the NAND Flash the NAND Flash access operation or error bit calculation cannot be performed for a duration of 20 system clocks fSYS It is necessary to insert 20 NOP instructions or the like g RSESTA The RSESTA bit i...

Page 251: ...e is latched so that the ECC generator can generate the ECC for another page without problem while the ECC calculator is calculating the error address and error bit position At this time the ECC generator can perform both encode write and decode read operations When RSECCL is set to 0 the latch is released and the contents of the ECC calculator are updated as the data in the ECC generator is updat...

Page 252: ...alue becomes effective after the calculation has started SEER 1 0 Meaning 00 1 address error 01 2 address error 10 3 address error 11 4 address error Note The SEER1 0 value becomes effective after the calculation has ended a SYSCKE The SYSCKE bit is used for both Hamming and Reed Solomon codes When using the NDFC this bit must be set to 1 to enable the system clock When not using the NDFC power co...

Page 253: ... Solomon codes This bit is used to enable or disable the interrupt to be generated when the status of the NDR B pin of the NAND Flash changes from busy 0 to ready 1 The interrupt is enabled when this bit is set to 1 and disabled when 0 f STATE3 0 SEER1 0 The STATE3 0 and SEER1 0 bits are used only for Reed Solomon codes When using Hamming codes they have no meaning These bits are used as flags to ...

Page 254: ...ite operations no flip flop is incorporated Since write and read operations are performed in different manners it is not possible to read out the data that has been just written Figure 3 11 6 NAND Flash Data Registers NDFDTR0 NDFDTR1 Write and read operations to and from the NAND Flash memory are performed by accessing the NDFDTR0 register When you write to this register the data is written to the...

Page 255: ...te access ld 0x1FF0 a Supported Not supported 2 byte access ld 0x1FF0 wa Supported Supported 4 byte access ld 0x1FF0 xwa Supported Supported Read Access Data Size Example of instruction 8 bit NAND Flash 16 bit NAND Flash 1 byte access ld a 0x1FF0 Supported Not supported 2 byte access ld wa 0x1FF0 Supported Supported 4 byte access ld xwa 0x1FF0 Supported Supported ...

Page 256: ...0 0 0 0 0 Function NAND Flash ECC Register 7 0 15 14 13 12 11 10 9 8 bit Symbol ECCD15 ECCD14 ECCD13 ECCD12 ECCD11 ECCD10 ECCD9 ECCD8 Read Write R After reset 0 0 0 0 0 0 0 0 Function NAND Flash ECC Register 15 8 NAND Flash ECC Register 3 7 6 5 4 3 2 1 0 bit Symbol ECCD7 ECCD6 ECCD5 ECCD4 ECCD3 ECCD2 ECCD1 ECCD0 Read Write R After reset 0 0 0 0 0 0 0 0 Function NAND Flash ECC Register 7 0 15 14 13...

Page 257: ... 0 The ECC in the NAND Flash ECC register is updated when NDFMCR0 ECCE changes from 1 to 0 Also note that when the ECC in the ECC generator is reset by NDFMCR0 ECCRST the contents of this register are not reset Register Name Hamming Reed Solomon NDECCRD0 15 0 Line parity for the first 256 bytes 15 0 Reed Solomon ECC code 79 64 NDECCRD1 7 2 Column parity for the first 256 bytes 15 0 Reed Solomon EC...

Page 258: ...n NAND Flash Reed Solomon Calculation Result Address Register 9 8 7 6 5 4 3 2 1 0 bit Symbol RS2A7 RS2A6 RS2A5 RS2A4 RS2A3 RS2A2 RS2A1 RS2A0 Read Write R After reset 0 0 0 0 0 0 0 0 Function NAND Flash Reed Solomon Calculation Result Address Register 7 0 15 14 13 12 11 10 9 8 bit Symbol RS2A9 RS2A8 Read Write R After reset 0 0 Function NAND Flash Reed Solomon Calculation Result Address Register 9 ...

Page 259: ...0 0 0 Function NAND Flash Reed Solomon Calculation Result Data Register 7 0 7 6 5 4 3 2 1 0 bit Symbol RS2D7 RS2D6 RS2D5 RS2D4 RS2D3 RS2D2 RS2D1 RS2D0 Read Write R After reset 0 0 0 0 0 0 0 0 Function NAND Flash Reed Solomon Calculation Result Data Register 7 0 7 6 5 4 3 2 1 0 bit Symbol RS3D7 RS3D6 RS3D5 RS3D4 RS3D3 RS3D2 RS3D1 RS3D0 Read Write R After reset 0 0 0 0 0 0 0 0 Function NAND Flash Re...

Page 260: ...able ldw xxxx ndeccrd0 Read ECC from internal circuit 1 st Read D15 0 LPR15 0 For first 256 bytes ldw xxxx ndeccrd1 Read ECC from internal circuit 2 nd Read D15 0 FFh CPR5 0 11b For first 256 bytes ldw xxxx ndeccrd0 Read ECC from internal circuit 3 rd Read D15 0 LPR15 0 For second 256 bytes ldw xxxx ndeccrd1 Read ECC from internal circuit 4 th Read D15 0 FFh CPR5 0 11b For second 256 bytes Writing...

Page 261: ...d ndfdtr0 10h Auto page program command ldw ndfmcr0 2010h WE disable CLE disable Wait setup time from Busy to Ready 1 Flag polling 2 Interrupt Reading status Read Status ldw ndfmcr0 20B0h WE enable CLE enable ld ndfdtr0 70h Status read command ldw ndfmcr0 2010h WE disable CLE disable ld xx ndfdtr0 Status read ...

Page 262: ...ECC data read 3 times Generating ECC Reading ECC Read ECC ldw ndfmcr0 2010h ECC circuit disable ldw xxxx ndeccrd0 Read ECC from internal circuit 1 st Read D15 0 LPR15 0 For first 256 bytes ldw xxxx ndeccrd1 Read ECC from internal circuit 2 nd Read D15 0 FFh CPR5 0 11b For first 256 bytes ldw xxxx ndeccrd0 Read ECC from internal circuit 3 rd Read D15 0 LPR15 0 For second 256 bytes ldw xxxx ndeccrd1...

Page 263: ...lows ldw ndfmcr0 20B0h WE Enable CLE enable ld ndfdtr0 90h Write ID read command ldw ndfmcr0 20D0h ALE enable CLE disable ld ndfdtr0 00h Write 00 ldw ndfmcr0 2010h WE disable CLE disable ld xx ndfdtr0 Read 1 st ID maker code ld xx ndfdtr0 Read 2 nd ID device code ...

Page 264: ...nable ldw ndfdtr0 00xxh Address write 4 or 5 times ldw ndfmcr0 508Dh Reset ECC code ECCE enable ldw ndfdtr0 xxxxh Data write 259 times 518byte 256 times 512byte Generating ECC Reading ECC Read ECC ldw ndfmcr0 5008h ECC circuit disable ldw ndfmcr0 50A8h WE enable CLE enable ldw ndfdtr0 0080h serial input command ldw ndfmcr0 50C8h ALE enable ldw ndfdtr0 00xxh Address write 4 or 5 times ldw xxxx ndec...

Page 265: ... 20Ehex address D15 0 The write operation is repeated four times to write 2112 bytes Executing page program Set auto page program ldw ndfmcr0 50A8h WE enable CLE enable ldw ndfdtr0 0010h Auto page program command ldw ndfmcr0 5008h WE disable CLE disable Wait set up time from Busy to Ready 1 Flag polling 2 Interrupt In case of LB type NANDF programming page size is normally each 2112 bytes and ECC ...

Page 266: ...ode mode ldw xxxx ndfdtr0 Data read 259 times 518 bytes 256 times 512byte ldw ndfmcr0 550Ch RSECGW enable ldw xxxx ndfdtr0 Read ECC 5 times 80 bits Wait set up time 20 system clocks 1 Error bit calculation ldw ndfmcr1 0047h Error bit calculation interrupt enable ldw ndfmcr0 560Ch Error bit calculation circuit start Wait set up time Interrupt routine End of calculation for Reed Solomon Error bit IN...

Page 267: ...ldw ndfmcr0 50A8h WE enable CLE enable ldw ndfdtr0 0090h Write ID read command ldw ndfmcr0 50C8h ALE enable CLE disable ldw ndfdtr0 0000h Write 00 ldw ndfmcr0 5008h WE disable CLE disable ldw xxxx ndfdtr0 Read 1 st ID maker code ldw xxxx ndfdtr1 Read 2 ndID device code ...

Page 268: ...sh memory to be used and the capacity of the board typical 2 KΩ Note 3 The WP Write Protect pin of NAND Flash is not supported When this function is needed prepare it on an external circuit Figure 3 11 10 An Example of Connections with NAND Flash NDCLE NDALE NDRE NDWE NDR B D 15 0 CE 0 ND CE 1 ND TMP92CZ26A CLE ALE RE WE R B open drain I O 15 0 CE WP NAND Flash 0 CLE ALE RE WE R B open drain I O 7...

Page 269: ...flip flops are controlled by 5bytes registers SFRs Special function registers Each of the 4 modules TMRA01 to TMRA67 can be operated independently All modules operate in the same manner hence only the operation of TMRA01 is explained here The contents of this chapter are as follows Table 3 12 1 Registers and Pins for Each Module Module Specification TMRA01 TMRA23 TMRA45 TMRA67 Input pin for extern...

Page 270: ... 512 256 128 64 32 16 8 4 2 φT1 φT4 φT16 φT256 Run clear Prescaler TA01MOD TA0CLK1 0 Prescaler clock φT0TMR TA01RUN TA0RUN Selector 8 bit timer register TA0REG TA01MOD PWM01 00 TA01MOD TA01M1 0 TMRA0 Interrupt output INTTA0 TMRA0 Interrupt output TA0TRG TA01MOD TA1CLK1 0 TA01RUN TA1RUN TA1FFCR Timer flip flop output TA1OUT TMRA1 Interrupt output INTTA1 Internaldata bus TA01RUN TA0RDE TA01RUN TA01P...

Page 271: ...28 64 32 16 8 4 2 φT1 φT4 φT16 φT256 Run clear Prescaler TA23MOD TA2CLK1 0 Prescaler clock φT0TMR TA23RUN TA2RUN Selector 8 bit timer register TA2REG TA23MOD PWM21 20 TA23MOD TA23M1 0 TMRA2 Interrupt output INTTA2 TMRA2 Interrupt output TA2TRG TA23MOD TA3CLK1 0 TA23RUN TA3RUN TA3FFCR Timer flip flop output TA3OUT TMRA3 Interrupt output INTTA3 Internal data bus TA23RUN TA2RDE TA23RUN TA23PRUN Selec...

Page 272: ... 128 64 32 16 8 4 2 φT1 φT4 φT16 φT256 Run clear Prescaler TA45MOD TA4CLK1 0 Prescaler clock φT0TMR TA45RUN TA4RUN Selector 8 bit timer register TA4REG TA45MOD PWM41 40 TA45MOD TA45M1 0 TMRA4 Interrupt output INTTA4 TMRA4 Interrupt output TA4TRG TA45MOD TA5CLK1 0 TA45RUN TA5RUN TA5FFCR Timer flip flop output TA5OUT TMRA5 Interrupt output INTTA5 Internal data bus TA45RUN TA4RDE TA45RUN TA45PRUN Sel...

Page 273: ... 128 64 32 16 8 4 2 φT1 φT4 φT16 φT256 Run clear Prescaler TA67MOD TA6CLK1 0 Prescaler clock φT0TMR TA67RUN TA6RUN Selector 8 bit timer register TA6REG TA67MOD PWM61 60 TA67MOD TA67M1 0 TMRA6 Interrupt output INTTA6 TMRA6 Interrupt output TA6TRG TA67MOD TA7CLK1 0 TA67RUN TA7RUN TA7FFCR Timer flip flop output TA7OUT TMRA7 Interrupt output INTTA7 Internal data bus TA67RUN TA6RDE TA67RUN TA67PRUN Sel...

Page 274: ... 32768 000 1 1 fc 32 fc 128 fc 512 fc 8192 001 1 2 fc 64 fc 256 fc 1024 fc 16384 010 1 4 fc 128 fc 512 fc 2048 fc 32768 011 1 8 fc 256 fc 1024 fc 4096 fc 65536 fc 100 1 16 1 1 8 1 2 fc 512 fc 2048 fc 8192 fc 131072 2 Up counters UC0 and UC1 These are 8 bit binary counters which count up the input clock pulses for the clock specified by TA01MOD The input clock for UC0 is selectable and can be eithe...

Page 275: ...erflow occurs in PWM mode or at the start of the PPG cycle in PPG mode Hence the double buffer cannot be used in timer mode When using the double buffer method of renewing timer register is only overflow in PWM mode or frequency agreement in PPG mode A reset initializes TA0RDE to 0 disabling the double buffer To use the double buffer write data to the timer register set TA0RDE to 1 and write the f...

Page 276: ...ng 00 to these bits inverts the value of TA1FF This is known as software inversion The TA1FF signal is output via the TA1OUT pin When this pin is used as the timer output the timer flip flop should be set beforehand using the port function registers The condition for TA1FF inversion varies with mode as shown below 8 bit interval timer mode UC0 matches TA0REG or UC1 matches TA1REG Select either one...

Page 277: ...RUN Register 7 6 5 4 3 2 1 0 Bit symbol TA2RDE I2TA23 TA23PRUN TA3RUN TA2RUN Read Write R W R W After Reset 0 0 0 0 0 TMRA23 prescaler Up counter UC3 Up counter UC2 Function Double buffer 0 Disable 1 Enable In IDLE2 mode 0 Stop 1 Operate 0 Stop and clear 1 Run Count up Note The values of bits 4 to 6 of TA23RUN are 1 when read Figure 3 12 6 Register for TMRA 1 TA01RUN 1100H TA0REG double buffer con...

Page 278: ...gister 7 6 5 4 3 2 1 0 Bit symbol TA6RDE I2TA67 TA67PRUN TA7RUN TA6RUN Read Write R W R W After Reset 0 0 0 0 0 TMRA67 prescaler Up counter UC7 Up counter UC6 Function Double buffer 0 Disable 1 Enable In IDLE2 mode 0 Stop 1 Operate 0 Stop and clear 1 Run Count up Note The values of bits 4 to 6 of TA67RUN are 1 when read Figure 3 12 7 Register for TMRA 2 TA45RUN 1110H TA4REG double buffer control 0...

Page 279: ... Source clock for TMRA0 00 TA0IN pin 01 φT1 10 φT4 11 φT16 00 TA0IN External input 01 φT1 10 φT4 TA0CLK1 0 11 φT16 TA01MOD TA01M1 0 01 TA01MOD TA01M1 0 01 00 Comparator output from TMRA0 01 φT1 10 φT16 TA1CLK1 0 11 φT256 Overflow output from TMRA0 16 bit timer mode 00 Reserved 01 2 6 Clock source 10 2 7 Clock source PWM01 00 11 2 8 Clock source 00 8 timer 2ch 01 16 bit timer 10 8 bit PPG TA01MA1 0...

Page 280: ... TMRA2 clock for TMRA2 00 TA2IN pin 01 φT1 10 φT4 11 φT16 00 TA2IN External input 01 φT1 10 φT4 TA2CLK1 0 11 φT16 TA23MOD TA23M1 0 01 TA23MOD TA23M1 0 01 00 Comparator output from TMRA2 01 φT1 10 φT16 TA3CLK1 0 11 φT256 Overflow output from TMRA2 16 bit timer mode 00 Reserved 01 2 6 Clock source 10 2 7 Clock source PWM21 20 11 2 8 Clock source 00 8 timer 2ch 01 16 bit timer 10 8 bit PPG TA23MA1 0 ...

Page 281: ... clock for TMRA4 00 low frequency clock 01 φT1 10 φT4 11 φT16 00 low frequency clock fs 01 φT1 10 φT4 TA4CLK1 0 11 φT16 TA45MOD TA45M1 0 01 TA45MOD TA45M1 0 01 00 Comparator output from TMRA4 01 φT1 10 φT16 TA5CLK1 0 11 φT256 Overflow output from TMRA4 16 bit timer mode 00 Reserved 01 2 6 Clock source 10 2 7 Clock source PWM41 40 11 2 8 Clock source 00 8 timer 2ch 01 16 bit timer 10 8 bit PPG TA45...

Page 282: ... clock for TMRA6 00 low frequency clock 01 φT1 10 φT4 11 φT16 00 low frequency clock fs 01 φT1 10 φT4 TA6CLK1 0 11 φT16 TA67MOD TA67M1 0 01 TA67MOD TA67M1 0 01 00 Comparator output from TMRA6 01 φT1 10 φT16 TA7CLK1 0 11 φT256 Overflow output from TMRA6 16 bit timer mode 00 Reserved 01 2 6 Clock source 10 2 7 Clock source PWM61 60 11 2 8 Clock source 00 8 timer 2ch 01 16 bit timer 10 8 bit PPG TA67...

Page 283: ...select 0 TMRA0 1 TMRA1 0 Inversion by TMRA0 TA1FFIS 1 Inversion by TMRA1 0 Disabled TA1FFIE 1 Enabled 00 Inverts the value of TA1FF Software inversion 01 Sets TA1FF to 1 10 Clears TA1FF to 0 TA1FFC1 0 11 Don t care Note The values of bits 4 to 6 of TA1FFCR are 1 when read Figure 3 12 12 Register for TMRA 8 TA1FFCR 1105H Read modify write instructions are prohibited Control of TA1FF Inversion signa...

Page 284: ...select 0 TMRA2 1 TMRA3 0 Inversion by TMRA2 TA3FFIS 1 Inversion by TMRA3 0 Disabled TA3FFIE 1 Enabled 00 Inverts the value of TA3FF Software inversion 01 Sets TA3FF to 1 10 Clears TA3FF to 0 TA3FFC1 0 11 Don t care Note The values of bits 4 to 6 of TA3FFCR are 1 when read Figure 3 12 13 Register for TMRA 9 TA3FFCR 110DH Read modify write instructions are prohibited Control of TA3FF Inversion signa...

Page 285: ...elect 0 TMRA4 1 TMRA5 0 Inversion by TMRA4 TA5FFIS 1 Inversion by TMRA5 0 Disabled TA5FFIE 1 Enabled 00 Inverts the value of TA5FF Software inversion 01 Sets TA5FF to 1 10 Clears TA5FF to 0 TA5FFC1 0 11 Don t care Note The values of bits 4 to 6 of TA5FFCR are 1 when read Figure 3 12 14 Register for TMRA 10 TA5FFCR 1115H Read modify write instructions are prohibited Control of TA5FF Inversion signa...

Page 286: ...elect 0 TMRA6 1 TMRA7 0 Inversion by TMRA6 TA7FFIS 1 Inversion by TMRA7 0 Disabled TA7FFIE 1 Enabled 00 Inverts the value of TA7FF Software inversion 01 Sets TA7FF to 1 10 Clears TA7FF to 0 TA7FFC1 0 11 Don t care Note The values of bits 4 to 6 of TA7FFCR are 1 when read Figure 3 12 15 Register for TMRA 11 TA7FFCR 111DH Read modify write instructions are prohibited Control of TA7FF Inversion signa...

Page 287: ...r reset 0 0 0 0 0 0 0 0 bit Symbol Read Write W After reset 0 0 0 0 0 0 0 0 bit Symbol Read Write W After reset 0 0 0 0 0 0 0 0 bit Symbol Read Write W After reset 0 0 0 0 0 0 0 0 bit Symbol Read Write W After reset 0 0 0 0 0 0 0 0 Note All registers are prohibited to execute read modify write instruction Figure 3 12 16 TMRA Registers TA0REG 1102H TA1REG 1103H TA2REG 110AH TA3REG 110BH TA4REG 1112...

Page 288: ...TTA1 interrupt every 20 us at fc 50 MHz set each register as follows Clock state Clcok gear 1 1 Prescaler of clock gear 1 2 MSB LSB 7 6 5 4 3 2 1 0 TA01RUN X X X 0 Stop TMRA1 and clear it to 0 TA01MOD 0 0 X X 0 1 X X Select 8 bit timer mode and select φT1 0 16 μs at fC 50 MHz as the input clock TA1REG 0 1 1 1 1 1 0 1 Set TA1REG to 20 μs φT1 125 7DH INTETA1 X 1 0 1 X Enable INTTA1 and set it to lev...

Page 289: ...0 TA01RUN X X X 0 Stop TMRA1 and clear it to 0 TA01MOD 0 0 X X 0 1 X X Select 8 bit timer mode and select φT1 0 16 μs at fC 50 MHz as the input clock TA1REG 0 0 0 0 1 0 1 0 Set the timer register to 3 2 μs φT1 2 0AH TA1FFCR X X X X 1 0 1 1 Clear TA1FF to 0 and set it to invert on the match detect signal from TMRA1 PM X X X X 0 X PMFC X X X X 1 X Set PM1 to function as the TA1OUT pin TA01RUN X X X ...

Page 290: ...om TMRA0 is used as the input clock for TMRA1 regardless of the value set in TA01MOD TA01CLK1 0 Table 3 12 2shows the relationship between the timer Interrupt cycle and the input clock selection Example To generate an INTTA1 interrupt every 0 13 s at fSYS 50 MHz set the timer registers TA0REG and TA1REG as follows Clock state Clcok gear 1 1 Prescaler of clock gear 1 2 If φT16 2 6 μs at fSYS 50 MHz...

Page 291: ...F is inverted Example When TA1REG 04H and TA0REG 80H Figure 3 12 19 Timer Output by 16 Bit Timer Mode 3 8 bit PPG Programmable pulse generation output mode Square wave pulses can be generated at any frequency and duty ratio by TMRA0 The output pulses may be active low or active high In this mode TMRA1 cannot be used TMRA0 outputs pulses on the TA1OUT pin Figure 3 12 20 8 Bit PPG Output Waveforms I...

Page 292: ... be shifted into TA0REG each time TA1REG matches UC0 Use of the double buffer facilitates the handling of low duty waves when duty is varied Figure 3 12 22 Operation of Register Buffer Note The values that can be set in TAxREG renge from 01h to 00h equivalent to 100h If the maximum value 00h is set the match detect signal goes active when the up counter overfolws 8 bit up counter UC0 Comparator Co...

Page 293: ... is to be set to 1 4 t 1 4 32 μs 1 4 8 μs 8 μs 0 16 μs 50 Therefore set TA0REG 50 32H 7 6 5 4 3 2 1 0 TA01RUN X X X 0 0 Stop TMRA0 and TMRA1 and clear it to 0 TA01MOD 1 0 X X X X 0 1 Set the 8 bit PPG mode and select φT1 as input clock TA0REG 0 0 0 0 1 0 1 0 Write 32H TA1REG 1 1 0 0 1 0 0 0 Write C8H TA1FFCR X X X X 0 1 1 X Set TA1FF enabling both inversion and the double buffer Writing 10 provide...

Page 294: ...r UC0 is cleared when 2n counter overflow occurs The following conditions must be satisfied before this PWM mode can be used Value set in TA0REG Value set for 2n counter overflow Value set in TA0REG 0 Figure 3 12 23 8 Bit PWM Waveforms Figure 3 12 24 shows a block diagram representing this mode Figure 3 12 24 Block Diagram of 8 Bit PWM Mode Selector 8 bit up counter UC0 Comparator TA0IN φT1 φT4 φT...

Page 295: ...s 16 0 μs when φT1 0 16 μs set the following value for TAREG 16 0 μs 0 16 μs 100 64H Clock state Clcok gear 1 1 Prescaler of clock gear 1 2 MSB LSB 7 6 5 4 3 2 1 0 TA01RUN X X X 0 Stop TMRA0 and clear it to 0 TA01MOD 1 1 1 0 X X 0 1 Select 8 bit PWM mode cycle 2 7 and select φT1 as the input clock TA0REG 0 1 1 0 0 1 0 0 Write 64H TA1FFCR X X X X 1 0 1 X Clear TA1FF to 0 enable the inversion and do...

Page 296: ...16384 fc 65536 fc 262144 fc 010 x4 8192 fc 32768 fc 131072 fc 16384 fc 65536 fc 262144 fc 32768 fc 131072 fc 524288 fc 011 x8 16384 fc 65536 fc 262144 fc 32768 fc 131072 fc 524288 fc 65536 fc 262144 fc 1048576 fc 1 fc 100 x16 1 x8 x2 32768 fc 131072 fc 524288 fc 65536 fc 262144 fc 1048576 fc 131072 fc 524288 fc 2097152 fc 5 Settings for each mode Table 3 12 4 shows the SFR settings for each mode T...

Page 297: ...te control SFR Each channel TMRB0 TMRB1 operate independently In this section the explanation describes only for TMRB0 because each channel is identical operation except for the difference as follows Table 3 13 1 Difference between TMRB0 and TMRB1 Channel Specification TMRB0 TMRB1 External clock capture trigger input pins TB0IN0 Shared with PP4 TB1IN0 Shared with PP5 External pins Timer flip flop ...

Page 298: ...ister TB0RG1H L TB0MOD TB0CP0I 16 bit comparator CP11 Capture external interrupt input control TB0RUN TB0RUN Caputure register 1 TB0CP1H L Capture register 0 TB0CP0H L Run clear Internal data bus Match detection 16 bit up counter UC10 Count clock from TMRA01 Prescaler clock φT0TMR 32 16 8 4 2 φT1 φT4 φT16 TB0RUN TB0PRUN Internal data bus TB0MOD TB0CLE Intenal data bus Timer flip flop Timer flip fl...

Page 299: ...1H L TB1MOD TB1CP0I 16 bit comparator CP13 Capture external interrupt input control TB1RUN TB1RUN Caputure register 1 TB1CP1H L Capture register 0 TB1CP0H L Run clear Internal data bus Match detection 16 bit up counter UC12 Count clock from TMRA01 Prescaler clock φT0TMR 32 16 8 4 2 φT1 φT4 φT16 TB1RUN TB1PRUN Internal data bus TB1MOD TB1CLE Intenal data bus Timer flip flop Timer flip flop output I...

Page 300: ... fc 16 fc 64 fc 256 1 4 fc 32 fc 128 fc 512 1 8 fc 64 fc 256 fc 1024 1 16 1 2 fc 128 fc 512 fc 2048 1 1 fc 32 fc 128 fc 512 1 2 fc 64 fc 256 fc 1024 1 4 fc 128 fc 512 fc 2048 1 8 fc 256 fc 1024 fc 4096 fc 1 16 1 8 1 2 fc 512 fc 2048 fc 8192 2 Up counter UC10 UC10 is a 16 bit binary counter which counts up pulses input from the clock specified by TB0MOD TB0CLK1 0 Any one of the prescaler internal c...

Page 301: ...itten in the register buffer regardless of the register buffer to the timer register unexpectedly as explained below For example let us assume that an interrupt occurs when only the lower 8 bits L1 of the register buffer data H1L1 have been written and the interrupt routine includes writes to all 16 bits in the register buffer and a transfer of the data to the timer register In this case if the hi...

Page 302: ...lue is written to the register buffer 10 only The addresses of the timer registers are as follows Upper 8 bits TB0RG0H Lower 8 bits TB0RG0L TB0RG0H L 1189H 1188H Upper 8 bits TB0RG1H Lower 8 bits TB0RG1L TB0RG1 H L 118BH 118AH TMRB0 Upper 8 bits TB1RG0H Lower 8 bits TB1RG0L TB1RG0 H L 1199H 1198H Upper 8 bits TB1RG1H Lower 8 bits TB1RG1L TB1RG1 H L 119BH 119AH TMRB1 The timer registers are write o...

Page 303: ...of up counter UC10 into TB0CP0H L and TB0CP1H L and generates external interrupt The latch timing of capture register and selection of edge for external interrupt is controlled by TB0MOD TB0CPM1 0 The value in the up counter UC10 can be loaded into a capture register by software Whenever 0 is written to TB0MOD TB0CP0I the current value in the up counter UC10 is loaded into capture register TB0CP0H...

Page 304: ... match detect signal and a setting change via the TB0FFCR register occurs simultaneously the resultant operation varies depending on the situation as shown below If an inversion by the match detect signal and an inversion via the register occur simultaneously the flip flop will be inverted only once If an inversion by the match detect siganl and an attempt to set the flip flop to 1 via the registe...

Page 305: ...f TB0RUN are read as 1 value TMRB1 RUN Register 7 6 5 4 3 2 1 0 Bit symbol TB1RDE I2TB1 TB1PRUN TB1RUN Read Write R W R W R W R W R W After Reset 0 0 0 0 0 TMRB1 prescaler Up counter UC12 Function Double buffer 0 disable 1 enable Always write 0 In IDLE2 mode 0 Stop 1 Operate 0 Stop and clear 1 Run Count up Note The 1 4 and 5 of TB1RUN are read as 1 value Figure 3 13 3 Register for TMRB 1 Count ope...

Page 306: ... TMRB 2 TMRB0 source clock 00 TB0IN0 pin input 01 φT1 10 φT4 TB0CLK1 0 11 φT16 Control clearing for up counter UC10 0 Disable TB0CLE 1 Enable clearing by match with TB0RG1 Capture interrupt timing Capture control INT6 control 00 Disable 01 Capture to TB0CP0H L at rising edge of TB0IN0 INT6 occurs at the rising edge of TB0IN0 10 Capture to TB0CP0H L at rising edge of TB0IN0 Capture to TB0CP1H L at ...

Page 307: ...r UC12 0 Disable TB1CLE 1 Enable clearing by match with TB1RG1H L Figure 3 13 5 Register for TMRB 3 TMRB1 source clock 00 TB1IN0 pin input 01 φT1 10 φT4 TB1CLK1 0 11 φT16 Capture interrupt timing Capture control INT7 control 00 Disable 01 Capture to TB1CP0H L at rising edge of TB1IN0 INT7 occurs at the rising edge of TB1IN0 10 Capture to TB1CP0H L at rising edge of TB1IN0 Capture to TB1CP1H L at f...

Page 308: ...efined Always read as 11 Timer flip flop control TB0FF0 00 Invert 01 Set to 11 10 Clear to 00 TB0FF0C1 0 11 Undefined Always read as 11 Figure 3 13 6 Register for TMRB 4 TB0FF0 control Inverted when UC10 value matches the valued in TB0RG0H L 0 Disable trigger TB0E0T1 1 Enable trigger TB0FF0 control Inverted when UC10 value matches the valued in TB0RG1H L 0 Disable trigger TB0E1T1 1 Enable trigger ...

Page 309: ...r 11 Don t care Always read as 11 Figure 3 13 7 Register for TMRB 5 Timer flip flop control TB1FF0 00 Invert 01 Set to 11 10 Clear to 00 TB1FF0C1 0 11 Don t care TB1FF0 control Inverted when UC12 value matches the valued in TB1RG0H L 0 Disable trigger TB1E0T1 1 Enable trigger TB1FF0 control Inverted when UC12 value matches the valued in TB1RG1H L 0 Disable trigger TB1E1T1 1 Enable trigger TB1FF0 c...

Page 310: ...0 0 0 0 0 bit Symbol Read Write W After reset 0 0 0 0 0 0 0 0 bit Symbol Read Write W After reset 0 0 0 0 0 0 0 0 bit Symbol Read Write W After reset 0 0 0 0 0 0 0 0 bit Symbol Read Write W After reset 0 0 0 0 0 0 0 0 Note All registers are prohibited to execute read modify write instruction Figure 3 13 8 Register for TMRB 6 TB0RG0L 1188H TB0RG0H 1189H TB0RG1L 118AH TB0RG1H 118BH TB1RG0L 1198H TB1...

Page 311: ...No change 2 16 bit event counter mode In 16 bit timer mode as described in above the timer can be used as an event counter by selecting the external clock TB0IN0 pin input as the input clock Up counter UC10 counts up at the rising edge of TB0IN0 input To read the value of the counter first perform software capture once and read the captured value 7 6 5 4 3 2 1 0 TB0RUN 0 X X X 0 Stop TMRB0 PPCR X ...

Page 312: ...e Generation PPG Output Waveforms When the TB0RG0H L double buffer is enabled in this mode the value of register buffer 10 will be shifted into TB0RG0H L at match with TB0RG1H L This feature facilitates the handling of low duty waves Figure 3 13 10 Operation of double buffer Note The values that can be set in TBxRGx range from 0001h to 0000h equivalent to 10000h If the maximum value 000h is set th...

Page 313: ... and frequency are changed on an INTTB01 interrupt TB0FFCR X X 0 0 1 1 1 0 Set the mode to invert TB0FF0 at the match with TB0RG0H L TB0RG1H L Set TB0FF0 to 0 TB0MOD 0 0 1 0 0 1 Select the internal clock as the input clock and disable 01 10 11 the capture function PPFC 1 X Set PP6 to function as TB0OUT0 TB0RUN 1 0 X X 1 X 1 Start TMRB0 X Don t care No change Selector 16 bit up counter UC10 16 bit ...

Page 314: ...e d to TB0RG0H L c d and set the above set value c d plus a one shot pulse width p to TB0RG1H L c d p The TB0FFCR TB0E1T1 TB0E0T1 register should be set 11 and that the TB0FF0 inversion is enabled only when the up counter value matches TB0RG0H L or TB0RG1H L When interrupt INTTB01 occurs this inversion will be disabled after one shot pulse is output The c d and p correspond to c d and p in the Fig...

Page 315: ...0 TB0CP0 3ms φT1 TB0RG1 TB0RG0 2ms φT1 TB0FFCR X X 1 1 Enable TB0FF0 inversion when the up counter value matches TB0RG0H L or TB0RG1H L INTETB0 X 1 0 0 X 0 0 0 Enable INTTB01 Setting in INTTB01 routine TB0FFCR X X 0 0 Disable TB0FF0 inversion when the up counter value matches TB0RG0H L or TB0RG1H L INTETB0 X 0 0 0 X 0 0 0 Disable INTTB01 X Don t care No change When delay time is unnecessary invert...

Page 316: ...in TB0CP0H L and TB0CP1H L when the interrupt INTTA0 or INTTA1 is generated by either 8 bit timer Figure 3 13 14 Frequency Measurement For example if the value for the level 1 width of TA1FF of the 8 bit timer is set to 0 5 s and the difference between TB0CP0H L and TB0CP1H L is 100 the frequency will be 100 0 5 s 200 Hz Note The frequency in this examole is calculated with 50 duty c p c Inversion...

Page 317: ...le For example if the internal clock is 0 8 us and the difference between TB0CP0H L and TB0CP1H L is 100 the pulse width will be 100 0 8 us 80us Additionally the pulse width which is over the UC10 maximum count time specified by the clock source can be measured by changing software Figure 3 13 15 Pulse Width Measurement Note Only in this pulse width measuring mode TB0MOD TB0CPM1 0 10 external inte...

Page 318: ...ly prescaler serial clock generation circuit receiving buffer and control circuit transmission buffer and control circuit Figure 3 14 1 Data Formats I O interface mode Mode 0 For transmitting and receiving I O data using the synchronizing signal SCLK for extending UART mode Mode 1 7 bit data Mode 2 8 bit data Mode 3 9 bit data Bit0 1 2 3 4 5 6 7 Bit0 1 2 3 4 5 6 Stop Start Bit0 1 2 3 4 5 Parity St...

Page 319: ... IOC Receive counter UART only 16 Transmision counter UART only 16 Receive control Transmission control INTRX0 INTTX0 Receive buffer 2 SC0BUF RB8 Error flag SC0CR OERR PERR FERR Serial channel interrupt control TB8 CTS0 TXD0 Transmission buffer SC0BUF RXD0 TXDCLK SC0MOD0 WU fIO SC0MOD0 RXE SCLK0 SCLK0 SIOCLK Internal data bus Parity control SC0CR PE EVEN Serial clock generation circuit BR0CR BR0CK...

Page 320: ... rate generator Table 3 14 1 Prescaler Clock Resolution to Baud Rate Generator Clock Resolution Clock gear SYSCR1 GEAR2 0 φT0 φT2 φT8 φT32 000 1 1 fSYS 4 fSYS 16 fSYS 64 fSYS 256 001 1 2 fSYS 8 fSYS 32 fSYS 128 fSYS 512 010 1 4 fSYS 16 fSYS 64 fSYS 256 fSYS 1024 011 1 8 fSYS 32 fSYS 128 fSYS 512 fSYS 2048 fc 100 1 16 1 4 fSYS 64 fSYS 256 fSYS 1024 fSYS 4096 XXX Don t care The baud rate generator s...

Page 321: ...DD BR0K3 0 are ignored The baud rate generator divides the selected prescaler clock by N which is set in BR0CK BR0S3 0 N 1 2 3 16 When BR0CR BR0ADDE 1 The N 16 K 16 division function is enabled The baud rate generator divides the selected prescaler clock by N 16 K 16 using the value of N set in BR0CR BR0S3 0 N 2 3 15 and the value of K set in BR0ADD BR0K3 0 K 1 2 3 15 Note If N 1 or N 16 the N 16 ...

Page 322: ...e input clock is φT2 the frequency divider N BR0CR BR0S3 0 6 K BR0ADD BR0K3 0 8 and BR0CR BR0ADDE 1 the baud rate in UART Mode is as follows Clock state System clock 1 1 Prescaler clock 1 2 Baud Rate 16 15 9744 106 16 6 16 9600 bps Table 3 14 2 show examples of UART Mode transfer rates Additionally the external clock input is available in the serial clock Serial Channel 0 The method for calculatin...

Page 323: ...800 7 200 1 800 9 76 800 19 200 4 800 1 200 58 9824 2 460 800 115 200 28 800 7 200 3 307 200 76 800 19 200 4 800 5 184 320 46 080 11 520 2 880 6 153 600 38 400 9 600 2 400 8 115 200 28 800 7 200 1 800 C 76 800 19 200 4 800 1 200 F 61 440 15 360 3 840 0 960 73 728 1 1152 000 288 000 72 000 18 000 3 384 000 96 000 24 000 6 000 6 192 000 48 000 12 000 3 000 A 115 200 28 800 7 200 1 800 C 96 000 24 00...

Page 324: ...each data bit is sampled three times on the 7th 8th and 9th clock cycles The value of the data bit is determined from these three samples using the majority rule For example if the data bit is sampled respectively as 1 0 and 1 on 7th 8th and 9th clock cycles the received data bit is taken to be 1 A data bit sampled as 0 0 and 1 is taken to be 0 5 Receiving control In I O Interface Mode In SCLK Out...

Page 325: ...r is enabled by setting SC0MOD0 WU to 1 in this mode INTRX0 interrupts occur only when the value of SC0CR RB8 is 1 SIO interrupt mode is selectable by the register SIMC Note1 The double buffer structure does not support SC0CR RV08 Note2 If the CPU reads receive buffer 2 while data is being transferred from receive buffer 1 to receive buffer 2 the data may not be read properly To avoid this situati...

Page 326: ...ft clock which is output on the SCLK0 pin according to the SC0CR SCLKS setting In SCLK Input Mode with the setting SC0CR IOC 1 the data in the Transmission Buffer is output one bit at a time on the TXD0 pin on the rising or falling edge of the SCLK0 input according to the SC0CR SCLKS setting In UART Mode When transmission data sent from the CPU is written to the Transmission Buffer transmission st...

Page 327: ...RTS pin a handshake function can be easily configured by setting any port assigned to be the RTS function The RTS should be output High to request send data halt after data receive is completed by software in the RXD interrupt routine Figure 3 14 4 Handshake function Note 1 1 If the 0 CTS signal goes High during transmission no more data will be sent after completion of the current transmission No...

Page 328: ... to the transmission buffer In the case of receiving data is shifted into receiving buffer 1 and the parity is added after the data has been transferred to receiving buffer 2 SC0BUF and then compared with SC0BUF RB7 in 7 bit UART mode or with SC0CR RB8 in 8 bit UART mode If they are not equal a parity error is generated and the SC0CR PERR flag is set 11 Error flags Three error flags are provided t...

Page 329: ...red every time it is read However if a parity error is detected w twice in succession and the parity error flag is read between the two parity errors it may seem as if the flag had not been cleared To avoid this situation a read of the parity error flag should be riggered by a receive interrupt 3 Framing error FERR The stop bit for the received data is sampled three times around the center If the ...

Page 330: ...red to allow checking for a framing error Note2 The higher the transfer rate the later than the middle receive interrupts and errors occur Transmitting Mode 9 Bit 8 Bit Parity 8 Bit 7 Bit Parity 7 Bit Interrupt timing Just before stop bit is transmitted Just before stop bit is transmitted Just before stop bit is transmitted b I O interface SCLK Output Mode Immediately after last bit See Figure 3 1...

Page 331: ...0 input Serial transmission clock source UART 00 TMRA0 match detect signal 01 Baud rate generator 10 Internal clock fIO 11 External clock SCLK0 input Note The clock selection for the I O interface mode is controlled by the serial bontrol register SC0CR Serial Transmission Mode 00 I O Interface Mode 01 7 bit mode 10 8 bit mode 11 UART mode 9 bit mode Wake up function 9 Bit UART Other Modes 0 Interr...

Page 332: ...ing Error flag Parity Error flag Overrun Error flag 0 Transmits and receivers data on rising edge of SCLK0 1 Transmits and receivers data on falling edge SCLK0 Edge selection for SCLK pin Input Output Mode 0 Disabled 1 Enabled Parity addition enables Even parity addition check 1 error 0 Baud rate generator 1 SCLK0 pin input Cleared to 0 when read 0 Odd parity 1 Even parity Received data 8 Prohibit...

Page 333: ...K 1 to 1111 K 15 Disable Divided by N 16 K 16 Divided by N BR0CR 1203H 16 K 16 division enable 00 Internal clock φT0 01 Internal clock φT2 10 Internal clock φT8 11 Internal clock φT32 Setting the input clock of baud rate generator 0 Disable 1 Enable Divided frequency setting BR0ADD 1204H Note1 Availability of 16 K 16 division function N UART mode I O mode 2 to 15 1 16 The baud rate generator can b...

Page 334: ...RB1 RB0 Receiving Note Prohibit read modify write for SC0BUF Figure 3 14 9 Serial Transmission Receiving Buffer Registers channel 0 SC0BUF 7 6 5 4 3 2 1 0 Bit symbol I2S0 FDPX0 Read Write R W R W After Reset 0 0 Function IDLE2 0 Stop 1 Run duplex 0 half 1 full Figure 3 14 10 Serial Mode Control Register 1 channel 0 SC0MOD1 SC0MOD1 1205H ...

Page 335: ...e 3 14 11 SCLK Output Mode connection example Figure 3 14 12 Example of SCLK Input Mode Connection Output extension TC74HC595 or equivalent A B SI C D SCK E F RCK G H TXD SCLK Port Shift register TMP92CZ26A Input extension TC74HC165 or equivalent A B QH C D CLOCK E F S L G H RXD SCLK Port Shift register TMP92CZ26A Output extension TC74HC595 or equivalent A B SI C D SCK E F RCK G H TXD SCLK Port Sh...

Page 336: ...ut on the TXD0 pin when the SCLK0 input becomes active after the data has been written to the Transmission Buffer by the CPU When all data is output INTES0 ITX0C will be set to generate INTTX0 interrupt Figure 3 14 14 Transmitting Operation in I O Interface Mode SCLK0 Input Mode TXD0 ITX0C INTTX0 interrupt request SCLK0 output SCLKS 0 rising edge mode Timing to write transmisison data Bit0 Bit1 Bi...

Page 337: ...shifted to Receiving Buffer 1 when the SCLK input goes active The SCLK input goes active when the Receive Interrupt flag INTES0 IRX0C is cleared as the received data is read When 8 bit data is received the data is shifted to Receiving Buffer 2 SC0BUF following the timing shown below and INTES0 IRX0C is set to 1 again causing an INTRX0 interrupt to be generated Figure 3 14 16 Receiving Operation in...

Page 338: ...s fsys 2 4576 MHz Main routine 7 6 5 4 3 2 1 0 INTES0 X 0 0 1 X 0 0 0 Set the INTTX0 level to 1 Set the INTRX0 level to 0 P9CR X X X X X 1 0 1 P9FC X X X 1 X 1 Set P90 P91 and P92 to function as the TXD0 RXD0 and SCLK0 pins respectively SC0MOD0 0 0 Select I O interface mode SC0MOD1 1 X X X X X X Select full duplex mode SC0CR 0 0 SCLK0 output mode select rising edge BR0CR 0 0 0 1 1 0 0 0 Baud rate ...

Page 339: ...C0CR 1 1 Add even parity BR0CR 0 0 1 0 1 0 0 0 Set the transfer rate to 2400 bps INTES0 X 1 0 0 X 0 0 0 Enable the INTTX0 interrupt and set it to interrupt level 4 SC0BUF Set data for transmission X Don t care No change 3 Mode 2 8 Bit UART Mode 8 Bit UART Mode is selected by setting SC0MOD0 SM1 SM0 to 10 In this mode a parity bit can be added use of a parity bit is enabled or disabled by the setti...

Page 340: ...RT Mode 9 Bit UART Mode is selected by setting SC0MOD0 SM1 0 to 11 In this mode parity bit cannot be added In the case of transmission the MSB 9th bit is written to SC0MOD0 TB8 In the case of receiving it is stored in SC0CR RB8 When the buffer is written and read the MSB is read or written first before the rest of the SC0BUF data Wake up function In 9 Bit UART Mode the wake up function for slave c...

Page 341: ...ller whose code matches clears its WU bit to 0 5 The master controller transmits data to the specified slave controller the controller whose SC0MOD0 WU bit has been cleared to 0 The MSB bit 8 of the data TB8 is cleared to 0 6 The other slave controllers whose WU bits remain at 1 ignore the received data because their MSBs bit 8 or RB8 are set to 0 disabling INTRX0 interrupts The slave controller w...

Page 342: ...e using fSYS as the transfer clock Interrupt routine INTRX0 Acc SC0BUF if Acc Select code Then SC0MOD0 0 Clear WU to 0 Main routine P9CR X X X X X 0 1 P9FC X X X X 1 Set P90 and P91 to function as the TXD0 and RXD0 pins respectively INTES0 X 1 0 0 X 1 0 1 Enable the INTTX0 interrupt and set it to Interrupt Level 4 Enable the INTRX0 interrupt and set it to Interrupt Level 5 SC0MOD0 1 0 1 0 1 1 1 0 ...

Page 343: ...R PLSEL When the transmit data is 1 the modem outputs 0 Figure 3 14 19 Transmission example 2 Modulation of the receive data When the receive data is the effective width of pulse 1 the modem outputs 0 to SIO0 Otherwise the modem outputs 1 to SIO0 The effective pulse width is selected by SIRCR SIRWD3 to SIRWD0 Figure 3 14 20 Receiving example Transmisison data SIO0 IR modulator IR demodulator Recei...

Page 344: ...the data SIRCR during SIO0 is stopping The following example describes how to set this register 1 SIO setting Set the SIO to UART Mode 2 LD SIRCR 07H Set the receive data pulse width to 16 3 LD SIRCR 37H TXEN RXEN Enable the Transmission and receiving 4 Start transmission and receiving for SIO0 The modem operates as follows y SIO0 starts transmitting y IR receiver starts receiving ...

Page 345: ...2 23 μs The infra red pulse width is specified either baud rate T 3 16 or 1 6 μs 1 6 μs is equal to 3 16 pulse width when baud rate is 115 2 kbps The TMP92CZ26A has the function selects the pulse width of Transmission either 3 16 or 1 16 But 1 16 pulse width can be selected when the baud rate is equal or less than 38 4 kbps As the same reason 16 k 16 division function in the baud rate generator of...

Page 346: ...n be set 1 to 14 Can not be set 0 15 Select receive pulse width Formula Effective pulse width 2x value 1 100ns x 1 fFPH 0000 Cannot be set 0001 Equal or more than 4x 100ns to 1110 Equal or more than 30x 100ns 1111 Can not be set Receive recovery operation 0 Disable receiving operation Received data is ignored 1 Enabled receiving operation Transmit modulation operation 0 Disabled transmission opera...

Page 347: ...V7C PV6C PVFC PV7F PV6F I2 C bus mode 11 11 11 3 15 1 Configuration Figure 3 15 1 Serial bus interface SBI SIO clock control Divider I 2 C bus clock sync control SBICR2 SBISR SCL SCK Input output control SO SI SDA I2CAR SBIDBR SBICR0 1 SBIBR0 Shift register Transfer control circuit Noise canceller fSYS 4 Noise canceller I 2 C bus data control SIO data control INTSBI interrupt request PV6 SDA PV7 S...

Page 348: ...r 0 SBIBR0 3 15 3 The Data Formats in the I2 C Bus Mode The data formats in the I2C bus mode is shown below a Addressing format b Addressing format with restart c Free data format data transferred from master device to slave device Figure 3 15 2 Data format in the I2 C bus mode S Slave address R W Data A C K A C K Data A C K P 8 bits 1 1 to 8 bits 1 1 to 8 bits 1 1 1 or more S Slave address R W Da...

Page 349: ...the I2C bus mode Serial Bus Interface Control Register 0 7 6 5 4 3 2 1 0 Bit symbol SBIEN Read Write R W R After Reset 0 0 0 0 0 0 0 0 Function SBI operation 0 disable 1 enable Always read 0 SBIEN When using SBI SBIEN should be set 1 SBI operation enable before setting each register of SBI module Figure 3 15 3 Registers for the I2 C bus mode Prohibit Read modify Write SBICR0 1247H ...

Page 350: ...specification 0 Not generate clock pulse for acknowledge signal 1 Generate clock pulse for acknowledge signal Number of bits transferred ACK 0 ACK 1 BC2 0 Number of clock pulses Bits Number of clock pulses Bits 000 001 010 011 100 101 110 111 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 9 2 3 4 5 6 7 8 8 1 2 3 4 5 6 7 Note1 For the frequency of the SCL line clock see 3 15 5 3 Serial clock Note2 The initial dat...

Page 351: ...1 Reserved 10 I 2 C Bus mode 11 Reserved Software reset generate write 10 and 01 then an internal reset signal is generated Serial bus interface operating mode selection Note2 00 Port Mode Serial Bus Interface output disabled 01 Reserved 10 I 2 C Bus Mode 11 Reserved Note 1 Reading this register functions as SBISR register Note 2 Switch a mode to port mode after confirming that the bus is free Swi...

Page 352: ...n monitor 0 Undetected 1 Detected GENERAL CALL detection monitor 0 Undetected 1 Detected Last received bit monitor 0 0 1 1 Last received bit monitor 0 Last received bit was 0 1 Last received bit was 1 GENERAL CALL detection monitor 0 Undetected 1 GENERAL CALL detected Slave address match detection monitor 0 Slave address don t match or Undetected 1 Slave address match or GENERAL CALL detected Arbi...

Page 353: ...ced from LSB bit0 Note2 SBIDBR can t be read the written data because of it has buffer for writing and buffer for reading individually Therefore Read modify write instruction e g BIT instruction is prohibitted Note3 Written data to SBIDBR is cleared by INTSBI signal I2 C Bus Address Register 7 6 5 4 3 2 1 0 Bit symbol SA6 SA5 SA4 SA3 SA2 SA1 SA0 ALS I2CAR 1242H Read Write R W After reset 0 0 0 0 0...

Page 354: ...does not generate a clock pulse for the Acknowledge signal when operating in the Master Mode 2 Number of transfer bits The SBICR1 BC2 0 is used to select a number of bits for next transmitting and receiving data Since the BC2 0 is cleared to 000 as a start condition a slave address and direction bit transmission are executed in 8 bits Other than these the BC2 0 retains a specified value 3 Serial c...

Page 355: ...High level Since Master B holds the SCL line of the bus at the Low level Master A wait for counting high level width of an own clock pulse After Master B finishes counting low level width of an own clock pulse at point c and Master A detects the SCL line of the bus at the High level and starts counting High level of an own clock pulse The clock pulse on the bus is determined by the master device w...

Page 356: ...he I2C bus is detected or arbitration is lost 7 Start Stop condition generation When the SBISR BB is 0 slave address and direction bit which are set to SBIDBR are output on a bus after generating a start condition by writing 1 to the SBICR2 MST TRX BB PIN It is necessary to set transmitted data to the data buffer register SBIDBR and set 1 to ACK beforehand Figure 3 15 10 Start condition generation...

Page 357: ...ration procedure has been implemented in order to guarantee the integrity of transferred data In case set start condition bit with bus is busy start condition is not output on SCL and SDA pin but arbitration lost is generated Data on the SDA line is used for I2C bus arbitration The following shows an example of a bus arbitration procedure when two master devices exist simultaneously on the bus Mas...

Page 358: ... AAS is cleared to 0 when data is written to or read from the data buffer register SBIDBR 12 GENERAL CALL detection monitor SBISR AD0 is set to 1 in Slave Mode when a GENERAL CALL is received all 8 bit received data is 0 after a start condition SBISR AD0 is cleared to 0 when a start condition or stop condition is detected on the bus 13 Last received bit monitor The SDA line value stored at the ris...

Page 359: ...r Register SBIDBR The received data can be read and transferred data can be written by reading or writing the SBIDBR In the master mode after the start condition is generated the slave address and the direction bit are set in this register 16 I2CBUS Address Register I2CAR I2CAR SA6 0 is used to set the slave address when the TMP92CZ26A functions as a slave device The slave address output from the ...

Page 360: ...smitted to the SBIDBR When SBICR2 BB 0 the start condition are generated by writing 1111 to SBICR2 MST TRX BB PIN Subsequently to the start condition nine clocks are output from the SCL pin While eight clocks are output the slave address and the direction bit which are set to the SBIDBR At the 9th clock the SDA line is released and the acknowledge signal is received from the slave device An INTSBI...

Page 361: ... set in I2CAR is received the SDA line is pulled down to the Low level at the 9th clock and the acknowledge signal is output An INTSBI interrupt request occurs on the falling edge of the 9th clock The PIN is cleared to 0 In Slave Mode the SCL line is pulled down to the Low level while the PIN 0 Figure 3 15 14 Start condition generation and slave address transfer 1 2 3 4 5 6 7 8 9 A6 A5 A4 A3 A2 A1...

Page 362: ...erial clock pulse is generated for transferring a new 1 word of data from the SCL pin and then the 1 word data is transmitted After the data is transmitted an INTSBI interrupt request occurs The PIN becomes 0 and the SCL line is pulled down to the Low level If the data to be transferred is more than one word in length repeat the procedure from the LRB checking above INTSBI interrupt if MST 0 Then ...

Page 363: ...ast data word does not generate a clock pulse as the Acknowledge signal After the data has been transmitted and an interrupt request has been generated set BC2 0 to 001 and read the data The TMP92CZ26A generates a clock pulse for a 1 bit data transfer Since the master device is a receiver the SDA line on the bus remains High The transmitter interprets the High signal as an ACK signal The receiver ...

Page 364: ...ad the data of 1st to N 2 th End of interrupt INTSBI interrupt N 1 th Receive data 7 6 5 4 3 2 1 0 SBICR1 X X X 0 0 X X X Not generate acknowledge signal Reg SBIDBR Load the data of N 1 th End of interrupt INTSBI interrupt Nth Receive data 7 6 5 4 3 2 1 0 SBICR1 0 0 1 0 0 X X X Generate the clock for 1bit transmit Reg SBIDBR Receive the data of Nth End of interrupt INTSBI interrupt After receiving...

Page 365: ... data transfer terminates after losing arbitration When an INTSBI interrupt request occurs the PIN is cleared to 0 and the SCL pin is pulled down to the Low level Either reading writing from to the SBIDBR or setting the PIN to 1 will release the SCL pin after taking tLOW time Check the SBISR AL TRX AAS and AD0 and implements processes according to conditions listed in the next table Example In cas...

Page 366: ...ear TRX to 0 to release the bus If LRB is cleared to 0 set BC2 0 to the number of bits in a word and write the transmitted data to SBIDBR since the receiver requests next data 1 1 0 The TMP92CZ26A loses arbitration when transmitting a slave address and receives a slave address or GENERAL CALL for which the value of the direction bit sent from another master is 0 1 0 0 The TMP92CZ26A loses arbitrat...

Page 367: ...n pulled Low by another device the TMP92CZ26A generates a stop condition when the other device has released the SCL line and SDA pin rising 7 6 5 4 3 2 1 0 SBICR2 1 1 0 1 1 0 0 0 Generate stop condition Figure 3 15 18 Stop condition generation Single master Figure 3 15 19 Stop condition generation Multi master SCL pin SDA Pin PIN BB Read Stop condition 1 MST 1 TRX 0 BB 1 PIN Internal SCL Internal ...

Page 368: ...ter confirming that the bus remains in a free state generate a start condition using the procedure described in 2 In order to satisfy the set up time requirements when restarting take at least 4 7 μs of waiting time by software from the time of restarting to confirm that the bus is free until the time to generate the start condition 7 6 5 4 3 2 1 0 SBICR2 0 0 0 1 1 0 0 0 Release the bus if SBISR B...

Page 369: ...BULK in 64 bytes 2 FIFO Endpoint 3 Interrupt in 8 bytes 1 FIFO 5 Built in DPLL which generates sampling clock for receive data 6 Detecting and generating SOP EOP RESUME RESET and TIMEOUT 7 Encoding and decoding NRZI data 8 Inserting and discarding stuffed bit 9 Detecting and checking CRC 10 Generating and decoding packet ID 11 Built in power management function 12 Supported dual packet mode Note1 ...

Page 370: ...scriptor RAM and 4 endpoint FIFO 3 USB transceiver About above 1 is explained at 3 16 2 and 2 is 3 16 3 Figure 3 16 1 UDC Block Diagram Descriptor RAM 384 bytes Request controller Endpoint 0 FIFO 64 bytes 1 Endpoint 1 FIFO 64 bytes 2 Endpoint 2 FIFO 64 bytes 2 Endpoint 3 FIFO 8 bytes 1 PWM DPLL SIE IFM I F FIFO manager 900 H1 CPU interface USB transceiver UDC core ADDRESS RD WR D UDC D ...

Page 371: ...at method of detecting by using VBUS 5V voltage Note If rising of waveform is solw recommned that likely baffering for waveform Recommendation value R6 60kΩ R7 100kΩ VBUS reducing current when suspend 500μA 4 Connect oscillator of 10MHz to X1 X2 or input 48MHz clock to X1USB If using USB by using the combination external 10MHz oscillator and internal Stage of external hub which can be used is rest...

Page 372: ... control USBINTFR1 USB interrupt flag register 1 USBINTFR2 USB interrupt flag register 2 USBINTFR3 USB interrupt flag register 3 USBINTFR4 USB interrupt flag register 4 USBINTMR1 USB interrupt mask register 1 USBINTMR2 USB interrupt mask register 2 USBINTMR3 USB interrupt mask register 3 USBINTMR4 USB interrupt mask register 4 Figure 3 16 2 900 H1 CPU I F SFR Address Read Write SFR Symbol 07F0H R ...

Page 373: ...REMOTE WAKEUP If the REMOTE WAKEUP 1 means SUSPEND status write 1 and 0 to WAKEUP after checking by this remote wakeup function will be started If the REMOTE WAKEUP 0 or EP0 1 2 3_STATUS SUSPEND 0 don t write 1 to WAKEUP SPEED Bit1 1 Full speed 12 MHz 0 Reserved This bit selects USB speed Set to 1 for TMP92CZ26A USBCLKE Bit0 0 Disable USB clock 1 Enable USB clock This bit controls to supply USB cl...

Page 374: ...pt souce changes 1 0 C The flag register is set because mask register 0 and interrupt souce changes 0 1 D The flag register is reset to 0 by writing 0 to flag register Note 1 Both INTUSB generated number and bit number which is set to flag register are not always equal In the INTUSB interrupt routine clear FLAG register USBINTFRn after checking it The interrupt request flag which is occurred betwe...

Page 375: ...R or INT_URST_END request of RESET INT_URST_STR Bit7 This is a flag for INT_URST_STR USB reset start interrupt This is set to 1 when the UDC started to receive USB reset signal from USB host An application program has to initialize whole UDC by this interrupt INT_URST_END Bit6 This is a flag for INT_URST_END USB reset end interrupt This is set to 1 when the UDC receive USB reset end signal from US...

Page 376: ...en read 0 Not generate interrupt 1 Generate interrupt When write 0 Clear flag 1 Note Above interrupt can release Halt state from IDLE2 mode IDLE1 and STOP mode can not be released EPx_FULL_A B When transmitting This is set to 1 when CPU full write data to FIFO_A B When receiving This is set to 1 when UDC full receive data to FIFO_A B EPx_Empty_A B When transmitting This is set to 1 when FIFO becom...

Page 377: ...interrupt This is set to 1 when the UDC receive data of the data phase for Control transfer type At the Control write transfer data reading from FIFO is needed if this interrupt occur At the Control read transfer transmission data writing to FIFO is needed if this interrupts occurred By host may don t assert ACK of last packet in the data stage In that case this interrupt cannot be generated So ig...

Page 378: ...ngth specified by the host But if the USB host change to status stage this interrupt is always generated because of this signal is designed by using NAK of first packet So to avoid that this interrupt always generate use mask register USBINTMRn Disable this interrupt before data of last payload is written INT_EPxN Bit3 2 1 This is a flag for INT_EPxN NAK acknowledge to the USB host interrupt This ...

Page 379: ...ked MSK_URST_STR Bit7 This is a mask register for USBINTFR1 INT_URST_STR MSK_URST_END Bit6 This is a mask register for USBINTFR1 INT_URST_END MSK_SUS Bit5 This is a mask register for USBINTFR1 INT_SUS MSK_RESUME Bit4 This is a mask register for USBINTFR1 INT_RESUME MSK_CLKSTOP Bit3 This is a mask register for USBINTFR1 INT_CLKSTOP MSK_CLKON Bit2 This is a mask register for USBINTFR1 INT_CLKON USBI...

Page 380: ...r reset 1 1 1 1 1 1 1 1 Function 0 Be not masked 1 Be masked EP1 2_MSK_FA FB EA EB This is a mask register for USBINTFR2 EPx_FULL_A B or EPx_Empty_A B 7 6 5 4 3 2 1 0 bit Symbol EP3_MSK_FA EP3_MSK_EA Read Write R W R W After reset 1 1 Function 0 Be not masked 1 Be masked EP3_MSK_FA FB EA EB This is a mask register for USBINTFR3 EP3_FULL_A or EP3_Empty_A USBINTMR2 07F5H USBINTMR3 07F6H ...

Page 381: ...7 This is a mask register for USBINTFR4 INT_SETUP MSK_EP0 Bit6 This is a mask register for USBINTFR4 INT_EP0 MSK_STAS Bit5 This is a mask register for USBINTFR4 INT_STAS MSK_STASN Bit4 This is a mask register for USBINTFR4 INT_STASN MSK_EP1N Bit3 This is a mask register for USBINTFR4 INT_EP1N MSK_EP2N Bit2 This is a mask register for USBINTFR4 INT_EP2N MSK_EP3N Bit1 This is a mask register for USB...

Page 382: ...nfig register USB_STATE register StandardRequest register Request register EPx_STATUS register d Setup EPx_BCS register EPx_SINGLE register Standard Request Mode register Request Mode register Descriptor RAM register PortStatus register e Control EPx_MODE register EOP register COMMAND register INT_ Control register Setup Received register USBREADY register f Others ADDRESS register DATASET registe...

Page 383: ...d 0789H R W EP1_MODE 078AH R W EP2_MODE 078BH R W EP3_MODE 078CH R W EP4_MODE 078DH R W EP5_MODE 078EH R W EP6_MODE 078FH R W EP7_MODE 0790H R EP0_STATUS 0791H R EP1_STATUS 0792H R EP2_STATUS 0793H R EP3_STATUS 0794H R EP4_STATUS 0795H R EP5_STATUS 0796H R EP6_STATUS 0797H R EP7_STATUS 0798H R EP0_SIZE_L_A 0799H R EP1_SIZE_L_A 079AH R EP2_SIZE_L_A 079BH R EP3_SIZE_L_A 079CH R EP4_SIZE_L_A 079DH R ...

Page 384: ...uest 07C2H R wValue_L 07C3H R wValue_H 07C4H R wIndex_L 07C5H R wIndex_H 07C6H R wLength_L 07C7H R wLength_H 07C8H W Setup Received 07C9H R Current_Config 07CAH R Standard Request 07CBH R Request 07CCH R DATASET1 07CDH R DATASET2 07CEH R USB_STATE 07CFH W EOP 07D0H W COMMAND 07D1H R W EPx_SINGLE1 07D1H R W EPx_SINGLE2 07D3H R W EPx_BCS1 07D4H R W EPx_BCS2 07D5H R W Reserved 07D6H R W INT_Control 0...

Page 385: ...DC CORE SFRs 3 3 Address Read Write SFR Symbol 07E0H R W Port_Status 07E1H R FRAME_L 07E2H R FRAME_H 07E3H R ADDRESS 07E4H Reserved 07E5H Reserved 07E6H R W USBREADY 07E7H Reserved 07E8H W Set Descriptor STALL Note is not used at TMP92CZ26A ...

Page 386: ...t Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 7 6 5 4 3 2 1 0 bit Symbol EP3_DATA7 EP3_DATA6 EP3_DATA5 EP3_DATA4 EP3_DATA3 EP3_DATA2 EP3_DATA1 EP3_DATA0 Read Write R W R W R W R W R W R W R W R W After reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Note Read or write these window registers by using load instruction of 1 byt...

Page 387: ...nt 00011 etc Others Reserved 3 16 3 4 bRequest Register This register shows the bRequest field of device request 7 6 5 4 3 2 1 0 bit Symbol REQUEST7 REQUEST6 REQUEST5 REQUEST4 REQUEST3 REQUEST2 REQUEST1 REQUEST0 Read Write R R R R R R R R After reset 0 0 0 0 0 0 0 0 Standard Printer class 00000000 GET_STATUS 00000000 GET_DEVICE_ID 00000001 CLEAR_FEATURE 00000001 GET_PORT_STATUS 00000010 Reserved 0...

Page 388: ... 2 1 0 bit Symbol INDEX_L7 INDEX_L6 INDEX_L5 INDEX_L4 INDEX_L3 INDEX_L2 INDEX_L1 INDEX_L0 Read Write R R R R R R R R After reset 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 bit Symbol INDEX_H7 INDEX_H6 INDEX_H5 INDEX_H4 INDEX_H3 INDEX_H2 INDEX_H1 INDEX_H0 Read Write R R R R R R R R After reset 0 0 0 0 0 0 0 0 3 16 3 7 wLength Register There are 2 registers the wLength_L register and wLength_H register the wLe...

Page 389: ...his register shows the present value that is set by SET_CONFIGURATION and SET_INTERFACE 7 6 5 4 3 2 1 0 bit Symbol REMOTEWAKEUP ALTERNATE 1 ALTERNATE 0 INTERFACE 1 INTERFACE 0 CONFIG 1 CONFIG 0 Read Write R R R R R R R After reset 0 0 0 0 0 0 0 CONFIG 1 0 Bit1 to bit0 00 UNCONFIGURED Set to UNCONFIGURED by the host 01 CONFIGURED1 Set to CONFIGURED 1 by the host 10 CONFIGURED2 Set to CONFIGURED 2 b...

Page 390: ... Bit 4 GET_CONFIGRATION Bit 3 GET_DESCRIPTOR Bit 2 SET_FEATURE Bit 1 CLEAR_FEATURE Bit 0 GET_STATUS 3 16 3 11 Request Register This register shows the device request that is executing now A bit which is set to 1 shows present executing request 7 6 5 4 3 2 1 0 bit Symbol SOFT_RESET G_PORT_STS G_DEVICE_ID VENDOR CLASS ExSTANDARD STANDARD Read Write R R R R R R R After reset 0 0 0 0 0 0 0 SOFT_RESET ...

Page 391: ...ngle packet mode DATASET1 Bit0 bit2 bit4 and bit6 DATASET2 Bit0 bit2 bit4 and bit6 These bits show whether FIFO of applicable endpoint has data or not In endpoint of receiving mode if bit 1 of applicable endpoint is 1 data that should be read exist to FIFO Access EPx_SIZE register and grasp size of data that should be read and read data of its size When this bit is 0 data that should be read does ...

Page 392: ... to FIFO If transmission become short packet write 0 to EOP EPn_EOPB after writing data to the FIFO The maximum size that can be written to A or B packet is same with maximum payload size If the both A and B bits are 0 continuous writing of double maximum payload size are available Note3 In the dual packet transmitting mode if both A and B packet are empty and EOP EPn_EOPB is written 0 the NULL da...

Page 393: ...ATUS 1 STATUS 0 FIFO_DISABLE STAGE_ERR Read Write R R R R R R R After reset 0 0 1 1 1 0 0 7 6 5 4 3 2 1 0 bit Symbol TOGGLE SUSPEND STATUS 2 STATUS 1 STATUS 0 FIFO_DISABLE STAGE_ERR Read Write R R R R R R R After reset 0 0 1 1 1 0 0 7 6 5 4 3 2 1 0 bit Symbol TOGGLE SUSPEND STATUS 2 STATUS 1 STATUS 0 FIFO_DISABLE STAGE_ERR Read Write R R R R R R R After reset 0 0 1 1 1 0 0 7 6 5 4 3 2 1 0 bit Symb...

Page 394: ...is not generated The hosts re try and transfer IN token to this 100 RX_ERR UDC set RX_ERR to status register without transmitting ACK to host when an error like a CRC error is detected in data of received token In this case an interrupt is not generated The hosts re try and transfer IN token to this 101 BUSY This status is used only for the control transfer type and it is set when a token of statu...

Page 395: ...ETUP token is received When this bit is 1 this bit is cleared to 0 by read EP0_STATUS register This bit is not cleared even if normal control transfer or other transfer is executed after To clear read this bit When software transaction is finished and UDC writes EOP register UDC shifts to status register and waits termination of status stage In this case if software is needed to confirm that statu...

Page 396: ... 4 3 2 1 0 bit Symbol PKT_ACTIVE DATASIZE6 DATASIZE5 DATASIZE4 DATASIZE3 DATASIZE2 DATASIZE1 DATASIZE0 Read Write R R R R R R R R After reset 1 0 0 0 1 0 0 0 7 6 5 4 3 2 1 0 bit Symbol PKT_ACTIVE DATASIZE6 DATASIZE5 DATASIZE4 DATASIZE3 DATASIZE2 DATASIZE1 DATASIZE0 Read Write R R R R R R R R After reset 1 0 0 0 1 0 0 0 7 6 5 4 3 2 1 0 bit Symbol PKT_ACTIVE DATASIZE6 DATASIZE5 DATASIZE4 DATASIZE3 D...

Page 397: ...SIZE9 DATASIZE8 DATASIZE7 Read Write R R R After reset 0 0 0 7 6 5 4 3 2 1 0 bit Symbol DATASIZE9 DATASIZE8 DATASIZE7 Read Write R R R After reset 0 0 0 7 6 5 4 3 2 1 0 bit Symbol DATASIZE9 DATASIZE8 DATASIZE7 Read Write R R R After reset 0 0 0 7 6 5 4 3 2 1 0 bit Symbol DATASIZE9 DATASIZE8 DATASIZE7 Read Write R R R After reset 0 0 0 Note EP3 4 5 6 7_SIZE_L_B registers are not used at TMP92CZ26A ...

Page 398: ...ASIZE9 DATASIZE8 DATASIZE7 Read Write R R R After reset 0 0 0 7 6 5 4 3 2 1 0 bit Symbol DATASIZE9 DATASIZE8 DATASIZE7 Read Write R R R After reset 0 0 0 7 6 5 4 3 2 1 0 bit Symbol DATASIZE9 DATASIZE8 DATASIZE7 Read Write R R R After reset 0 0 0 7 6 5 4 3 2 1 0 bit Symbol DATASIZE9 DATASIZE8 DATASIZE7 Read Write R R R After reset 0 0 0 Note EP4 5 6 7_SIZE_H_A registers are not used at TMP92CZ26A E...

Page 399: ...R After reset 0 0 0 Note EP3 4 5 6 7_SIZE_H_B registers are not used at TMP92CZ26A DATASIZE 9 7 H register Bit2 to bit0 DATASIZE 6 0 L register Bit6 to bit0 In receiving data number that 1 packet received from the host is shown This is renewed when a data from the host is received with no error PKT_ACTIVE L register Bit7 1 OUT_ENABLE 0 OUT_DISABLE When dual packet mode is selected this bit show pa...

Page 400: ...tialized to 0 FRAME STS 1 0 H register Bit1 and bit0 0 BEFORE 1 VALID 2 LOST These bits show the status whether a frame number that is shown FRAME register is correct or not At the LOST status a correct frame number is undefined If this register is VALID number that is shown to FRAME register is correct If this register is BEFORE when SOF auto generation BEFORE condition shows it from USB host con...

Page 401: ...er reset 1 1 1 1 1 1 1 1 Note EOP EP7_EOPB EP6_EOPB EP5_EOPB EP4_EOPB registers are not used at TMP92CZ26A In a dataphase of control transfer type write 0 to EP0_EOPB when all transmission data is written to the FIFO or read all receiving data from the FIFO UDC is terminated status stage by this signal When short packet is transmitted by using bulk IN or interrupt IN endpoint use this for terminat...

Page 402: ...control in software Each bit mean kind of request When this register is set applicable bit to 0 answer is executed automatically by hardware When this register is set applicable bit to 1 answer is controlled by software If request is received during hardware control interrupt signal INT_SETUP INT_EP0 INT_STAS INT_STAN is set to disable If request is received during software control interrupt signa...

Page 403: ...rol interrupt signal is asserted and it is controlled by software 7 6 5 4 3 2 1 0 bit Symbol Soft_Reset G_Port_Sts G_DeviceId Read Write R W R W R W After reset 0 0 0 Note TMP92CZ26A don t use this register because of printer class is not support automatic answer Soft_Reset G_Port_Sts G_Config G_Descript Bit 7 Reserved Bit 6 SOFT_RESET Bit 5 GET_PORT_STATUS Bit 4 GET_DEVICE_ID Bit 3 to 0 Reserved ...

Page 404: ...011 RESET This COMMAND reset applicable endpoint EP0 to EP3 If this COMMAND is inputted applicable endpoint is initialized CLEAR_FEATURE request stall endpoint When this stall is cleared execute this COMMAND This command doesn t affect to transfer mode This command Initialize following item Clear toggle sequence bit of applicable endpoint Clear STALL of applicable endpoint Set to FIFO_ENABLE condi...

Page 405: ... If UDC detect USB_RESET from host controller it read content of descriptor RAM automatically and it set various setting If descriptor RAM is changed during operates system it must read setting again Therefore execute this command Case of connects to USB host this function start reading automatically Therefore don t have to execute this command 1010 FIFO_CLEA This COMMAND initializes FIFO of appli...

Page 406: ...te of present for connection with USB host 7 6 5 4 3 2 1 0 bit Symbol Configured Addressed Default Read Write R W R R After reset 0 0 1 Inside UDC answer for each Device Request is managed by referring this bits Configured Addressed and Default If transaction for SET_CONFIG request is executed by using software write present state to this register If host appointconfig0 this becomes Unconfigured A...

Page 407: ...set to software control after received INT_SETUP interrupt finish writing before access EOP register This register prohibits writing when it is other timing and it is ignored DIRECTION Bit0 0 OUT Direction of from host to device 1 IN Direction of from device to host MODE 1 0 Bit2 and bit1 00 Control transfer type 01 Isochronous transfer type 10 Bulk transfer type or interrupt transfer type 11 Inte...

Page 408: ...SINGLE bit become valid in following content 0 DUAL mode 1 SINGLE mode If set ting content of EPx_SINGLE bit to valid set EPx_SELECT bit to 1 0 Invalid 1 Valid 3 16 3 26 EPx_BCS Register This register set mode that access to FIFO in each endpoint 7 6 5 4 3 2 1 0 bit Symbol EP3_SELECT EP2_SELECT EP1_SELECT EP3_BCS EP2_BCS EP1_BCS Read Write R W R W R W R W R W R W After reset 0 0 0 0 0 0 Bit number...

Page 409: ...fter released USB_RESET If pull up resister on D signal is controlled by using control signal when pull up resister is connected to host in OFF condition this condition is equivalent condition with USB_RESET signal by pull down resister in host side Therefore UDC isn t detected in USB_RESET until write 0 to USBREADY register Note1 Pull up resister and control switch are needed at external of TMP92...

Page 410: ...efined This register can Read Write only following timing before detect USB_RESET during processing SET_DESCRIPTOR request SET_DESCRIPTOR request processes from INT_SETUP assert until access EOP register If there is rewriting request of descriptor in SET_DESCRIPTOR process request following sequence 1 Read descriptor that is transferred by SET_DESCRIPTOR requests every packet 2 When reading descri...

Page 411: ...effective only case of store descriptor as RAM Note 5 RAM size is total 384 bytes Note 6 Possible timing in RD WR of descriptor RAM is only before detect USB_RESET and processing SET_DESCRIPTOR request Prohibit access except this timing Writing must finish before connect to USB host and processing SET_DESCRIPTOR request SET_DESCRIPTOR request processes from INT_SETUP assert until access EOP regist...

Page 412: ...or 512H 09H BLength 513H 02H bDescriptorType Config Descriptor 514H 4EH wtotalLength L 78 bytes 515H 00H wtotalLength H 516H 01H bNumInterfaces 517H 01H bConfigurationValue 518H 00H iConfiguration 519H A0H bmAttributes Bus powered remote wakeup 51AH 31H MaxPower 98 mA Interface0 Descriptor AlternateSetting0 51BH 09H bLength 51CH 04H bDescriptorType Interface Descriptor 51DH 00H bInterfaceNumber 51...

Page 413: ...82H bEndpointAddress IN 53EH 02H bmAttributes BULK 53FH 40H wMaxPacketSize L 64 bytes 540H 00H wMaxPacketSize H 541H 00H bInterval Interface0 Descriptor AlternateSetting2 542H 09H bLength 543H 04H bDescriptorType Interface Descriptor 544H 00H bInterfaceNumber 545H 02H bAlternateSetting AlternateSetting2 546H 03H bNumEndpoints 547H FFH bInterfaceClass 548H 00H bInterfaceSubClass 549H FFH bInterface...

Page 414: ...criptor1 562H 00H bLength Length of String Descriptor2 563H 00H bLength Length of String Descriptor3 String Descriptor0 564H 04H bLength 565H 03H bDescriptorType String Descriptor 566H 09H bString Language ID 0x0409 567H 04H bString String Descriptor1 568H 10H bLength 569H 03H bDescriptorType String Descriptor 56AH 00H bString Toshiba 56BH 54H bString T 56CH 00H bString 56DH 6FH bString o 56EH 00H...

Page 415: ...akeup Self power D15 D14 D13 D12 D11 D10 D9 D8 0 0 0 0 0 0 0 0 Remote wakeup It returns present remote wakeup setting This bit is set or reset by SET_FEATURE or CLEAR_FEATURE request Default is value that is set to bmAttributes field in Config descriptor Self power It returns present power supply setting This bit return Self or Bus Power according to value that is set to bmAttributes field in Conf...

Page 416: ...cable endpoint is cleared Feature selector except 0 STALL state Note If it request to endpoint that is not exist it stall 3 SET_FEATURE request This request set or enables particular function bmRequestType bRequest wValue wIndex wLength Data 00000000B 00000001B 00000010B SET_ FEATURE Feature selector 0 Interface endpoint 0 None Reception side device Feature selector 1 Present remote wakeup setting...

Page 417: ...equest wValue wIndex wLength Data 10000000B GET_ DESCRIPTOR Descriptor type and Descriptor index 0 or Language ID Descriptor length Descriptor Device Device transmits device descriptor that is stored to descriptor RAM Config Config transmits config descriptor that is stored to descriptor RAM At this point it transmits not only config descriptor but also interface and endpoint descriptor String Str...

Page 418: ...P register and write 0 to EP0_EOPB bit Therefore status stage finish Transaction is same with vendor request Pleas refer to vendor request section 7 GET_CONFIGURATION request This request returns configuration value of present device bmRequestType bRequest wValue wIndex wLength Data 10000000B GET_ CONFIG 0 0 1 Configuration value If it is not configured it returns 0 If configuration it returns con...

Page 419: ...nted interface it become STALL state 11 SYNCH_FRAME request This request transmits synchronous frame of endpoint bmRequestType bRequest wValue wIndex wLength Data 10000010B SYNCH_FRAME 0 Endpoint 2 Frame No Automatically answer of this request does not support According to INT_SETUP interrupt if receiving request was discerned as SYNCH_FRAME request write data of 2byte in Frame No after it confirm...

Page 420: ... in DATASET register is 0 INT_ENDPOINT0 interrupt is can be used If writing all data finished write 0 to EP0 bit of EOP register When UDC receive it status stage finish automatically And when UDC finish status stage normally INT_STATUS interrupt is asserted If finishing status stage normally is recognized to external application manage this stage by using this interrupt signal If status stage cann...

Page 421: ...ength registers And execute transaction for each request As application access Setup_Received register after request was judged And it must inform that INT_SETUP interrupt was recognized to UDC After receiving data prepared in application access DATASET register and confirm EP0_DSET is 1 After confirming read data FIFO of endpoint 0 If receiving data more than payload write data after it confirmed...

Page 422: ...t_Vendor_Request transaction Check DATASET register Transmit judgement Total_Length Total payload WR number of payload to EP0_FIFO register Total Total payload Total payload WR number of rest data to EP0_FIFO Total 0 EP0 bit 1 EP0 bit 0 Receive except INT_STATUS Receive INT_STAS Status finish transacrion in UDC Check DATASET register Receive judgement Total_Length Total payload RD number of payloa...

Page 423: ...ss doesn t accord UDC ignores this token Endpoint field If sub channels more than two is needed in field of 4 bits it decides it function UDC can be supported endpoint except for control endpoint max 7 endpoint Token for endpoint that is permitted is ignored Frame number field Field of 11 bits is added 1 at every frame by host This field follows to SOF token that is transmitted in first of each fr...

Page 424: ...is explanation until FIFO a Bulk transfer type Bulk transfer type warrants transferring no error between host and function by using detect error and retry Basically 3 phases token data and handshake are used are used However if flow control and STALL condition data phase is changed to hand shake phase and it become to 2 phases UDC holds status of every each endpoint and it control flow control in ...

Page 425: ...urn to IDLE If data number of 1 packet is prepared to FIFO it shifts to 3 3 Data packet is generated Data packet generated by using toggle bit register in UDC Next it transfers data from FIFO of internal UDC to SIE and data packet is generated At this point it confirms transferred data number And if there is more than max payload size of each endpoint bit stuff error is generated and finish transf...

Page 426: ...ttach DATA0 DATA1 Confirm Datasize register Transmit data OK OK OK Attach CRC OK Receive ACK Wait ACK to host Normal finish transaction Clear FIFO Clear DATASET register Renew toggle bit Set STATUS to READY OK Time out Set STATUS to TX_ERR Put back addless pointer of FIFO Bit stuff error Set STATUS at STALL ConfirmToken packet PID Address Endpoint Transfer mode Error Transmit NAK Transmit STALL In...

Page 427: ...ata is transferred from SIE of internal UDC to FIFO At this point it confirms transferred data number And if there is more than max payload size of each endpoint STATUS become to STALL and state return to IDLE ACK handshake doesn t return 4 After last data was transferred and compare counted CRC with transferred CRC If it doesn t conform it sets STATUS to RX_ERR and state return to IDLE At this po...

Page 428: ...int Transfer mode Error Transmit NAK Transmit STALL Invalid Stall FIFO empty Except data PID Time out Error Generate DATA PID DATA0 DATA1 Time out Toggle check Receive data Error Confirm receiving data number Error transaction Set STATUS at RX_ERR Put back FIFO address pointer Cancel data Cancel data Error transaction Set status to stall Data communication of more than payload Retry transaction OK...

Page 429: ...e UDC operation is same with bulk transmission mode Please refer to section a b 2 Interrupt transmission mode Not toggle mode This is same bulk transmission mode basically However if ACK handshake from host is not received transaction is different After transmit data packet When ACK handshake from host is received Clear FIFO Clear DATASET register Renew toggle bit and prepare for next Set STATUS t...

Page 430: ...ame with transmission bulk transaction except case of token ID become to SETUP However control flow in UDC differ it Token SETUP Data DATA 0 Handshake ACK Control flow Below is control flow in UDC when SETUP token is received 1 SETUP token packet is received and address endpoint number and error are confirmed And it checks whether applicable endpoint is the control transfer mode 2 STATUS register ...

Page 431: ...e request is judged whether software control or hardware control if request need control in software request is informed receiving to external by asserting INT_SETUP interrupt If using hardware INT_SETUP interrupt is not asserted According to stage control flow prepare for next stage Set STATUS to DATAIN Set toggle bit to 1 Setup stage finishes by above This flow is Figure 3 16 6 8 byte data that ...

Page 432: ... transaction Set DATASET register Assert INT_SETUP and request flag According to stage flow prepare for next stage Set STATUS to DATAIN Set toggle bit to 1 OK Confirm Token packet PID Address Endpoint Transfer mode Error Invalid Except DATA0 PID Time out Error Error transaction Set STATUS to RX_ERR Put back FIFO address point Receive data Error Confirm receving data number Error more than payload ...

Page 433: ...s status stage base of control flow in control transfer type At this point CPU must write 0 to EP0 bit of EOP register in last transaction for status stage finish normally Below is detail of status stage c 3 1 IN status stage Below is IN status stage transaction format Token IN Data DATA1 0 data length NAK STALL Handshake ACK Control flow Below is transaction flow of IN status stage in UDC 1 Token...

Page 434: ...abled base on stage control flow in UDC advance next stage 2 STATUS register state is confirmed INVALID condition State return to IDLE STALL condition Data is cleared stall handshake is returned and state return to IDLE It confirm whether EOP register is accessed or not by external If it is not accessing NAK handshake is returned for continue control transfer And state return to IDLE 3 If EOP regi...

Page 435: ...There is data stage or not Data stage direction Control read transfer type is jugged control write transfer type control write transfer type No data stage by them Below are various conditions for changing stage in control transfer If receiving token for next stage from host before switching next stage from state of internal UDC NAK handshake is returned and BUSY is informed to USB host In all cont...

Page 436: ...short packet transfer in EOP register EP0 bit of DATASET register is set UDC transfers data that is set to FIFO to host by IN token interrupts When CPU finish transaction it writes 0 to EP0 bit of EOP register Change status stage in UDC 3 Receive OUT token from host Return ACK to OUT token and state change to IDLE in UDC Assert INT_STATUS interrupt to external These changing conditions are shown i...

Page 437: ...nd state change to IDLE in UDC Assert INT_STATUS interrupt to external when receive ACK for 0 data packet These changing conditions are shown in Figure 3 16 11 Figure 3 16 11 The Control Flow in UDC Control Write Transfer Type In control read transfer type transaction number of data stage do not always accord with data number that is apppointed by device request Therefore CPU can be processd by us...

Page 438: ... to UDC CPU process receiving data by device request When CPU finish transaction it writes 0 to EP0 bit of EOP register Change status stage in UDC Return data packet of 0 data to IN token and state change to IDLE in UDC Assert INT_STATUS interrupt to external when receive ACK for 0 data packet These change condition is Figure 3 16 12 Figure 3 16 12 The Control Flow in UDC Control Write Transfer Ty...

Page 439: ...in next frame Below are two conditions in FIFO of Isochronous transmission mode transferring X FIFO for storing data that transmits to host in present frame DATASET register bit 1 Y FIFO for storing data for transmitting host in next frame DATASET register bit 0 FIFO that is divided into two packet A and packet B conditions is whether X condition or Y condition Below flow is explained as X Conditi...

Page 440: ...UDC finishes normally by above transaction Packet A s FIFO can be received next data In renewed frame Packet A s FIFO interchange packet B s FIFO and transaction is used same flow If SOF token is not received by error and so on this data is lost because of frame is not renewed Nothing problem in receiving PID and if frame data is received with CRC error USB sets LOST to STATUS on FRAME register an...

Page 441: ...d Error IDLE Clear X condition A Set FULL to STATUS Set LOST to FRAME register Not renew FRAME number Assert SOF ReceiveSOF FRAME noread BANK shift BANK B transaction Assert SOF Clear transmitting FIFO BANK A in preceding frame Clear DATASET register s BANK A bit Set DATASET register s BANK B bit Finish a write in previous frame Set STATUS to READY Wait data for transmitting next frame BANK A BANK...

Page 442: ...rror is confirmed and it checks whether conform applicable endpoint transfer mode with OUT token If it doesn t conform state return to IDLE 2 Condition of status register is confirmed INVALID condition State return to IDLE 3 Data packet is received Data is transferred from SIE into the UDC to packet A s FIFO X Condition 4 After last data was transferred and compare counted CRC with transferred CRC...

Page 443: ...ame is not renewed Nothing problem in receiving PID and if frame data is received with CRC error USB sets LOST to STATUS on FRAME register and frame number is not renewed However in this case SOF is asserted and FIFO condition is renewed If SOF token is received without transmit and transfer Isochronous in frame UDC clears FIFO X Condition and sets STATUS to FULL These are shown in Figure 3 16 14 ...

Page 444: ...on A Error transaction Set STATUS to RX ERR Receive SOF Frame no read Shift BANK BANK B transaction Assert SOF Set data size received preceding frame to DATASIZE register in BANK A Set BANK A bit in DATASET register Clear BANK B bit in DATASET register Set STATUS to DATAIN But if error generate set RX_ERR Shift FIFO BANK every receive SOF Error time out exept data PID Error receiving data more tha...

Page 445: ... uses as independent FIFO Even if UDC is transmitting and receiving to USB host it can be used bus efficient by to possible load to FIFO But control transfer type receives only single packet mode Epx_SINGLE signal in dual packet mode must be fixed to 0 If this signal is fixed to 0 FIFO register runs in single mode Sample If you use endpoint 1 to dual packet of payload 64 bytes EP1_FIFO size Prepar...

Page 446: ... packet of endpoint 1 to 3 can change by setting Epx_SINGLE register When transferring don t change packet Figure 3 16 15 Receiving Sequence in Single Packet Mode IDLE DATASET register Check bit of EPx_DSET_A SIZE register Size of SIZE_A_L confirmation Size of SIZE_A_H confirmation RD receiving data of size in appricable endpoint DATASET 1 DATASET register Set bit of EPx_D SET_A Assert EPx_DATASET...

Page 447: ...d Transmission event DATASET 1 DATASET register Check bit of EPx_DSET_A Distinction transmitting EOP register WR 0 to only bit of applicable endpoint If transmitting number reach to payload applicable bit of DATASET register is set 1 Wait transmitting Finish transmitting If transmitting finish normally it clears applicable bit of DATASET Wait IN token DATASET 0 Must access to EOP register in trans...

Page 448: ...If PACKET_ACTIVE bit was set to 1 that packet is received first Packet A and packet B set data turn about always Below is this sequence Figure 3 16 17 Receiving Sequence in Dual Packet Mode IDLE DATASET register Check bit of EPx_DSET_A Check bit of EPx_DSET_B SIZE register Confirm Size of SIZE_A_L Confirm Size of SIZE_A_H Confirm Size of SIZE_B_L Confirm Size of SIZE_B_H Read size of receiving dat...

Page 449: ...vent DATASETregister Check bit of EPx_DSET_A Check bit of EPx_DSET_B Transmittind data distinction Transmitting number payload 2 Write number of transmitting number Total 0 EOP register Write 0 to only bit of applicable endpoint If transmitting number reach to payload DATASET set 1 to applicable bit of register Wait transmitting Finish transmitting If transmitting finish normally It clears applica...

Page 450: ...LL packet in a certain period it is answered by keeping EPx_EOPB signal to L level However if mode is dual packet mode EPx_DATASET signal assert L level for showing space of data Therefore data condition both data have not data cannot be confirmed from external Note NULL packet can be set also accessing EOP register Example 2 Interrupt control Interrupt signal is prepared This function use adept s...

Page 451: ...t except for it is prohibited Register name Initial value ENDPOINT STATUS EP0 40H Except for EP0 5CH 2 Detail of STATUS register Status register that was prepared every endpoint shows condition of every endpoint in UDC Each condition affects transfer various USB Condition changing in each transfer type refers to chapter 5 EPx_STATUS register value is 0 to 3 and it shows conditions of below 0 to 4 ...

Page 452: ...Y is set STATUS is BUZY until CPU finishes enumeration transaction and EP0 bit of EOP register is written 0 in UDC If CPU enumeration transaction finishes and EP0 bit of EOP register is written 0 and status stage from USB host finish normally it displays READY Please refer to 5 2 3 in chapter 5 6 STALL STALL show that endpoint is STALL condition This condition generate if it violates protocol or e...

Page 453: ...ume Way to UDC change from suspend condition to resume condition have two type resume condition output from USB host and remote wakeup When activity of bus on USB signal restore by resume condition output from USB UDC reset SUSPEND output from 1 to 0 and it resets SUSPEND bit of STATUS register from 0 And it resumed system Resume condition output from this host keep on no less than during 10 ms Th...

Page 454: ...hat supply to UDC can be controlled clock supply to USB by using USBINTFR1 INT_SUS and INT_CLKSTOP If UDC switches to suspend condition USBINTFR1 INT_SUS is set to 1 and INT_CLKSTOP is set to 1 After confirmation stop supply CLK USBCLK by setting 0 to USBCR1 USBCLKE If SUSPEND signal is set to 0 by resuming from host supply normal CLK to UDC within 3 ms When it uses remote wakeup supplying stable ...

Page 455: ...ENDPOINT0 INT_STATUS REQUEST FLAG EP0 FIFO access Request access Setup Received access IN ACK IN ACK OUT ACK EOP register access Stage error SETUP DATA0 ACK IN NAK DATA1 DATA0 DATA0 INT_SETUP INT_ ENDPOINT0 INT_STATUS REQUEST FLAG EP0 FIFO access Request access Setup Received access IN ACK IN ACK ACK EOP register access SETUP Stage error bit STATUS register read Normal Normal ...

Page 456: ...00 Standard request 0x00 0x00 FRAME_L 0x00 0x00 Request 0x00 0x00 FRAME_H 0x02 0x02 DATASET 0x00 0x00 ADRESS 0x00 0x00 Port Status 0x18 Hold EPx_SINGLE 0x00 Hold Standard request mode 0x00 Hold EPx_BCS 0x00 Hold Request mode 0x00 Hold ID_STATE 0x01 0x00 Note 1 Above initial value is value that is initialized by external reset USB_RESET This value may differs display value by various condition Plea...

Page 457: ...trol flow chart a Transaction for standard request Outline flowchart Example USB interrupt Call USBINT0 function Judge Interrupt SETUP transaction ENDPOINT 0 transaction STATUS transaction STATUS NAK transaction ENDPOINT 1 transaction ...

Page 458: ...ndition change Initialization transaction Turn on power supply Waiting USB interrupt condition Request transaction condition Receive USB token Transmit Request error S Transaction error Transmit STALL Normal finish No transaction ...

Page 459: ... request data Judge Request End Standard request CLEAR_FEATURE SET_FEATURE GET_STATUS SET_ADDRESS SET_CONFIGURATION GET_CONFIGURATION SET_INTERFACE GET_INTERFACE SYNCH_FRAME GET_DESCRIPTOR Class request Error for not support Vendor request Error for not support Error transaction ...

Page 460: ...Z26A 92CZ26A 457 c 1 CLEAR_FEATURE request transaction Start End Is request right Finish transaction Error transaction No Yes Judge Recipient Device Disable remote wakeup setting Endpoint Clear stall setting ...

Page 461: ...TMP92CZ26A 92CZ26A 458 c 2 SET_FEATURE request transaction Start End Is request right Finish transaction Error transaction No Yes Judge Recipient Device Enable remote wakeup setting Endpoint Set stall ...

Page 462: ... GET_STATUS request transaction Start End Is request right Finish transaction Error transaction No Yes Judge Recipient Interface Set 0 x 0 0 data of 2 bytes Endpoint Set stall information Device Set self power supply information ...

Page 463: ..._CONFIGRATION request transaction Start End Is request right Finish transaction Error transaction No Yes Is EP0 stall Is assignment value valid Is state valid Set assignment configuration value Clear stall flag No No No Yes Yes Yes ...

Page 464: ...TMP92CZ26A 92CZ26A 461 c 5 GET_CONFIGRATION request transaction Set present configuraion value Start End Is request right Finish transaction Error transaction No Is state valid No Yes Yes ...

Page 465: ...T_INTERFACE request transaction Start End Is request right Finish transaction Error transaction No Yes Is EP0 stall Is assignment value valid Is state valid Set each endpoint to assignmented configuration value No No No Yes Yes Yes ...

Page 466: ...CH_FRAME request transaction Start End Is request right Finish transaction Error transaction No Yes Is EP0 stall Is assignment value valid Is state valid Set altrenate setting value to present transmitting data No No No Yes Yes Yes ...

Page 467: ...464 c 8 SYNCH_FRAME request transaction c 9 SET_DESCRIPTOR request transaction Start End Is request right Finish transaction Error transaction No Yes Start End Is request right Finish transaction Error transaction No Yes ...

Page 468: ... request right Write information to FIFO EP0_fifowrite Error transaction No Yes Is EP0 stall Is assignment value valid Is state valid No No No Yes Yes Yes String Set string descriptor information Config Set config descriptor information Device Set device descriptor information ...

Page 469: ...O by EP0 Start End Is request right No Yes Stage information data stage STATUS_NAK interrupt enable Data read from FIFO All data number renew transfer address Read data from FIFO STATUS_NAK interrupt disable Stage information stataus stage Finish transaction ...

Page 470: ...ta stage STATUS_NAK interrupt enable Set data size to SIZE register All data number renew former transfer address Write data to FIFO STATUS_ NAK interrupt disable Stage information status stage Finish transaction Write data to FIFO Set transmitting size to SIZE register Yes No Is data number decided time of payload size ...

Page 471: ...microcontroller c 14 Begining setting transaction of UDC Start Set Stack point Clear vRAM USB farm initialization USB_INIT Interrupt disable Set Various interrupt UDC initialization UDC_INIT Interrupt enable Main transaction main Start End USBC reset transaction ...

Page 472: ...USB farm changing number c 16 Set DEVICE_ID data to DEVICE_ID of UDC Start End Renew stage information Renew current information Renew support information Invalid EP except EP0 Various flag Intialization Start End Set DEVICE_ID data to DEVICE_ID_RAM area ...

Page 473: ... End Set descriptor data to DESC_RAM area Start Judge Interrupt Read INT register End Judge Request transaction STATUS_judge Setup interrupt transaction Proc_SETUPINT Endpoint 0 interrupt Proc_ ENDPOINT Status_NAK interrupt Proc_STATUSNAKINT Status_interrupt Proc_STATUSINT Others Error transaction ...

Page 474: ...ms nothing therefore outline flow is skipping c 20 Request judgment transaction If transaction result is error it puts STALL command c 21 SETUP stage transaction Start End Is request right No Yes Error transaction Start End Is request right No Yes Stage information SETUP stage Request transaction ...

Page 475: ...ETUP stage c 23 Status stage interrupt transaction Start End Judge Stage Others Error transaction Status stage Finish normally Data stage GET system request EP0_fifowrite SET system request EP0_fiforead Start End Status stage Error transaction Normal finish transaction No Yes ...

Page 476: ...A 92CZ26A 473 c 24 STATUS_NAK interrupt transaction c 25 This transaction is no transaction by USB transaction perform in interrupts Start Start End Data stage Error transaction Normal finish transaction No Yes ...

Page 477: ... of standard request Start End Is config within support No Yes Get device information on descriptor Interface is within support in config present No Yes Get config information on descriptor Get device information on descriptor Increment count to next config information ...

Page 478: ...pt access to SetupReceived register After that issue STALL command after detecting INT_ENDPOINT0 interrupt c CONTROL OUT without data stage software response If STALL needs to be set for endpoint 0 judging from request after receiving INT_SETUP interrupt issue STALL command before access to eop register d CONTROL IN software response If STALL needs to be set for endpoint 0 judging from request aft...

Page 479: ... ACK UDC rejects it because the data have already received normally While if FIFO is not available UDC returns NAK and informs USB host that is unable to receive 4 If using USB device controller in TMP92CZ26A the crystal oscillator USB standard 10 MHz 2500ppm is recommended And in this case the stage of external hub can be used until max 3 stages by the precision of this USB device controller and ...

Page 480: ...e as follows 1 32 byte FIFO Transmit Receive 2 Generate CRC7 and CRC16 Transmit Receive data 3 Baud Rate 20Mbps max 4 Connect several SD cards and MMC Use other output port for SPCS pin as CS 5 Use as general clock synchronous SIO MSB LSB first 8 16bit data length rising falling edge 6 2 Interrupts INTSPITX Trans interruption INTSPIRX receive interruption Select Read Mask for interrupts RFUL TEMP ...

Page 481: ...ur final set Note2 Please use general input port or interrupt signal for WP Write Protect and CD Card Detect Figure 3 17 1 Block diagram and Connection example fSYS Baud rate Generator SPIMD CT 16bit SPCLK SPCS SPIIE 16bit SPICR SPIC SPI Controller SD Card SCLK CS Port WP Write Protect INTn CD Card Detect 100KΩ 100KΩ SPIST 16bit INTSPI 16bit SPITD Transmitt Receive ontroller SPDO 16bit SPIRD SPDI ...

Page 482: ...d to 1 Synchronous clock edge during transmitting 0 fall 1 rise Synchronous clock edge during receiving 0 fall 1 rise Invert data During transmitting 0 disable 1 enable Invert data During receiving 0 disable 1 enable Note Maximum speed of this SD card is 20Mbps in SD card SPI mode When setting the baud rates select less than 20Mbps according to the operation speed of CPU fSYS Figure 3 17 2 SPIMD r...

Page 483: ...k during receiving Please change the setting during SPIMD XEN 0 And set the same value as TCPOL Figure 3 17 5 TCPOL Register Function f TDINV Select logical invert no invert when outputs transmitted data from SPDO pin Please don t change the setting of this register when transmitting receiving is in operation g RDINV Select logical invert no invert for received data from SPDI pin Please don t chan...

Page 484: ...tially even if the data of receive buffer becomes invalid Therefore stops receive operation by writing SPICT RXE 0 after finishing to receive all the data in receiving And all the receive operation is stopped by writing SWRST 1 after checking no UNIT data in receiving namely after REND interrupt or the time to receive 1UNIT During receiving do not write SWRST 1 Software reset can be executed by 1 ...

Page 485: ...UNIT 1 Sequential Transmit control 0 disable 1 enable Alignment in Full duplex 0 disable 1 enable Receive Mode 0 UNIT 1 Sequential Receive control 0 disable 1 enable 15 14 13 12 11 10 9 8 bit Symbol CRC16_7_B CRCRX_TX_B CRCRESET_B Read Write R W After Reset 0 0 0 Function CRC select 0 CRC7 1 CRC16 CRC data 0 Transmit 1 receive CRC calculate register 0 Reset 1 Release Reset Figure 3 17 6 SPICT Regi...

Page 486: ...e 1 after write CRCRESET_B to 0 3 Write transmit data to SPITD register and wait for finish transmission all data 4 Read SPICR register and obtain the result of CRC calculation 5 Transmit CRC which is obtained in 4 by the same way as 3 CRC calculation of receive data is the same process Figure 3 17 7 Flow chart of CRC calculation process Start CRC16_7_B 1 CRCRX_TX_B 0 CRCRESET_B 0 1 Transmit all d...

Page 487: ...operation h TXMOD Select UNIT Sequential transmission During transmission it is prohibited to change the transmission mode Sequential UNIT UNIT Sequential For UNIT transmit the data in transmit FIFO is invalid TEMP interrupt generates when the data is shifted from transmit data register SPITD to transmit buffer For sequential transmit 32 bytes of the data in FIFO is valid TEMP interrupt generates ...

Page 488: ...erations as below These are selected in FDPXE RXMOD RXE TXMOD TXE registers Table 3 17 2 Transmit Receive operation mode Register setting Operation mode FDPXE TXMOD TXE RXMOD RXE Description 1 UNIT transmit 0 0 1 x x Transmit written data per UNIT 2 Sequential transmit 0 1 1 x x Transmit written data in FIFO sequentially 3 UNIT receive 0 x x 0 1 Receive only 1 UNIT of data 4 Sequential receive 0 x...

Page 489: ...equential transmit mode Writing data in transmit FIFO every 16 bytes is always needed If writing other than 16 bytes TEMP interrupt does not generate normally The written transmit data is shifted by turn with the condition SPICT TXE 1 Or shifted by turn when writing SPICT TXE 1 after writing data in transmit FIFO The transmission is kept executing as long as data exists Therefore the transmission ...

Page 490: ...ive is the mode that receiving the data sequentially and automatically when receive FIFO has space Sequential receive is selected by writing SPICT RXMOD 1 The 32 bytes size of receive FIFO becomes valid in sequential receive mode Reading the data in receive FIFO every 16 bytes is always needed If reading other than 16 bytes RFUL interrupt does not generate normally Received data is loaded to recei...

Page 491: ...at the same time has not been prepared Transmit receive start when writing the data to SPITD register with the condition TXE 1 The waveform of each transmit receive operation is as follows Note If transmit receive are not operated simultaneously please communicate with the condition FDPXE 0 Figure 3 17 8 Transmit Receive Transmitter SPCLK output SPDI input Bit1 Bit2 Bit3 Bit4 Bit0 LSB Bit5 Bit6 Bi...

Page 492: ...lock with the FIFO empty Sequential transmit mode TEMP interrupt generates from 2 phenomenon One is when the space of FIFO becomes 16 bytes size and the other 32 bytes size TEND interrupt generates when the last UNIT transmit is finished the falling edge of the last bit clock with the FIFO empty Receive interrupt RFUL Receive FIFO interrupt and REND Receive finish interrupt As for RFUL interrupt t...

Page 493: ...transmission it is set to 1 when no valid data exists in transmit buffer b TEND This bit is cleared to 0 when valid data to transmit exists in the shift register FIFO buffer or when transmission It is set to 1 when no valid data exists in the transmit data register FIFO buffer and finish transmitting all the data c REND For UNIT receiving it is set to 1 when finish receiving and valid data was loa...

Page 494: ...11 10 9 8 bit Symbol Read Write After Reset Function Figure 3 17 10 SPIIE Register a TEMPIE Set enable disable of TEMP interrupt b RFULIE Set enable disable of RFUL interrupt c TENDIE Set enable disable of TEND interrupt d RENDIE Set enable disable of REND interrupt Note As for 4 interrupts 2 transmit interrupts INTSPITX TEMP TEND and 2 receive interrupts INTSPIRX RFUL REND it should be selected o...

Page 495: ...CRC16 all bits are valid In case CRC7 lower 7 bits are valid The flow will be showed to calculate CRC16 of received data for instance by flowchart Firstly initialize CRC calculation register by writing CRCRESET_B 1 after setting CRC16_7_b 1 CRCRX_TX_B 0 CRCRESET_B 0 Next finish transmitting all bits to calculate CRC by writing data in SPITD register Please sense SPIST TEND to confirm whether recei...

Page 496: ...ata register 15 8 Figure 3 17 12 SPITD Register This bit is for writing transmitted data When read the last written data is read The data is overwritten if write next data with transmit FIFO is not empty Transmit register exist 4bytes Therefore it is possible writing by using 4byte instruction use DMA together it etc However when write data Destination address writing the data from 830 addresses i...

Page 497: ...t data with transmit FIFO is not empty Receive register exist 4bytes Therefore it is possible reading by using 4byte instruction use DMA together it etc However when read data basically read the data from 834 addresses There is exception Method of reading data instruction is restricted Please refer to following table UNIT receiving No using FIFO Sequential receiving Using FIFO Receive data read si...

Page 498: ...re not executed normally because read pointer in FIFO becomes abnormal condition Therefore manage number of reading by using software If receive is sequential reading the data from receive FIFO every 16 bytes is always needed If reading other than 16 bytes RFUL interrupt does not generate normally Note If transmitting it by except 16 byte use UNIT receiving 3 CRC CRC is generated in I O point Plea...

Page 499: ... Item Description Number of Channels 2 channels Format I 2 S format compliant Right justified and left justified formats supported Stereo monaural Master transmission only Pins used 1 I2SnCKO clock output 2 I2SnDO output 3 I2SnWS Word Select output WS frequency Data transfer rate Refer to Setting the transfer clock generator and Word Select signal Transmission buffer 64 bytes x 2 Direction of data...

Page 500: ...ontrol I2S0CTL EDGE0 TXE0 I2SCLKE0 I2S0CKO I2SWS Control I2S0CTL DTFMT01 00 WLVL0 I2S0WS 64 byte FIFO0 2 bytes 32 0 1 31 Data Selector Interrupt Control I2S0DO Read Pointer FIFO Control I2SBUF0 INTI2S0 32bit I2S0CTL DTFMT01 00 DIR0 BIT0 I2S0CTL DIR0 Shifter Internal Data Bus Write Pointer 8 bit Counter I2S0C CK07 00 I2S0C WS05 00 6 bit Counter Clock Generator 64 byte FIFO1 2 bytes 32 0 1 31 fI2S R...

Page 501: ...h left Data output clock edge 0 Falling 1 Rising Clock operation after transmis sion 0 Enable 1 Disable I2S0 Divider Value Setting Register 7 6 5 4 3 2 1 0 bit Symbol CK07 CK06 CK05 CK04 CK03 CK02 CK01 CK00 Read Write R W R W R W R W R W R W R W R W After reset 0 0 0 0 0 0 0 0 Function Divider value for CK signal 8 bit counter 15 14 13 12 11 10 9 8 Bit symbol WS05 WS04 WS03 WS02 WS01 WS00 Read Wri...

Page 502: ...der Value Setting Register 7 6 5 4 3 2 1 0 bit Symbol CK17 CK16 CK15 CK14 CK13 CK12 CK11 CK10 Read Write R W R W R W R W R W R W R W R W After reset 0 0 0 0 0 0 0 0 Function Divider value for CK signal 8 bit counter 15 14 13 12 11 10 9 8 Bit symbol WS15 WS14 WS13 WS12 WS11 WS10 Read Write R W R W R W R W R W R W After reset 0 0 0 0 0 0 Function Divider value for WS signal 6 bit counter I2S1 Buffer...

Page 503: ...tes the I2SnWS signal by dividing the I2SnCKO signal B Word Select Word Select signal I2SnWS The I2SnWS signal is used to distinguish the position of valid data and whether left data or right data is being transmitted in the I2S format This signal is clocked out in synchronization with the data transfer clock In only channel 0 this signal can be used as an AD conversion trigger signal for the ADC ...

Page 504: ... LSB Valid data Valid Data Valid Data Valid Data MSB LSB MSB LSB MSB Left justify I2SnDO Stereo Valid Data Valid Data Right Data Left Data Right justify I2SnDO Stereo I2S format I2SnDO Stereo I2SnCKO LSB MSB LSB Valid Data Monaural LSB MSB LSB MSB Valid Data Monaural MSB LSB MSB Monaural Valid Data ...

Page 505: ...quency and divider value 8 bit counter set value Divider value 00000000 256 00000001 1 11111111 255 When fSYS 60 MHz and I2SnC CKn7 0 150 the data transfer speed is set as follows I2SnCKO fSYS 150 60 MHz 150 400 kbps Note It is recommended that the value to be set in I2SnC CKn7 0 be an even number Although it is possible to set an odd number the clock duty of the CK signal does not become 50 Setti...

Page 506: ...itten to the 4 bytes 32 bits of the I2SnBUF register is written to this FIFO buffer This FIFO must be written in units of 4 bytes It is also necessary to consider the output order and to distinguish between right data and left data To write data to the I2SnBUF register be sure to use a 4 byte load instruction If a 1 byte load instruction is used invalid data will be transmitted In case of using 1 ...

Page 507: ...put order MSB first 8 bits LSB first 8 bits MSB first 16 bits LSB first 16 bits MSB first 8 bits LSB first 8 bits 2 nd Data 1 st Data 4 th Data 3 rd Data 2 nd Data 1 st Data 1 st Data 2 nd Data 1 st Data 2 nd Data 3 rd Data 4 th Data I2SnBUF register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MSB first 16 bits LSB first 16 bits Output order MSB first 8 bi...

Page 508: ...tten to the FIFO in the interrupt routine Example settings and timing diagram are shown below Example settings I2S0WS 8 KHz I2SnCKO 400 kHz data transmission on the rising edge at fSYS 50 MHz Main routine 7 6 5 4 3 2 1 0 INTEI2S01 X X 0 0 1 Set interrupt level PFCR X X PFFC X 1 1 1 Set pins PF0 I2S0CKO PF1 I2S0DO PF2 I2S0WS 1 0 0 1 0 1 1 0 Divider value N 150 I2S0SC X X 1 1 0 0 1 0 Divider value K...

Page 509: ...check the FIFO state by using the I2SnCTL TEMPn flag 2 I2SnCTL TXEn Transmission is started by setting I2SnCTL TXEn to 1 Once TXEn is set to 1 transmission is continued automatically as long as the FIFO contains the data to be transmitted While TXE is set to 1 transmission in progress the other bits in the I2SnCTL register must not be changed To stop transmission make sure that the FIFO is empty b...

Page 510: ...tor is not cleared To clear the clock generator I2SnCTL CNTEn must be set to 0 4 FIFO buffer The I2S unit is provided with a 128 byte FIFO Although it is not necessary to use all 128 bytes in the FIFO data should basically be written in units of 64 bytes using an INTI2Sn interrupt as a trigger If data is written to the FIFO without waiting for an INTI2Sn interrupt or in units other than 64 bytes i...

Page 511: ...he LCDC outputs a bus request to the CPU reads data from the display RAM converts the data as necessary and writes it to a dedicated FIFO buffer TFT support With LCD drivers supporting digital RGB input TFT an 8 to 24 bit data interface is used to realize 4096 color 65536 color 262144 color and 16777216 color display The data transfer method is the same as in the case of STN The LCDC controls LCD ...

Page 512: ... 24 bits 8 bits Maximum transfer rate VRAM read at fSYS 80 MHz 4 17 ns byte at internal RAM LCD driver data bus LD23 to LD0 pins To be connected to LCD driver data bus 8 bit mode LD7 to LD0 TFT mode LD23 to LD0 LCP0 pin Data shift clock for TFT source driver Shift clock pulse output pin 0 To be connected to column driver s CP pin The LCD driver latches the data bus value on the falling edge of thi...

Page 513: ...rizontal flip 101 Reserved 010 Vertical flip 110 Reserved 011 Horizontal vertical flip 111 Reserved LD bus inversion 0 Normal 1 Invert Auto bus inversion 0 Disable 1 Enable Valid only for TFT Interrupt selection 0 LLOAD 1 LVSYNC LFR edge 0 LHSYNC Front Edge 1 LHSYNC Rear Edge LD bus Trance Speed 0 normal 1 1 3 Note LDINV 1 inverts all output data on the LD bus However the LDIV signal that indicate...

Page 514: ...After reset 1 0 1 0 0 0 Function LCP0 phase 0 Rising 1 Falling LHSYNC phase 0 Rising 1 Falling LVSYNC phase 0 Rising 1 Falling LLOAD phase 0 Rising 1 Falling LVSYNC enable time control 00 1 clock of LHSYNC 01 2 clocks of LHSYNC 10 3 clocks of LHSYNC 11 Reserved LCD Control 2 Register 7 6 5 4 3 2 1 0 bit Symbol LGOE2P LGOE1P LGOE0P Read Write R W R W R W After reset 0 0 0 Function LGOE2 phase 0 Ris...

Page 515: ...C period bits 15 8 LCD V SYNC Pulse Register 7 6 5 4 3 2 1 0 bit Symbol LVP7 LVP6 LVP5 LVP4 LVP3 LVP2 LVP1 LVP0 Read Write W After reset 0 0 0 0 0 0 0 0 Function LVSYNC period bits 7 0 7 6 5 4 3 2 1 0 bit Symbol LVP9 LVP8 Read Write W After reset 0 0 Function LVSYNC period bits 9 8 LCD LVSYNC Pre Pulse Register 7 6 5 4 3 2 1 0 bit Symbol PLV6 PLV5 PLV4 PLV3 PLV2 PLV1 PLV0 Read Write W After reset ...

Page 516: ...k later than LLOAD LLOAD delay bits 6 0 7 6 5 4 3 2 1 0 bit Symbol OE0D6 OE0D5 OE0D4 OE0D3 OE0D2 OE0D1 OE0D0 Read Write W After reset 0 0 0 0 0 0 0 Function OE0 delay bits 6 0 7 6 5 4 3 2 1 0 bit Symbol OE1D6 OE1D5 OE1D4 OE1D3 OE1D2 OE1D1 OE1D0 Read Write W After reset 0 0 0 0 0 0 0 Function OE1 delay bits 6 0 7 6 5 4 3 2 1 0 bit Symbol OE2D6 OE2D5 OE2D4 OE2D3 OE2D2 OE2D1 OE2D0 Read Write W After ...

Page 517: ... 0 Function LGOE0 width bits 7 0 7 6 5 4 3 2 1 0 bit Symbol O1W7 O1W6 O1W5 O1W4 O1W3 O1W2 O1W1 O1W0 Read Write W After reset 0 0 0 0 0 0 0 0 Function LGOE1 width bits 7 0 7 6 5 4 3 2 1 0 bit Symbol O2W7 O2W6 O2W5 O2W4 O2W3 O2W2 O2W1 O2W0 Read Write W After reset 0 0 0 0 0 0 0 0 Function LGOE2 width bits 7 0 7 6 5 4 3 2 1 0 bit Symbol O2W9 O2W8 O1W9 O1W8 O0W8 LDW9 LDW8 HSW8 Read Write W After reset...

Page 518: ...d internal RAM as VRAM A1 signal cannot be used Every 4bytes setting is needed LCD Sub Area Start Address Register 7 6 5 4 3 2 1 0 bit Symbol LSSA7 LSSA6 LSSA5 LSSA4 LSSA3 LSSA2 LSSA1 Read Write R W R W R W R W R W R W R W After reset 0 0 0 0 0 0 0 Function LCD sub area start address A7 A1 7 6 5 4 3 2 1 0 bit Symbol LSSA15 LSSA14 LSSA13 LSSA12 LSSA11 LSSA10 LSSA9 LSSA8 Read Write R W R W R W R W R...

Page 519: ... Symbol SAHY8 Read Write R W After reset 0 Function LCD sub area HOT point 8 LCD Sub Area Display Segment Size Register 7 6 5 4 3 2 1 0 bit Symbol SAS7 SAS6 SAS5 SAS4 SAS3 SAS2 SAS1 SAS0 Read Write R W R W R W R W R W R W R W R W After reset 0 0 0 0 0 0 0 0 Function LCD sub area segment size 7 0 7 6 5 4 3 2 1 0 bit Symbol SAS9 SAS8 Read Write R W R W After reset 0 0 Function LCD sub area segment s...

Page 520: ...ry fast accesses 32 bit bus 2 1 1 1 read write it enables data transfer to the LCD driver DMA operation with the minimum CPU stop time Using the internal RAM also greatly reduces power consumption during LCD display 3 19 3 2 Display Memory Mapping Since the number of bits needed to display one pixel varies even for the same display size depending on the selected color mode the required display RAM...

Page 521: ...be used LCP0 signal Only at valid data output Always output LD23 LD0 signal Signal Name LDINV signal LVSYNC signal Enable width control Phase control LHSYNC signal LLOAD signal LGOEn signal Enable width control Phase control Delay control LFR signal FREDGE 0 Frame divide control Line Dot LLOAD signal LLOAD signal details Frame period Refresh rate Phase control Enable width control Phase control En...

Page 522: ...rlapping the current line signal The transfer speed of display data must be set to suit the refresh rate otherwise data cannot be transferred properly Set the data transfer speed so that each transfer completes within the LHSYNC period Maximum speed If the LCP0 period is too short the data to be transferred to the LCD driver cannot be prepared in time causing wrong data to be transferred The maxim...

Page 523: ... 1 wait STN 256 color Refresh cycle 70 Hz fSYS 2 to fSYS 16 fSYS 2 to fSYS 16 fSYS 4 to fSYS 16 fSYS 8 to fSYS 16 up to 2 waits fSYS 16 up to 6 waits STN 4K color Refresh cycle 70 Hz fSYS 2 to fSYS 16 fSYS 2 to fSYS 16 fSYS 4 to fSYS 16 fSYS 4 to fSYS 16 up to 2 waits fSYS 8 to fSYS 16 up to 6 waits fSYS 16 up to 14 waits TFT 4K color Refresh cycle 70 Hz fSYS 2 to fSYS 16 fSYS 2 To fSYS 16 fSYS 2 ...

Page 524: ...ODE3 MODE2 MODE1 MODE0 Read Write R W R W R W R W R W R W R W R W After reset 0 0 1 1 0 0 0 0 Function Display RAM 00 Internal RAM 32 bit 01 External SRAM 10 SDRAM 11 Reserved LD bus transfer speed SCPW2 0 00 2 clk 01 4 clk 10 8 clk 11 16 clk SCPW2 1 00 6 clk 01 12 clk 10 24 clk 11 48 clk Mode selection 0000 Reserved 1000 Reserved 0001 SR mono 1001 Reserved 0010 SR 4 gray 1010 TFT 256 color 0011 R...

Page 525: ... width 0 At setting in register 1 At valid data only LCDC operation 0 Stop 1 Start Note When select STN mode LCP0 is output at valid data only regardless of the setting of LCP0OC bit The phase of the LCP0 signal can be inverted by the setting of LCDCTL1 LCP0P LCD Control 1 Register 7 6 5 4 3 2 1 0 bit Symbol LCP0P LHSP LVSP LLDP LVSW1 LVSW0 Read Write R W R W R W R W R W R W After reset 1 0 1 0 0 ...

Page 526: ... LH15 LH14 LH13 LH12 LH11 LH10 LH9 LH8 Read Write W After reset 0 0 0 0 0 0 0 0 Function LHSYNC period bits 15 8 The period of the vertical synchronization signal LVSYNC is defined as the product of the value set in LCDVSP LV9 0 and the LHSYNC period The value to be set in LCDVSP LV9 0 is obtained as follows TFT Common size number of dummy clocks STN Common size number of dummy clocks A minimum of...

Page 527: ...transfer times 2 LHSYNC LCP0 pulse count Note 2 The vertical back porch must have a minimum of one dummy clock TFT driver The recommended number of dummy clocks is specified by each TFT driver or LCD module Refer to the specifications of the TFT driver LCD module to be used STN driver For an STN driver the refresh rate can be set accurately by adjusting the value of the horizontal back porch If th...

Page 528: ...t size front dummy LCP0 LDD6 0 Note 1 The back dummy LCP0 horizontal back porch must have a minimum of two LCP0 clocks Note 2 The delay time that is set in LCDLDDLY LDD6 0 is counted based on LHSYNC with 0 delay 7 6 5 4 3 2 1 0 bit Symbol PDT LDD6 LDD5 LDD4 LDD3 LDD2 LDD1 LDD0 Read Write R W W After reset 0 0 0 0 0 0 0 0 Function Data output timing 0 Sync with LLOAD 1 1 clock later than LLOAD LLOA...

Page 529: ...d by the LCDC This section explains how to control each of these signals LCP0 signal LD23 LD0 signal LCP0 signal Signal Name LDINV signal LVSYNC signal LHSYNC signal FR signal LLOAD signal LLOAD signal LGOEn signal Front dummy LHSYNC Vertical front porch Back dummy LHSYNC Vertical back porch Valid LHSYNC Common size ...

Page 530: ...Write W After reset 0 0 0 0 0 0 0 0 Function LVSYNC period bits 7 0 7 6 5 4 3 2 1 0 bit Symbol LVP9 LVP8 Read Write W After reset 0 0 Function LVSYNC period bits 9 8 The enable width of the LVSYNC signal can be specified as 1 clock 2 clocks or 3 clocks of LHSYNC in LCDCTL1 LVSW1 0 The phase of the LVSYNC signal can be inverted by the setting of LCDCTL1 LVSP LCD Control 1 Register 7 6 5 4 3 2 1 0 b...

Page 531: ... Monochrome grayscale Segment size 8 number of dummy clocks Color Segment size 3 8 number of dummy clocks LHSYNC s period LCP0 s period LH15 0 1 LCD LHSYNC Pulse Register 7 6 5 4 3 2 1 0 bit Symbol LH7 LH6 LH5 LH4 LH3 LH2 LH1 LH0 Read Write W After reset 0 0 0 0 0 0 0 0 Function LHSYNC period bits 7 0 7 6 5 4 3 2 1 0 bit Symbol LH15 LH14 LH13 LH12 LH11 LH10 LH9 LH8 Read Write W After reset 0 0 0 0...

Page 532: ...e pulse of the LCP0 clock LCDHSW Register 7 6 5 4 3 2 1 0 bit Symbol HSW7 HSW6 HSW5 HSW4 HSW3 HSW2 HSW1 HSW0 Read Write W After reset 0 0 0 0 0 0 0 0 Function LHSYNC width bits 7 0 7 6 5 4 3 2 1 0 bit Symbol O2W9 O2W8 O1W9 O1W8 O0W8 LDW9 LDW8 HSW8 Read Write W After reset 0 0 0 0 0 0 0 0 Function LGOE2 width bits 9 8 LGOE1 width bits 9 8 LGOE0 width bit 8 LLOAD width bits 9 8 LHSYNC width bit 8 LC...

Page 533: ... LCD Control 1 Register 7 6 5 4 3 2 1 0 bit Symbol LCP0P LHSP LVSP LLDP LVSW1 LVSW0 Read Write R W R W R W R W R W R W After reset 1 0 1 0 0 0 Function LCP0 phase 0 Rising 1 Falling LHSYNC phase 0 Rising 1 Falling LVSYNC phase 0 Rising 1 Falling LLOAD phase 0 Rising 1 Falling LVSYNC enable time control 00 1 clock of LHSYNC 01 2 clocks of LHSYNC 10 3 clocks of LHSYNC 11 Reserved LCP0 signal Signal ...

Page 534: ...Y register data output is also delayed Also note that when LCDLDDLY PDT 1 data is output one LCP0 clock later than the LLOAD signal LCDLDDLY PDT 0 Data is output in synchronization with the LLOAD signal LCDLDDLY PDT 1 Data is output one LCP0 clock later than the LLOAD signal The delay time for the LLOAD signal is controlled based on LCDLDDLY PDT 1 Therefore even if the delay time is set to 0 with ...

Page 535: ...ed depending on the LCDCTL0 LCP0OC setting as shown below LCDCTL0 LCP0OC 0 Output at setting value in LCDDLW LDW9 0 LCDCTL0 LCP0OC 1 Output at valid data LCD Control 0 Register 7 6 5 4 3 2 1 0 bit Symbol PIPE ALL0 FRMON DLS LCP0OC START Read Write R W R W R W R W R W R W R W After reset 0 0 0 0 0 0 0 Function PIP function 0 Disable 1 Enable Segment data 0 Normal 1 Always output 0 Frame divide sett...

Page 536: ...T 0 LCDLDW Register 7 6 5 4 3 2 1 0 bit Symbol LDW7 LDW6 LDW5 LDW4 LDW3 LDW2 LDW1 LDW0 Read Write W After reset 0 0 0 0 0 0 0 0 Function LLOAD width bits 7 0 7 6 5 4 3 2 1 0 bit Symbol O2W9 O2W8 O1W9 O1W8 O0W8 LDW9 LDW8 HSW8 Read Write W After reset 0 0 0 0 0 0 0 0 Function LGOE2 width bits 9 8 LGOE1 width bits 9 8 LGOE0 width bit 8 LLOAD width bits 9 8 LHSYNC width bit 8 When LCDCTL0 LCP0OC 1 the...

Page 537: ...iming 0 Sync with LLOAD 1 1 clock later than LLOAD LLOAD delay bits 6 0 The phase of the LLOAD signal can be inverted by the setting of LCDCTL1 LLDP LCD Control 1 Register 7 6 5 4 3 2 1 0 bit Symbol LCP0P LHSP LVSP LLDP LVSW1 LVSW0 Read Write R W R W R W R W R W R W After reset 1 0 1 0 0 0 Function LCP0 phase 0 Rising 1 Falling LHSYNC phase 0 Rising 1 Falling LVSYNC phase 0 Rising 1 Falling LLOAD ...

Page 538: ... After reset 0 0 0 0 0 0 0 0 Function LGOE1 width bits 7 0 7 6 5 4 3 2 1 0 bit Symbol O2W7 O2W6 O2W5 O2W4 O2W3 O2W2 O2W1 O2W0 Read Write W After reset 0 0 0 0 0 0 0 0 Function LGOE2 width bits 7 0 7 6 5 4 3 2 1 0 bit Symbol O2W9 O2W8 O1W9 O1W8 O0W8 LDW9 LDW8 HSW8 Read Write W After reset 0 0 0 0 0 0 0 0 Function LGOE2 width bits 9 8 LGOE1 width bits 9 8 LGOE0 width bit 8 LLOAD width bits 9 8 LHSYN...

Page 539: ...D6 OE1D5 OE1D4 OE1D3 OE1D2 OE1D1 OE1D0 Read Write W After reset 0 0 0 0 0 0 0 Function OE1 delay bits 6 0 7 6 5 4 3 2 1 0 bit Symbol OE2D6 OE2D5 OE2D4 OE2D3 OE2D2 OE2D1 OE2D0 Read Write W After reset 0 0 0 0 0 0 0 Function OE2 delay bits 6 0 LCP0 signal Signal Name LVSYNC signal LHSYNC signal Internal reference signal LGOE0 signal Delay control LCDO0DLY 0291H LCDO1DLY 0292H LCDO2DLY 0293H ...

Page 540: ... 6 5 4 3 2 1 0 bit Symbol LGOE2P LGOE1P LGOE0P Read Write R W R W R W After reset 0 0 0 Function LGOE2 phase 0 Rising 1 Falling LGOE1 phase 0 Rising 1 Falling LGOE0 phase 0 Rising 1 Falling Phase control LGOEnP 0 LGOEnP 1 LGOEn signal LCDCTL2 0287H ...

Page 541: ...DLS 0 and FREDGE 0 LFR signal synchronous with front edge of LHSYNC signal and when DLS 0 and FREDGE 1 LFR signal synchronous with rear edge of LHSYNC signal When LCDCTL0 FRMON is set to 0 to disable the frame divide function the LFR signal is inverted in synchronization with the LVSYNC period Enabling this function does not affect the waveform and timing of the LVSYNC signal The refresh rate is n...

Page 542: ...s inverted at intervals of LCP0 M The M value is specified in LCDDVM0 FMP7 4 When DLS 1 LFR signal synchronous with front edge of LHSYNC signal So prohibit to set FREDGE 1 always need to set FREDGE 0 LVSYNC LHSYNC LHSYNC Expansion LCP0 M M N LFR FREDGE 0 FRMON 1 FMP7 0 N FML7 0 M DLS 1 Note prohibit to set FREDGE 1 always need to set FREDGE 0 ...

Page 543: ...t valid data only LLOAD width 0 At setting in register 1 At valid data only LCDC operation 0 Stop 1 Start Note When select STN mode LCP0 is output at valid data only regardless of the setting of LCP0OC bit Divide FRM 0 Register 7 6 5 4 3 2 1 0 bit Symbol FMP3 FMP2 FMP1 FMP0 FML3 FML2 FML1 FML0 Read Write R W After reset 0 0 0 0 0 0 0 0 Function LCP0 DVM bits 3 0 M LHSYNC DVM bits 3 0 N 7 6 5 4 3 2...

Page 544: ...e When SDRAM is used additional 9 clocks are needed as overhead time for reading each common line data When internal RAM is used additional 1 clock is needed as overhead time for reading each common line data Additional 1 clock of overhead time is also needed when a change of blocks occur in the internal RAM even if the common line remains the same The time the CPU stops operating while data for o...

Page 545: ...ata 2 bit memory data Display Memory LD Bus Output 8 bit type LD0 1 0 17 16 LD1 3 2 19 18 LD2 5 4 21 20 LD3 7 6 23 22 LD4 9 8 25 24 LD5 11 10 27 26 LD6 13 12 29 28 LD7 15 14 31 30 Figure 3 19 2 Memory Map Image and Data Output in STN Monochrome 4 Grayscale Mode Address 0 Address 1 Address 2 Address 3 LSB MSB D0 D31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 ...

Page 546: ... 55 52 LD6 27 24 59 56 LD7 31 28 63 60 Figure 3 19 3 Memory Map Image and Data Output in STN 8 16 Grayscale Mode Address 0 Address 1 Address 2 Address 3 LSB MSB D0 D31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Address 4 Address 5 Address 6 Address 7 LSB MSB D0 D31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 6...

Page 547: ...Data Output in STN 64 Grayscale Mode Address 0 Address 1 Address 2 Address 3 LSB MSB D0 D31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Address 4 Address 5 Address 6 Address 7 LSB MSB D0 D31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 Address 8 Address 9 Address 10 Address 11 LSB MSB D0 D31 64 65 66 67 68...

Page 548: ... 18 16 R2 39 38 B4 LD7 21 19 G2 42 40 R5 Figure 3 19 5 Memory Map Image and Data Output in STN 256 Color Mode Address 0 Address 1 Address 2 Address 3 LSB MSB D0 D31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R0 G0 B0 R1 G1 B1 R2 G2 B2 R3 G3 B3 Address 4 Address 5 Address 6 Address 7 LSB MSB D0 D31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 5...

Page 549: ... 24 R2 59 56 B4 LD7 31 28 G2 63 60 R5 Figure 3 19 6 Memory Map Image and Data Output in STN 4096 Color Mode Address 0 Address 1 Address 2 Address 3 LSB MSB D0 D31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R0 G0 B0 R1 G1 B1 R2 G2 Address 4 Address 5 Address 6 Address 7 LSB MSB D0 D31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 ...

Page 550: ...B0 19 B1 Figure 3 19 7 Memory Map Image and Data Output in TFT 256 Color Mode Address 0 Address 1 Address 2 Address 3 LSB MSB D0 D31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R0 G0 B0 R1 G1 B1 R2 G2 B2 R3 G3 B3 Address 4 Address 5 Address 6 Address 7 LSB MSB D0 D31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 ...

Page 551: ...0 B1 LD9 9 B0 21 B1 LD10 10 B0 22 B1 LD11 11 B0 23 B1 Figure 3 19 8 Memory Map Image and Data Output in TFT 4096 Color Mode Address 0 Address 1 Address 2 Address 3 LSB MSB D0 D31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 R0 G0 B0 R1 G1 B1 R2 G2 Address 4 Address 5 Address 6 Address 7 LSB MSB D0 D31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50...

Page 552: ...B0 27 B1 LD12 12 B0 28 B1 LD13 13 B0 29 B1 LD14 14 B0 31 B1 LD15 15 B0 32 B1 Figure 3 19 9 Memory Map Image and Data Output in TFT 65536 Color Mode Address 4 Address 5 Address 6 Address 7 LSB MSB D0 D31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 R2 G2 B2 R3 G3 B3 Address 0 Address 1 Address 2 Address 3 LSB MSB D0 D31 0 1 2 3 4 5 6 7 8 9 10 11 12...

Page 553: ...1 LD23 17 B0 41 B1 LD12 18 B0 42 B1 LD12 18 B0 42 B1 LD13 19 B0 43 B1 LD13 19 B0 43 B1 LD14 20 B0 44 B1 LD14 20 B0 44 B1 LD15 21 B0 45 B1 LD15 21 B0 45 B1 LD16 22 B0 46 B1 LD16 22 B0 46 B1 LD17 23 B0 47 B1 LD17 23 B0 47 B1 Note The display RAM data format for 18 bpp is the same as that for 24 bpp When 18 bpp is used the least significant bit should be disabled by port setting Figure 3 19 10 Memory...

Page 554: ... been transferred and the data to be transferred next are compared If there are more changed bits than unchanged bits for example 7 or more bits are changed when using a 12 bit bus and 5 or more bits are changed when using a 8 bit bus the data is inverted and the LDIV signal is also driven high This function can be used with TFT source drivers having the data inversion function to reduce radiated ...

Page 555: ...s given priority Thus CPU accepts interrupt immediately after reading the data from VRAM LCDMODE1 Register 7 6 5 4 3 2 1 0 bit Symbol LDC2 LDC1 LDC0 LDINV AUTOINV INTMODE FREDGE SCPW2 Read Write R W R W R W R W R W R W W W After reset 0 0 0 0 0 0 0 0 Function Data rotation function Supported for 64K color 16 bps only 000 Normal 100 90 degree 001 Horizontal flip 101 Reserved 010 Vertical flip 110 R...

Page 556: ...and start address are specified as in the case of the normal screen display For the sub screen the display size and start address are also specified for determining the position and size of the sub screen When the HOT point upper left corner and segment common size are set for the sub screen and the PIP function is enabled by setting LCDCTL0 PIPE to 1 the sub screen is displayed over the main scre...

Page 557: ...s on the bit width of the external RAM to be used When the internal RAM is used VRAM is always accessed via a 32 bit bus Note 2 The same RAM must be used for both the main and sub areas The table below shows the HOT point segment and common sizes that can be specified Segment size VRAM Access Minimum size units Common size 16bit 32 dots In units of 16 dots Monochrome display 32bit 64 dots In units...

Page 558: ...W R W After reset 0 1 0 0 0 0 0 0 Function LCD main area start address A23 A16 LCD Sub Area Start Address Register 7 6 5 4 3 2 1 0 bit Symbol LSSA7 LSSA6 LSSA5 LSSA4 LSSA3 LSSA2 LSSA1 Read Write R W R W R W R W R W R W R W After reset 0 0 0 0 0 0 0 Function LCD sub area start address A7 A1 7 6 5 4 3 2 1 0 bit Symbol LSSA15 LSSA14 LSSA13 LSSA12 LSSA11 LSSA10 LSSA9 LSSA8 Read Write R W R W R W R W R...

Page 559: ...t Symbol SAHY8 Read Write R W After reset 0 Function LCD sub area HOT point 9 8 Note The HOT point should be set in units of the specified number of dots which is determined by the display color mode and display RAM access data bus width LCD Sub Area Display Segment Size Register 7 6 5 4 3 2 1 0 bit Symbol SAS7 SAS6 SAS5 SAS4 SAS3 SAS2 SAS1 SAS0 Read Write R W R W R W R W R W R W R W R W After res...

Page 560: ...C5 SAC4 SAC3 SAC2 SAC1 SAC0 Read Write R W R W R W R W R W R W R W R W After reset 0 0 0 0 0 0 0 0 Function LCD sub area common size 7 0 7 6 5 4 3 2 1 0 bit Symbol SAC8 Read Write R W After reset 0 Function LCD sub area common size 8 Note The common size should be set in units of 1 line 02AFH LSACS 02AEH ...

Page 561: ... display RAM image shown above uses the data scan method for the normal display screen so that data is read from the display RAM and written to the LCDD from left to right and top to bottom The data on the LCD screen appears as horizontally flipped if data is read from the display RAM from left to right and top to bottom and written to the LCDD from right to left and top to bottom Likewise the dat...

Page 562: ...above shows typical data of QVGA size 320 segments 240 commons landscape type If the LCDD to be used is of landscape type the data can be written to the LCDD without any problem If the LCDD to be used is of portrait type 240 segments 320 commons the data cannot be displayed properly This function enables the orientation of each display image to be rotated 90 degrees without the need to change the ...

Page 563: ...YNC LFR edge 0 LHSYNC Front Edge 1 LHSYNC Rear Edge LD bus Trance Speed 0 normal 1 1 3 Note The LDC2 0 setting must not be changed while the LCDC is operating Be sure to set LCDCTL0 START to 0 to stop the LCDC operation before changing LDC2 0 When the horizontal and vertical flip function or 90 degree rotation function is used the display RAM start address of main sub area should be set differentl...

Page 564: ...river LCD panel and frame frequency to be used It is therefore recommended that operation checks be performed under the actual conditions 2 The LCDMODE1 LDC2 0 setting must not be changed while the LCDC is operating Be sure to set LCDCTL0 START to 0 to stop the LCDC operation before changing LDC2 0 3 The LCDC obtains the bus from the CPU when it has some operation to perform Since the TMP92CZ26A i...

Page 565: ...SS TEST DUAL VCCLR V0LR V2LR VSSLR V3LR V5LR LVSYNC EIO1 EIO2 open VDD VDD TEST Di7 Di0 VSS VCCL R V0L R V1L R V4L R V5L R T6C13B 240 row Driver T6C13B 240 column Driver TMP92CZ26 Note The LCD drive power for LCD display must be supplied from an external circuit port DI7 DI0 DSPOF DIR VSS DUAL SCP S C VSS COM001 COM240 SEG001 SEG240 240COM 80SEG LCD Color Panel Figure 3 19 11 STN Type LCD Driver C...

Page 566: ...6L78 AS 162 gate Driver JBT6L77 AS 2 80 RGB Source Driver 92CZ26 LHSYNC DA5 0 CPV TEST1 U D OE3 1 LGOE2 0 Display M emory SDRAM or SRAM D15 D0 D15 D0 Note The LCD drive power for LCD display must be supplied from and external circuit A0 A23 Axx Axx Control Signal Control Signal SA1 SB1 SC1 SA80 SB80 SC80 CPH LOAD DO I DA5 2 DI O DC5 2 U D VDD VSS DA1 0 DB1 0 DC1 0 DB5 2 SA81 SB81 SC81 SA160 SB160 ...

Page 567: ...TSICR0 and TSICR1 and using an internal AD converter 3 20 1 Touch Screen Interface Module Internal External Connection Figure 3 20 1External connection of TSI Figure 3 20 2 Internal block diagram of TSI External Capacitors MY MX PY PX TMP92CZ26A Y Y Touch Screen X X AVSS P96 INT4 PX P97 PY VREFH VREFL PXEN PYEN MXEN MYEN AN3 AN2 PG3 AN3 MY AVCC PG2 AN2 MX VREFH VREFL AVCC AVSS AD converter Touch s...

Page 568: ...nternal clock is used for de bounce circuit when IDLE1 STOP mode or PCM condition the de bounce circuit don t operate and also interrupt which through this circuit is not generated When IDLE1 STOP mode or PCM condition set this circuit to disable Write 0 to TSICR1 DBC7 before entering HALT state If de bounce time is set to 0 signal is received after counting the 6 system clock fSYS from the condit...

Page 569: ...ster PXD and INT4 isn t generated When pen was touched the internal resistors of X and Y direction are connected Therefore P96 INT4 PX pin s level is set to High by internal pull down register PXD and INT4 is generated And the de bounce circuit is prepared for avoiding that INT4 of plural times generate by one time touch When de bounce time is set to TSICR1 register the pulse of time less than its...

Page 570: ...6 INT4 pin Start the counter for de bounce time de bounce time de bounce time INT4 is generated by matching counter and specified de bounce time After pen is de touched INT4 can be issued again de bounce time INT4 isn t generated by matching counter and specified de bounce time because of it is an edge type interrupt ...

Page 571: ...utted to AN3 or AN2 pin can be calculated It is a ratio between resistance value in TMP92CZ26A and resistance value in touch screen shown in Figure 3 20 5 Therefore if the pen touches a corner area on touch screen analog voltage will not be to 3 3V or 0 0V As a notice since each resistor has an uneven consider about it And it is recommended that an average code among a few times AD conversion will...

Page 572: ...tine TSICR0 98H TSICR1 XXH voluntary 1 Touch Detection Procedure INT4 Routine 2 X Y Position Measurement Procedure Yes No Return to Main Routine Main Routine X position measurement TSICR0 C5H AD conversion for AN3 Store the result Y position measurement TSICR0 CAH AD conversion for AN2 Store the result Execute an operation By using X Y position Still touched TSICR0 PTST 1 a b c ...

Page 573: ...rupt level of INT4 tsicr0 98h Pull down resistor on SPY on Interrupt set TWIEN ei Enable interrupt X AVSS PX P96 INT4 PY P97 VREFH VREFL PXEN PYEN MXEN MYEN AN3 AN2 MY PG3 AVCC MX PG2 VREFH VREFL AVCC AVSS AD Converter Touch screen control TSI7 SPY SPX SMX SMY PXD typ 50kΩ Dec INT4 PTST Internal data bus Y Y Touch Screen X TMP92CZ26A ON ON ...

Page 574: ...e of P97 P96 to OFF admod1 b0h Set to AN3 admod0 08h Start AD conversion AVSS PX P96 INT4 PY P97 VREFH VREFL PXEN PYEN MXEN MYEN AN3 AN2 MY PG3 AVCC MX PG2 VREFH VREFL AVCC AVSS AD Converter Touch screen control TSI7 SPY SPX SMX SMY PXD typ 50kΩ Dec INT4 PTST Internal data bus Y Y Touch Screen X X TMP92CZ26A ON ON ...

Page 575: ...e of P97 P96 to OFF admod1 a0h Set to AN2 admod0 08h Start AD conversion AVSS PX P96 INT4 PY P97 VREFH VREFL PXEN PYEN MXEN MYEN AN3 AN2 MY PG3 AVCC MX PG2 VREFH VREFL AVCC AVSS AD Converter Touch screen control TSI7 SPY SPX SMX SMY PXD typ 50kΩ Dec INT4 PTST Internal data bus Y Y Touch Screen X X TMP92CZ26A ON ON ...

Page 576: ...1 STOP or PCM mode by using TSI set the de bounce circuit to disable before a condition become to HALT or PCM mode TSICR1 DBC7 0 2 Port setting During conversion the middle voltage of 0V AVcc by using AD converter the middle voltage is inputted to a normal C MOS input gate P96 and P97 too Therefore provide the flow current for P96 and P97 by using TSICR0 INGE In this case TSICR0 INGE 1 when the in...

Page 577: ...ystem to use it please manage upper two columns with the system side when handle year column in the Christian era Note2 Leap year A leap year is the year which is divisible with 4 but the year which there is exception and is divisible with 100 is not a leap year However the year is divisible with 400 is a leap year But there is not this product for the correspondence to the above exception Because...

Page 578: ...ter W R W RESTR 1328H 1Hz enable 16Hz enable Clock reset Alarm reset Always write 0 Reset register W only Note As for SECR MINR HOURR DAYR MONTHR YEARR of PAGE0 current state is read read it Table 3 21 2 PAGE1 Alarm function registers Symbol Address Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Function Read Write SECR 1320H R W MINR 1321H 40 min 20 min 10 min 8 min 4 min 2 min 1 min Minute column R W H...

Page 579: ...c column 20 sec column 10 sec column 8 sec column 4 sec column 2 sec column 1 sec column 0 0 0 0 0 0 0 0 sec 0 0 0 0 0 0 1 1 sec 0 0 0 0 0 1 0 2 sec 0 0 0 0 0 1 1 3 sec 0 0 0 0 1 0 0 4 sec 0 0 0 0 1 0 1 5 sec 0 0 0 0 1 1 0 6 sec 0 0 0 0 1 1 1 7 sec 0 0 0 1 0 0 0 8 sec 0 0 0 1 0 0 1 9 sec 0 0 1 0 0 0 0 10 sec 0 0 1 1 0 0 1 19 sec 0 1 0 0 0 0 0 20 sec 0 1 0 1 0 0 1 29 sec 0 1 1 0 0 0 0 30 sec 0 1 1 ...

Page 580: ...n column 0 0 0 0 0 0 0 0 min 0 0 0 0 0 0 1 1 min 0 0 0 0 0 1 0 2 min 0 0 0 0 0 1 1 3 min 0 0 0 0 1 0 0 4 min 0 0 0 0 1 0 1 5 min 0 0 0 0 1 1 0 6 min 0 0 0 0 1 1 1 7 min 0 0 0 1 0 0 0 8 min 0 0 0 1 0 0 1 9 min 0 0 1 0 0 0 0 10 min 0 0 1 1 0 0 1 19 min 0 1 0 0 0 0 0 20 min 0 1 0 1 0 0 1 29 min 0 1 1 0 0 0 0 30 min 0 1 1 1 0 0 1 39 min 1 0 0 0 0 0 0 40 min 1 0 0 1 0 0 1 49 min 1 0 1 0 0 0 0 50 min 1 ...

Page 581: ...lock 0 1 0 0 0 0 10 o clock 0 1 1 0 0 1 19 o clock 1 0 0 0 0 0 20 o clock 1 0 0 0 1 1 23 時 Note Do not set the data other than showing above 2 In case of 24 hour clock mode MONTHR MO0 0 7 6 5 4 3 2 1 0 Bit symbol HO5 HO4 HO3 HO2 HO1 HO0 HOURR 1322H Read Write R W After reset Undefined Function 0 is read PM AM 10 hour column 8 hour column 4 hour column 2 hour column 1 hour column 0 0 0 0 0 0 0 o cl...

Page 582: ...ジスタ PAGE0 1 7 6 5 4 3 2 1 0 Bit symbol DA5 DA4 DA3 DA2 DA1 DA0 DATER 1324H Read Write R W After reset Undefined Function 0 is read Day 20 Day 10 Day 8 Day 4 Day 2 Day 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1st day 0 0 0 0 1 0 2nd day 0 0 0 0 1 1 3rd day 0 0 0 1 0 0 4th day 0 0 1 0 0 1 9th day 0 1 0 0 0 0 10th day 0 1 0 0 0 1 11th day 0 1 1 0 0 1 19th day 1 0 0 0 0 0 20th day 1 0 1 0 0 1 29th day 1 1 0 0 0 0 ...

Page 583: ... 0 0 1 January 0 0 0 1 0 February 0 0 0 1 1 March 0 0 1 0 0 April 0 0 1 0 1 May 0 0 1 1 0 June 0 0 1 1 1 July 0 1 0 0 0 August 0 1 0 0 1 September 1 0 0 0 0 October 1 0 0 0 1 November 1 0 0 1 0 December Note Do not set the data other than showing above 7 Select 24 hour clock or 12 hour clock for PAGE1 only 7 6 5 4 3 2 1 0 Bit symbol MO0 MONTHR 1325H Read Write R W After reset Undefined Function 0 ...

Page 584: ... 0 0 0 0 0 0 1 1 03 years 0 0 0 0 0 1 0 0 04 years 0 0 0 0 0 1 0 1 05 years 1 0 0 1 1 0 0 1 99 years Note Do not set the data other than showing above 9 Leap year register for PAGE1 only 7 6 5 4 3 2 1 0 Bit symbol LEAP1 LEAP0 YEARR 1326H Read Write R W After reset Undefined Function 0 is read 00 leap year 01 one year after leap year 10 two years after leap year 11 three years after leap year 0 0 C...

Page 585: ... Select Page0 PAGE 1 Select Page1 0 Don t care ADJUST 1 Adjust sec counter When set this bit to 1 the sec counter become to 0 when the value of sec counter is 0 29 And in case that value of sec counter is 30 59 min counter is carried and become sec counter to 0 Output Adjust signal during 1 cycle of fSYS After being adjusted once Adjust is released automatically PAGE0 only 11 Reset register for PA...

Page 586: ... when carry of the inside counter happens during the operation which clock data reads Therefore please read two times with the following way for reading correct data Figure 3 21 2 Flowchart of timer data read Start END PAGER PAGE 0 Select PAGE0 Read the clock data 1st Read the clock data 2nd 1st data 2nd data NO YES ...

Page 587: ...nterrupt read clock data within 0 5s s after generating interrupt This is because count up of clock data occurs by rising edge of 1Hz pulse cycle Figure 3 21 3 Timing of INTRTC and Clock data 56 57 58 59 0 1 2 3 4 ALARM INTRTC 1s counter Internal signal 1s count UP Internal signal ...

Page 588: ...llow the below way 1 Resetting a divider In RTC inside there are 15 stage dividers which generates 1Hz clock from 32 768 KHz Carry of a timer is not done for one second when reset this divider So write in data at this interval Figure 3 21 4 Flowchart of data write Start End PAGER PAGE 0 Select PAGE0 RESTR RSTTMR 1 Divider reset Write the clock data Note This period is within 0 5 secound ...

Page 589: ...divider After becoming timer enable state output the carry signal to timer and revise time and continue operation However timer is late when timer disabling state continues for one second or more During timer disabling pay attention with system power is downed In this case the timer is stopped and time is delayed Figure 3 21 5 Flowchart of Clock disable Start End Disable the clock Read the clock d...

Page 590: ...etting alarm min alarm hour alarm day and alarm the day week are done by writing in data at each register of PAGE1 When all setting contents accorded RTC generates INTRTC interrupt if PAGER INTENA ENAALM is 1 However contents don t care state which does not set it up is considered to always accord The contents which set it up once cannot be returned to don t care state in independence Initializati...

Page 591: ...tting up PAGER ENAALM 0 RESTR DIS1HZ 0 DIS16HZ 1 And RTC generates INTRC interrupt by falling edge of the clock 3 When output clock of 16Hz RTC outputs clock of 16Hz to ALARM pin by setting up PAGER ENAALM 0 RESTR DIS1HZ 1 DIS16HZ 0 And RTC generates INTRC interrupt by falling edge of the clock ...

Page 592: ... connecting a loud speaker outside Melody tone can easily sound 2 Alarm generator The Alarm function generates eight kinds of alarm waveform having a modulation frequency 4096Hz determined by the low speed clock 32 768 KHz And this waveform is able to invert by setting a value to a register By connecting a loud speaker outside Alarm tone can easily sound Five kinds of fixed cycles 1Hz 2Hz 64Hz 512...

Page 593: ...M4E 0E 15bit conter UC1 8bit counter UC2 Alarm wave form generator ALM register Invert MELALMC ALMINV Selector ALMOUT MELOUT MELALMC FC1 0 Internal data bus Reset MELFH MELON Stop and Clear Low speed clock Invert MELOUT Alarm Generator Internal data bus Reset INTALM0 8192Hz INTALM1 512 Hz INTALM2 64 Hz INTALM3 2 Hz INTALM4 1 Hz MLDALM pin 4096 Hz Clear MELALMC MELALM INTALM ...

Page 594: ...er is running FC1 0 is kept 01 MELFL register 7 6 5 4 3 2 1 0 bit Symbol ML7 ML6 ML5 ML4 ML3 ML2 ML1 ML0 Read Write R W After reset 0 0 0 0 0 0 0 0 Function Setting melody frequency lower 8bit MELFH register 7 6 5 4 3 2 1 0 bit Symbol MELON ML11 ML10 ML9 ML8 Read Write R W R W After reset 0 0 0 0 0 Function Control melody counter 0 Stop Clear 1 Start Setting melody frequency upper 4bit ALMINT regi...

Page 595: ...be set to 12 bit register MELFH MELFL Followings are setting example and calculation of melody output frequency Formula for calculating of melody waveform frequency fs 32 768 kHz Melody output waveform fMLD Hz 32768 2 N 4 Setting value for melody N 16384 fMLD 2 Note N 1 4095 001H FFFH 0 is not acceptable Example program In case of outputting A musical scale 440Hz LD MELALMC XXXXX1B Select melody w...

Page 596: ...waveform as output waveform from MLDALM Then 10 be set on MELALMC FC1 0 register and clear internal counter Finally alarm pattern has to be set on 8 bit register of ALM If it is inverted output data set ALMINV as invert Followings are example program setting value of alarm pattern and waveform of each setting value Setting value of alarm pattern Setting value for ALM register Alarm waveform 00H 0 ...

Page 597: ...1 AL3 pattern once 250 ms AL8 pattern Once Modulation frequency 4096 Hz AL1 pattern Continuous output 31 25 ms 1 秒 1 2 8 1 AL2 pattern 8 times 1 sec 62 5 ms 1 sec 1 2 1 AL4 pattern Twice 1 sec 62 5 ms 1 sec 1 2 1 3 AL5 pattern 3 times 1 sec 62 5 ms 1 AL6 pattern 1 times 62 5 ms 1 2 AL7 pattern Twice ...

Page 598: ...rrent is reduced by setting ADMOD1 DACON to 0 in the ADC has been stopped Figure 3 23 1 ADC Block Diagram AD Monitor function interrupt INTADM Complete interrupt AD INTADHP Normal AD Conversion complete interrupt INTAD Comparator VREFH VREFL Sample Hold ADMOD1 Scan repeat Busy End Start Internal data bus Channel selection control circuit A D Conversion Result Register ADREG0L 5L ADREG0H 5H D A Con...

Page 599: ...l 7 6 5 4 3 2 1 0 bit Symbol EOS BUSY I2AD ADS HTRGE TSEL1 TSEL0 Read Write R R R W After reset 0 0 0 0 0 0 0 Function Normal AD conversion end flag 0 During conversion sequence or before starting 1 Complete conversion sequence Normal AD conversion BUSY Flag 0 Stop conversion 1 During conversion AD conversion when IDLE2 mode 0 Stop 1 Operate Start Normal AD conversion 0 Don t Care 1 Start AD conve...

Page 600: ...xt SCAN start timing control for the channel scan repeat mode Channel Scan Repeat mode SCAN 1 REPEAT 1 0 No Wait 1 Start after read last of conversion result store Register Specify AD conversion interrupt for Channel Fixed Repeat Conversion mode Channel Fixed Repeat Conversion Mode SCAN 0 REPEAT 1 0 Generates interrupt every conversion 1 Generated interrupt every fourth conversion DAC VREF applica...

Page 601: ...0 High priority AD conversion at Hard ware trigger 0 Disable 1 Enable Select Hard ware trigger 00 INTTB10 interrupt 01 Reserved 10 ADTRG 11 I2S Sampling Counter Output AD Mode Control Register 3 High priority conversion control 7 6 5 4 3 2 1 0 bit Symbol HADCH2 HADCH1 HADCH0 Read Write R W R W R W After reset 0 0 0 0 0 Function Always write 0 High priority analog input channel select Always write ...

Page 602: ...lect analog channel for AD monitor function 1 000 AIN0 100 AN4 001 AIN1 101 AN5 010 AIN2 110 Reserved 011 AN3 111 Reserved Select analog channel for AD monitor function 0 000 AIN0 100 AN4 001 AIN1 101 AN5 010 AIN2 110 Reserved 011 AN3 111 Reserved Note1 When converting AD in hard ware trigger by setting HHTRGE and HTRGE to 1 set PGFC PG3F to 1 as ADTRG in case of external TRG before enabling it Wh...

Page 603: ... Overrun flag 0 No generate 1 Generate AD conversion result store flag 1 Stored AD Conversion Result Register 1 High 7 6 5 4 3 2 1 0 bit Symbol ADR19 ADR18 ADR17 ADR16 ADR15 ADR14 ADR13 ADR12 Read Write R After reset 0 0 0 0 0 0 0 0 Function Store Upper 8 bits of AN1 AD conversion result 9 8 7 6 5 4 3 2 1 0 Channel X conversion result 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Figure 3 23 6 AD Conversion Reg...

Page 604: ... Overrun flag 0 No generate 1 Generate AD conversion result store flag 1 Stored AD Conversion Result Register 3 High 7 6 5 4 3 2 1 0 bit Symbol ADR39 ADR38 ADR37 ADR36 ADR35 ADR34 ADR33 ADR32 Read Write R After reset 0 0 0 0 0 0 0 0 Function Store Upper 8 bits of AN3 AD conversion result 9 8 7 6 5 4 3 2 1 0 Channel X conversion result 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Figure 3 23 7 AD Conversion Reg...

Page 605: ... Overrun flag 0 No generate 1 Generate AD conversion result store flag 1 Stored AD Conversion Result Register 5 High 7 6 5 4 3 2 1 0 bit Symbol ADR59 ADR58 ADR57 ADR56 ADR55 ADR54 ADR53 ADR52 Read Write R After reset 0 0 0 0 0 0 0 0 Function Store Upper 8 bits of AN5 AD conversion result 9 8 7 6 5 4 3 2 1 0 Channel X conversion result 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Figure 3 23 8 AD Conversion Reg...

Page 606: ...te R After reset 0 0 0 0 0 0 0 0 Function Store Upper 8 bits of an AD conversion result 9 8 7 6 5 4 3 2 1 0 Channel X conversion result 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Figure 3 23 9 AD Conversion Registers ADREGSPL 12B0H ADREGSPH 12B1H ADREGxH ADREGxL Bits 5 2 are always read as 0 Bit 0 is the AD conversion result store flag ADRxRF When AD conversion result is stored the flag is set to 1 When Lowe...

Page 607: ...ion AD Conversion Result Compare Criterion Register 1 Low 7 6 5 4 3 2 1 0 bit Symbol ADR21 ADR20 Read Write R W After reset 0 0 Function Store Lower 2 bits of an AD conversion result compare criterion AD Conversion Result Compare Criterion Register 1 High 7 6 5 4 3 2 1 0 bit Symbol ADR29 ADR28 ADR27 ADR26 ADR25 ADR24 ADR23 ADR22 Read Write R W After reset 0 0 0 0 0 0 0 0 Function Store Upper 8 bit...

Page 608: ...e clock frequency selected in the above register To assure conversion accuracy however the conversion clock frequency must not exceed 12MHz MHz Note2 Don t change the clock frequency while AD conversion is in progress Figure 3 23 11 AD Conversion Registers fIO fSYS 2 ADCLK2 0 ADCLK AD conversion speed 100 fIO 4 10 0MHZ 12 μsec 40MHz 101 fIO 5 8MHZ 15 μsec 011 fIO 3 10 0MHZ 12 μsec 30MHz 100 fIO 4 ...

Page 609: ... 0 selects one of the six scan modes 2 High priority AD conversion Setting ADMOD3 HADCH2 0 selects one of the eight input pins AN0 AN5 On a Reset ADMOD1 SCAN is set to 0 and ADMOD1 ADCH2 0 is initialized to 000 Thus pin AN0 is selected as the fixed input channel Pins that are not used as analog input channels can be used as standard input port pins If a high priority AD conversion is triggered whi...

Page 610: ...version if a high priority AD conversion start ADMOD0 BUSY holds 1 When an AD conversion complete ADMOD0 EOS and ADMOD2 HEOS is set to 1 These flags are cleared to 0 by reading these flags only During a normal AD conversion writing a 1 to ADMOD0 ADS causes the ADC to abort any ongoing conversion immediately and restart During a normal AD conversion if normal AD conversion starting is enabled by ha...

Page 611: ...pleted the ADC sets the ADMOD0 EOS and generates the INTAD interrupt ADMOD0 EOS is cleared to 0 when it is read b Channel Scan Single Conversion mode This mode is selected by programming ADMOD0 REPET SCAN to 01 In this mode the ADC performs a single conversion on each of a selected group of channels When a single conversion sequence is completed ADMOD0 EOS is set to 1 and generates the INTAD inter...

Page 612: ...continuous conversion modes 3 and 4 clearing the ADMOD1 REPEAT stops the conversion sequence after the ongoing scan conversion process is completed Shift to a standby mode IDLE2 Mode with ADMOD0 I2AD 0 IDLE1 Mode or STOP Mode immediately stops operation of the AD converter even if AD conversion is still in progress Therefore ADC may consume current even if operation is stopped depending on stop co...

Page 613: ...fter a conversion 0 0 After every conversion After every conversion 0 Channel Fixed Repeat Conversion Mode After every four conversions After every four conversions 1 1 0 Channel Scan Single Conversion Mode After a scan conversion sequence After a scan conversion sequence 0 1 Channel Repeat Single Conversion Mode After each scan conversion sequence After each scan conversion sequence 1 1 Note EOS ...

Page 614: ...e AD monitor function is enabled This function generates an interrupt depending on condition of IRQEN1 0 when the finished AD conversion of the channel which specified with the ADMOD5 register if the value of the AD conversion result register pair is greater or less specified with CMP1C 0C than the value of the compare criterion register 0 1 ADCMxREGH L The ADC performs this comparison each times ...

Page 615: ...l Fixed Repeat Conversion mode conversion results are stored into the ADREG0H L to ADREG3H L sequentially In other modes the AD conversion result of channel AN0 AN1 AN2 AN3 AN4 and AN5 is stored in ADREG0H L ADREG1H L ADREG2H L ADREG3H L ADREG4H L and ADREG5H L respectively Table 3 23 1 shows the relationships between the analog input channels and the AD conversion result registers ...

Page 616: ...AN3 ADREG3H L AN4 ADREG4H L AN5 ADREG5H L ADREG0H L ADREG3H L ADREG1H L ADREG2H L Note For detect a overrun error thoroughly read the AD conversion result register high at first and read the AD conversion result register low at second If OVRn 0 and ADRnRF 1 a correct conversion result was obtained 3 23 2 9 Data Polling When the results of AD conversion are processed by means of data polling withou...

Page 617: ...On ADMOD3 0 0 1 0 0 0 0 0 Set pin AN2 to be the analog input channel ADMOD2 0 0 0 0 1 0 0 0 Start a high priority AD conversion by software Interrupt routine processing example WA ADREGSP Read value of ADREGSPL and ADREGSPH into 16 bits general purpose register WA WA 6 Shift contents read into WA six times to right and zero fill upper bits 2A00H WA Write contents of WA to memory address 2A00H 4 Co...

Page 618: ...on Connecting the watchdog timer output to the reset pin internally forces a reset The level of external RESET pin is not changed 3 24 1 Configuration Figure 3 24 1 is a block diagram of the watchdog timer WDT Figure 3 24 1 Block Diagram of Watchdog Timer Note It needs to care designing the total machine set because Watchdog timer can t operate completely by external noise WDMOD WDTE RESET pin Sel...

Page 619: ...ring bus release when BUSAK goes low When the device is in IDLE2 mode the operation of WDT depends on the WDMOD I2WDT setting Ensure that WDMOD I2WDT is set before the device enters IDLE2 mode The watchdog timer consists of a 22 stage binary counter which uses the clock fIO as the input clock The binary counter can output 215 fIO 217 fIO 219 fIO and 221 fIO Selecting one of the outputs using WDMOD...

Page 620: ... state merely by setting WDTE to 1 3 Watchdog timer out reset connection RESCR This register is used to connect the output of the watchdog timer with the RESET terminal internally Since WDMOD RESCR is initialized to 0 at reset a reset by the watchdog timer will not be performed 2 Watchdog timer control registers WDCR This register is used to disable and clear the binary counter for the watchdog ti...

Page 621: ...on Watchdog timer detection time 00 2 15 fIO Approximately 819 2 μs at fIO 40 MHz 01 2 17 fIO Approximately 3 276 ms at fIO 40 MHz 10 2 19 fIO Approximately 13 107 ms at fIO 40 MHz 11 2 21 fIO Approximately 52 428 ms at fIO 40 MHz Watchdog timer enable disable control 0 Disabled 1 Enabled Figure 3 24 4 Watchdog Timer Mode Register 7 6 5 4 3 2 1 0 Bit symbol WDCR 1301H Read Write W After reset Func...

Page 622: ...at are supplied in Power Cut Mode are the power supply rail for external pins DVCC 3A DVCC 3B the power supply rail for ADC AVCC and the power supply rail for RTC and backup RAM DVCC 1B DVCC1A and DVCC1C power supply rails are isolated internally with their signals cut off so that no flow through current will be generated in the LSI when the power is turned off DVCC 3A DVCC 3B This 3V rail supplie...

Page 623: ...more about 92us internal reset signal will be released We recommend to confirm actual performance on final set because the time to be stable all voltage level and power supply circuit are difference characteristics every final set The following operations are affected by the setting of the PCM_ON bit PCM_ON 1 PCM_ON 0 External interrupt input No interrupt HOT_RESET signal assert Interrupt Operatio...

Page 624: ...rom the Power Cut Mode should be set as input pins with interrupt enabled About trigger of interruption only rising edges are effective among selectable interruption pins When INT4 is used as TSI the de bounce circuit should be disabled Then set the warm up time for waking up from Power Cut Mode in PMCCTL WUTM1 0 Write the wake up program at addresses from 46000H to 49FFFH in the internal RAM Shou...

Page 625: ... only bit 7 of PMCCTL register All initialize setting including WDT setting must be written in fixed RAM area 46000H 49FFFH 3 Control of low frequency clock XT Power Management Circuit operates by low frequency clock Low frequency clock XT must be enable condition 2 Operation Sequence 1 Execution area of program must shift to internal RAM area Before shifting Power Cut Mode it must stop all the so...

Page 626: ...nal boot ROM regardless of the external AM pin state All external ports retain the state before entering the Power Cut Mode except for the PnDR setting which is released upon release of HOT_RESET Output pin Hi Z state 1 or 0 output Input pin input gate OFF Input pin input gate ON The internal boot ROM first checks the PMCCTL PCM_ON bit in the PMC If this bit is set to 1 execution jumps to address ...

Page 627: ...lock time minimum around 31μS 4 The wake up triggers during waking up are ignored 5 After Warm up count and spend 1 clock time around 31μS release the DRV setting of every ports After that spends 2 clock time around 62μS release internal RESET Hot_Reset CPU state transition PMCCTL PCM_ON PWE pin INTRTC INT0 7 INTKEY Internal HOT_RESET Port state XT2 1 A maximum of 3 clocks 92 μs are needed for ent...

Page 628: ...cuitry excluding the CPU part of internal RAM AD converter and RTC to reduce leak current In the Power Cut Mode power is supplied to only the I O including the AD pins TSI circuit 16 Kbytes of internal RAM low frequency oscillation circuit RTC and PMC Main Power RTC LOW_OSC RAM16kB PMC TMP92CZ26A XT1 XT2 I O CPU Other Logic High_OSC Regulator 1 5V DVCC 1A DVCC 1C AVCC AVSS DVSS 1C DVSS COM DVCC 1B...

Page 629: ... may temporarily become unstable in this case Therefore if there is any possibility that this would affect external devices connected with the TMP92CZ26A external power supplies should be turned on or off while internal power supplies are stable as shown in the diagram above Note2 In the power ON sequence 3V rails must not be turned on before 1 5V rails In the power OFF sequence 3V rails must not ...

Page 630: ...Disable AD converter ld lcdctl0 00h Disable DMA operation ld pmfc 80h Set PM7 port to PWE function ld p9fc 40h ld inte34 50h Set INT4 and set level ld tsicr1 00h Disable de bounce circuit ld pllcr0 00h Change CPU clock from PLL to fOSCH ld pllcr1 00h Stop the PLL circuit ld pmcctl 00h Set Warm up time di ld pmcctl 80h Enable PCM_ON 1 Shift to Power Cut Mode After Wake up org 046000h ld pmcctl 00h ...

Page 631: ...k fSYS 3 26 1 1 Control Register The control register is used to control the operation of the MAC MAC Control Register 7 6 5 4 3 2 1 0 bit Symbol MOVF MOPST MSTTG2 MSTTG1 MSTTG0 MSGMD MOPMD1 MOPMD0 Read Write R W W R W R W R W After reset 0 0 0 0 0 0 0 0 Function Overflow flag 0 No overflow 1 Overflow occurred Calculation soft start 0 Don t care 1 Start calculation Calculation start trigger 000 Wr...

Page 632: ...isters are cleared to 0 Note 2 Read modify write instructions can be used on all the registers Note 3 All the registers can be accessed in long word word or byte units Note 4 When MACCR MSTTG2 0 is set to 0 001 010 or 011 and the registers are written in word or byte units the 7 0 bits of each register must be written last Note 5 The MACORL register is fixed one system clock fSYS after calculation...

Page 633: ...f the MACOR register Then the result is stored back in the MACOR register b 64 32 32 mode In this mode the contents of the MACMA register and the MACMB register are multiplied and the result is subtracted from the contents of the MACOR register Then the result is stored back in the MACOR register c 32 32 64 mode In this mode the contents of the MACMA register and the MACMB register are multiplied ...

Page 634: ... s complement data Even in unsigned mode it is possible to set signed two s complement data in the MACOR register to perform additions and subtractions in signed mode 2 Calculation start trigger As a trigger to start calculation writing to the MACMA MACMB or MACOR register or soft start MACCR MOPST 1 can be selected in MACCR MSTTG2 0 3 Overflow flag When an overflow occurs in the calculation resul...

Page 635: ...DE 22222222 ld MACORL xhl Write 33333333 to MACORL ld MACORH xde Clear MACORH ld MACMA xix Write 11111111 to MACMA ld MACMB xiy Write 22222222 to MACMB set 5 MACCR ld xhl MACORL Read lower result 0x41FDB975 bit 7 MACCR Check over flow error jp nz ERROR Go to error routine if there is over flow error ld xde MACORH Read upper result 0x02468ACF 3 Unsigned multiply accumulate operation two multiply ac...

Page 636: ...e TMP92CZ26A and an emulator in debug mode place the DSU connector on the target board as near less than 5cm to the TMP92CZ26A as possible It is desirable that all the signals are same length Recommend connector SAMTEC FTSH 110 01 DV EJ 2 How to enter debug mode Debug mode can be entered by setting the DBGE pin to Low To return to normal mode from debug mode be sure to set the DBGE pin to High and...

Page 637: ...roller must not be used to reset the controller and microcontroller Instead reset should be performed from the controller For details please refer to the instruction manual of the emulation pod to be used If reset from the microcontroller by the RESET pin may clash the register information and internal RAM data in the CPU including not only programs but also breakpoint and trace information ...

Page 638: ...pin data Output latch is reset to 0 Port Z Control Register 7 6 5 4 3 2 1 0 bit Symbol PZ7C PZ6C PZ5C PZ4C PZ3C PZ2C PZ1C PZ0C Read Write W After reset 0 0 0 0 0 0 0 0 Function 0 Input 1 Output Port Z Function Register 7 6 5 4 3 2 1 0 bit Symbol PZ7F PZ6F PZ5F PZ4F PZ3F PZ2F PZ1F PZ0F Read Write W After reset 0 0 0 0 0 0 0 0 Function 0 Port Port Z Drive Register 7 6 5 4 3 2 1 0 bit Symbol PZ7D PZ6...

Page 639: ... Bit Symbol PU7F PU6F PU5F PU4F PU3F PU2F PU1F PU0F Read Write W After reset 0 0 0 0 0 0 0 0 Function 0 Port 1 Data bus for LCDC LD23 to LD16 Note When LD23 to LD16 are used set PUnC to 1 Port U Drive Register 7 6 5 4 3 2 1 0 Bit Symbol PU7D PU6D PU5D PU4D PU3D PU2D PU1D PU0D Read Write R W After reset 1 1 1 1 1 1 1 1 Function Input output buffer drive register for standby mode Note Although it is...

Page 640: ...it symbol CSDIS ROMLESS VACE BROMCR 016CH Read Write R W After reset 1 1 1 0 Function NAND Flash area CS output 0 Enable 1 Disable Boot ROM 0 Used 1 Not used Vector address conversion 0 Disable 1 Enable 7 6 5 4 3 2 1 0 bit symbol PCM_ON WUTM1 WUTM0 Read Write R W W R W R W After system reset 0 0 0 0 After hot reset Data retained Function Power Cut Mode 0 Disable 1 Enable Always write 0 Always read...

Page 641: ...ns the bus it occupies the bus for 80 times of debug transmission clock LH_SYNCLK maximum Therefore in some cases other DMA operations LCD display DMAC data transfer SDRAM refresh may not be performed at desired timing Figure 3 27 1 Example of Data Bus Occupancy Timing in Non Debug Mode Figure 3 27 1 shows an example of data bus occupancy timing in non debug mode depicting the LHSYNC signal LCP0 s...

Page 642: ...r of LCD and HDMA LCD DMA operation 2 HDMA operation 2 regardless of the order in which they are issued Taking the above into account it is necessary to ensure that each LCD DMA or HDMA operation is finished before the next LCD driver output is started In other words to avoid abnormal operation in debug mode the maximum duration of HDMA operation time must be set so that it does not interfere with...

Page 643: ...3B Note2 In PG0 to PG5 P96 P97 VREFH VREFL maximum ratings for AVCC is applied Note3 The maximum ratings are rated values that must not be exceeded during operation even for an instant Any one of the ratings must not be exceeded If any maximum rating is exceeded a device may break down or its performance may be degraded causing it to catch fire or explode resulting in injury to the user Thus when ...

Page 644: ... PF5 PG0 to PG5 PJ5 to PJ6 PN0 to PN7 PP1 to PP2 PR0 to PR3 PT0 to PT7 PU0 to PU7 PX5 PX7 0 3 DVCC3A 3 0 DVCC3A 3 6 VIL1 Input Low Voltage for PV0 to PV2 PV6 to PV7 PW0 to PW7 0 3 DVCC3B 3 0 DVCC3B 3 6 VIL2 Input Low Voltage for P91 to P92 P96 to P97 PA0 to PA7 PC0 to PC3 PP3 to PP5 PZ0 to PZ7 RESET 0 25 DVCC3A 3 0 DVCC3A 3 6 VIL3 Input Low Voltage for AM0 to AM1 DBGE 0 1 DVCC3A 3 0 DVCC3A 3 6 VIL...

Page 645: ... 0 3 3 0 DVCC3A 3 6 VIH1 Input High Voltage for PV0 to PV2 PV6 to PV7 PW0 to PW7 0 7 DVCC3B DVCC3B 0 3 3 0 DVCC3B 3 6 VIH2 Input High Voltage for P91 to P92 P96 to P97 PA0 to PA7 PC0 to PC3 PP3 to PP5 PZ0 to PZ7 RESET 0 75 DVCC3A DVCC3A 0 3 3 0 DVCC3A 3 6 VIH3 Input High Voltage for AM0 to AM1 DBGE 0 9 DVCC3A DVCC3A 0 3 3 0 DVCC3A 3 6 VIH4 Input High Voltage for X1 0 9 DVCC1C DVCC1C 0 3 1 4 DVCC1C...

Page 646: ...tput High Voltage2 Except VOL1 output pin 2 4 IOH 2mA 3 0 DVCC3A VOL T Output Low Voltage for P96 PX P97 PY pins 0 2 IOL T 6 6mA VOH T Output High Voltage for P96 PX P97 PY pins VCC 0 2 V IOH T 6 6mA 3 0 DVCC3A 3 6 ILI Input Leakage Current 0 02 5 μA 0 0 Vin DVCC3A ILO Output Leakage Current 0 05 10 μA 0 2 Vin DVCC3A 0 2V RRST Pull Up Down Resistor for RESET PA0 to PA7 P96 30 50 70 KΩ CIO Pin Capa...

Page 647: ...Ta 70 6 30 Ta 50 DVCC3A 3 6V DVCC3B 3 6V AVCC 3 6V 50 Ta 70 Power Cut Mode WITH PMC function 2 35 Ta 50 DVCC1A 0V DVCC1B 1 6V DVCC1C 0V XT 32KHz X OFF 35 Ta 70 6 30 Ta 50 DVCC3A 3 6V DVCC3B 3 6V AVCC3 6V 800 Ta 70 ICC STOP 200 600 μA Ta 50 DVCC1A 1 6V DVCC1B 1 6V DVCC1C 1 6V XT OFF X OFF Note1 Typical values are value that when Ta 25 C and Vcc 3 3 V unless otherwise noted Note2 ICC measurement con...

Page 648: ... 1 A0 A23 valid D0 D15 input at 0 waits tAD 2 0T 18 0 7 15 3 tAD6 6 0T 18 0 82 5 2 A0 A23 valid D0 D15 input at 4 waits 6 waits tAD7 8 0T 18 0 82 tRD 1 5T 18 0 7 6 1 RD falling D0 D15 input at 0 waits tRD 1 5T 18 0 0 75 tRD6 5 5T 18 0 73 6 6 2 RD falling D0 D15 input at 4 waits 6waits tRD7 5 5T 18 0 50 75 7 1 RD low width at 0 waits tRR 1 5T 10 8 75 14 9 7 2 RD low width at 4 waits tRR6 5 5T 10 58...

Page 649: ... WR xx rising A0 A23 hold tWA 0 5T 5 0 1 25 3 3 21 WR xx rising D0 D15 hold tWD 0 5T 5 0 1 25 3 3 tRDO 0 5T 2 0 6 3 22 1 RD rising D0 D15 output tRDO 0 5T 1 0 5 25 tRDO 1 5T 2 0 22 9 22 2 RD rising D0 D15 output tRDO 2 5T 1 0 30 25 tSWP 1 0T 7 0 9 6 23 Write width for SRAM tSWP 1 0T 4 0 8 5 tSBW 1 0T 7 0 9 6 24 Data byte control end of write for SRAM tSBW 1 0T 4 0 8 5 25 Address setup time for SRA...

Page 650: ...gnals is undefined Note2 The above timing chart show an example of basic bus timing The CSn R W RD WRxx SRxxB SRWR pins timing can be adjusted by memory controller timing adjust function tOSC SDCLK WAIT A0 A23 D0 D15 SRxxB X1 CSn RD SRWR tCL tCYC tCH tTK tKT tAD tRR tRD tRRH tAR tRK tSBA Data input tHA tHR R W ...

Page 651: ...fined Note2 The above timing chart show an example of basic bus timing The CSn R W RD WRxx SRxxB SRWR pins timing can be adjusted by memory controller timing adjust function tOSC SDCLK WAIT A0 A23 D0 D15 SRxxB X1 CSn WRxx SRWR tCL tCYC tCH tTK tKT tWW tDW tAW tWK tSBW Data output tWA tSWR tWD RD tRDO tSDH tSAS tSWP tSDS R W ...

Page 652: ...TMP92CZ26A 92CZ26A 649 3 Read cycle 1 wait 4 Write cycle 1 wait SDCLK Data input tRR3 tAD3 tRD3 WAIT A0 A23 CSn RD D0 D15 R W SDCLK Data output tWW3 tDW3 WAIT A0 A23 CSn WRxx D0 D15 RD R W tRDO ...

Page 653: ...18 13 24 5 A0 A23 Invalid D0 D15 hold tHA 0 0 0 6 RD rising D0 D15 hold tHR 0 0 0 ns AC measuring condition Note The a b and c of Symbol in above table depend on the falling timing of RD pin The falling timing of RD pin is set by MEMCR0 RDTMG1 0 in memory controller If MEMCR0 RDTMG1 0 is set to 00 it correspond with a in above table and 01 is b 10 is c SDCLK A2 A23 A0 A1 2 CS RD D0 D15 0 1 2 3 Dat...

Page 654: ...tCK T 12 5 16 6 0 5T 5 3 3 8 CLK high level width tCH 0 5T 3 3 25 0 5T 5 3 3 9 CLK low level width tCL 0 5T 3 3 25 10 1a T 16 0 6 10 1b Access time from CLK CL 2 SRDS 0 Read data shift OFF tAC T 16 3 5 10 2a T 6 5 10 1 10 2b Access time from CLK CL 2 SRDS 1 Read data shift ON tAC T 6 5 6 11 Output data hold time tOH 0 0 0 1Word Single tDS 0 5T 4 2 25 3 3 12 Data in set up time Burst tDS 0 5T 4 2 2...

Page 655: ... 652 1 SDRAM read timing 1Word length read mode SPRE 1 Column Row SDCLK SDxxDQM SDCS SDRAS SDCAS A0 A9 D0 D15 SDWE A10 A11 A15 tCH tCL tCK tRCD tRAS tRP tCMS tCMH tCMS tCMH tRRD tAH tAS tAS tAH Row Row Data input tAC tOH ...

Page 656: ...653 2 SDRAM write timing Single write mode SPRE 1 SDCLK SDxxDQM SDCS SDRAS SDCAS D0 D15 SDWE tCH tCL tCK tWR tRCD tRP tCMS tRRD tCMS tCMH tRAS Data output tDS tDH tCMH Column Row A0 A9 A10 A11 A15 tAH tAS tAS tAH Row Row ...

Page 657: ...st read timing Start burst cycle Column Row SDCLK SDxxDQM SDCS SDRAS SDCAS A0 A9 D0 D15 SDWE A10 A11 A15 tCK tRCD tCMS tCMH tCMH tAH tAS Row Row Data input tAC tCMH tCMS tCMS 027 tAH tAS tAS 0 tAC tAC Data input Data input tOH tOH tMRD ...

Page 658: ...Z26A 92CZ26A 655 4 SDRAM burst read timing End burst timing SDCLK SDxxDQM SDCS SDRAS SDCAS D0 D15 SDWE tCK tRP tCMS tCMH Data input tCMH tCMS tCMS Column tAC Data input tOH tOH tCMH Row A0 A9 A10 A11 A15 tAS ...

Page 659: ...TMP92CZ26A 92CZ26A 656 5 SDRAM initializes timing 220 SDCLK SDxxDQM SDCS SDRAS SDCAS A0 A9 SDWE tCK tRC tCMS tCMH tCMS tCMH tCMH tCMS A10 A11 A15 tAS tAH tCMH tCMS 0 ...

Page 660: ...TMP92CZ26A 92CZ26A 657 6 SDRAM refreshes timing 7 SDRAM self refresh timing SDCLK SDxxDQM SDCS SDRAS SDCAS SDWE tCK tRC tCMH tCMS SDCLK SDCKE SDCS SDRAS SDCAS SDWE tCK tRC tCMH tCMS tCKS tCKS SDxxDQM ...

Page 661: ... 30 47 6 tDS Write data setup time 1 0 n T 20 30 47 7 tDH Write data hold time 0 5 m T 2 42 56 ns AC measuring condition Note1 The n in Variable means wait number which is set to NDFMCR0 SPLW1 0 and m means number which is set to NDFMCR0 SPHW1 0 Example If NDFMCR0 SPLW1 0 is set to 01 n 1 tRP 1 5 n T 12 2 5T 12 Note2 In above variable the setting that result is minus can not use Data input SDCLK A...

Page 662: ...ata valid SCLK rising falling tRDS 20 20 20 ns 2 SCLK output mode I O interface mode Variable Parameter Symbol Min Max 80 MHz 60 MHz Unit SCLK cycle Programmable tSCY 16T 8192T 200 266 Output data SCLK rising falling tOSS tSCY 2 40 60 93 SCLK rising falling Output data hold tOHS tSCY 2 40 60 93 SCLK rising falling Input data hold tHSR 0 0 0 SCLK rising falling Input data valid tSRD tSCY 1T 50 137 ...

Page 663: ...ation Variable Parameter Symbol Min Max 80 MHz 60 MHz Unit INT0 INT7 low width tINTAL 2T 40 65 74 INT0 INT7 high width tINTAH 2T 40 65 74 ns 4 3 8 USB Timing Full speed VCC 3 3 0 3 V fUSB 48 MHz Ta 0 70 C Parameter Symbol Min Max Unit D D rising time tR 4 20 D D falling time tF 4 20 ns Output signal crossover voltage VCRS 1 3 2 0 V AC measuring condition D D TMP92CZ26A R1 27 Ω R1 27 Ω R2 15 kΩ CL ...

Page 664: ...alling Include phase inversion tDSU T n 1 7 5 5 9 1 LCP0 falling Data hold Include phase inversion tDHD T n 1 7 5 5 9 1 Signal delay from LCP0 basic changing point Include phase inversion tGDL 20 20 20 20 ns AC measuring condition CL 50 pF LCP0 only CL 30 pF Note The n in Variable show value that is set to LCDMODE0 SCPW1 0 Example If LCDMODE0 SCPW1 0 01 n 1 tRWP 2T n 1 2T LCP0 tCWH tCWL tCW LD0 LD...

Page 665: ...5 tCR 15 35 35 I2SCKO low width tLB 0 5 tCR 15 35 35 I2SDO I2SWS setup time tSD 0 5 tCR 15 35 35 I2SDO I2SWS hold time tHD 0 5 tCR 8 42 42 ns Note The Maximum operation frequency of I2SCKO in I2S circuit is 10MHz Don t set I2SCKO to value more than 10MHz AC measuring condition I2SCKO I2SDO and I2SWS pins CL 30 pF I2SCKO tCR tLB tHB I2SDO tHD tHD tSD I2SWS ...

Page 666: ...CLK rising tODS 0 5S 18 7 15 SPCLK rising falling Output data hold tODH 0 5S 10 15 23 4 Input data valid SPCLK rising falling tIDS 5 5 5 SPCLK rising falling Input data valid tIDH 5 5 5 ns AC measuring condition Clock of top column in above table shows system clock frequency and S in Variable show SPCLK clock cycle ns CL 25 pF SPCLK Output at SPIMD TCPOL RCPOL 11 SPDO Output fPP tr tf 0 2VCC 0 7 V...

Page 667: ...S DVSS Analog input voltage AVIN VREFL VREFH V IREFON VREFON 1 0 38 0 45 mA Analog current for analog reference voltage IREFOFF VREFON 0 1 5 μA Total error Quantize error of 0 5 LSB is included ET Conversion speed at 12uS 2 0 4 0 LSB Note1 1 LSB VREFH VREFL 1024 V Note2 Minimum frequency for operation Minimum clock for AD converter operate is 3MHz Clock frequency that is seleted by Clock gear fSYS...

Page 668: ...bol Name Address 7 6 1 0 Bit Symbol Read Write Initial value after reset Remarks Note Prohibit RMW in the table means that you cannot use RMW instructions on these register Example When setting bit0 only of the register PxCR the instruction SET 0 PxCR cannot be used The LD transfer instruction must be used to write all eight bits Read Write R W Both read and write are possible R Only read is possi...

Page 669: ...C BH CH CH P7 CH CH PF DH DH DH DH EH EH P7CR EH EH PFCR FH FH P7FC FH FH PFFC Address Name Address Name Address Name Address Name 0040H PG 0050H PK 0060H PP 0070H Reserved 1H 1H 1H 1H Reserved 2H 2H 2H PPCR 2H Reserved 3H PGFC 3H PKFC 3H PPFC 3H Reserved 4H 4H PL 4H PR 4H Reserved 5H 5H 5H 5H Reserved 6H 6H 6H PRCR 6H Reserved 7H 7H PLFC 7H PRFC 7H Reserved 8H 8H PM 8H PZ 8H Reserved 9H 9H 9H 9H ...

Page 670: ... 3H PJDR 3H PTFC 3H PXFC 4H P4DR 4H PKDR 4H PU 4H 5H P5DR 5H PLDR 5H 5H 6H P6DR 6H PMDR 6H PUCR 6H 7H P7DR 7H PNDR 7H PUFC 7H 8H P8DR 8H PPDR 8H PV 8H 9H P9DR 9H PRDR 9H PVFC2 9H AH PADR AH PZDR AH PVCR AH BH BH PTDR BH PVFC BH CH PCDR CH PUDR CH PW CH DH DH PVDR DH DH EH EH PWDR EH PWCR EH FH PFDR FH PXDR FH PWFC FH Note Do not access no allocated name address ...

Page 671: ...DMAB 9H INTETB1 9H INTEKEY 9H 9H DMAR AH AH INTELCD AH IIMC1 AH DMASEL BH INTES0 BH INTEI2S01 BH BH CH CH INTENDFC CH CH DH DH Reserved DH DH EH EH INTEP0 EH EH FH FH INTEAD FH Reserved FH 3 MEMC 4 TSI Address Name Address Name Address Name Address Name 0140H B0CSL 0150H 0160H 01F0H TSICR0 1H B0CSH 1H 1H 1H TSICR1 2H MAMR0 2H 2H 2H Reserved 3H MSAR0 3H 3H 3H 4H B1CSL 4H 4H 4H 5H B1CSH 5H 5H 5H 6H ...

Page 672: ...LCDO0DLY 1H LSAMM 1H 2H 2H LCDO1DLY 2H LSAMH 2H 3H LCDDVM0 3H LCDO2DLY 3H 3H 4H LCDSIZE 4H LCDHSW 4H LSASL 4H 5H LCDCTL0 5H LCDLDW 5H LSASM 5H 6H LCDCTL1 6H LCDHO0W 6H LSASH 6H 7H LCDCTL2 7H LCDHO1W 7H 7H 8H LCDDVM1 8H LCDHO2SW 8H LSAHX 8H 9H 9H LCDHWB8 9H LSAHX 9H AH LCDHSP AH AH LSAHY AH BH LCDHSP BH BH LSAHY BH CH LCDVSP CH CH LSASS CH DH LCDVSP DH DH LSASS DH EH LCDPRVSP EH EH LSACS EH FH LCDH...

Page 673: ..._A BH EP3_MODE BH EP3_SIZE_L_A BH EP3_SIZE_H_A CH CH CH DH DH DH EH EH EH FH FH FH Address Name Address Name Address Name 07B0H 07C0H bmRequestType 07D0H COMMAND 1H EP1_SIZE_H_B 1H bRequest 1H EPx_SINGLE1 2H EP2_SIZE_H_B 2H wValue_L 2H Reserved 3H EP3_SIZE_H_B 3H wValue_H 3H EPx_BCS1 4H 4H wIndex_L 4H Reserved 5H 5H wIndex_H 5H 6H 6H wLength_L 6H INT_Control 7H 7H wLength_H 7H 8H 8H SetupReceived ...

Page 674: ...7F0H USBINTFR1 1H FRAME_L 1H USBINTFR2 2H FRAME_H 2H USBINTFR3 3H ADDRESS 3H USBINTFR4 4H 4H USBINTMR1 5H 5H USBINTMR2 6H USBREADY 6H USBINTMR3 7H 7H USBINTMR4 8H Set Descriptor STALL 8H USBCR1 9H 9H AH AH BH BH CH CH DH DH EH EH FH FH Note Do not access no allocated name address ...

Page 675: ...LOCALPX 1H LOCALRX 1H LOCALESX 1H LOCALOSX 2H LOCALPY 2H LOCALRY 2H LOCALESY 2H LOCALOSY 3H LOCALPY 3H LOCALRY 3H LOCALESY 3H LOCALOSY 4H LOCALPZ 4H LOCALRZ 4H LOCALESZ 4H LOCALOSZ 5H LOCALPZ 5H LOCALRZ 5H LOCALESZ 5H LOCALOSZ 6H 6H 6H 6H 7H 7H 7H 7H 8H LOCALLX 8H LOCALWX 8H LOCALEDX 8H LOCALODX 9H LOCALLX 9H LOCALWX 9H LOCALEDX 9H LOCALODX AH LOCALLY AH LOCALWY AH LOCALEDY AH LOCALODY BH LOCALLY ...

Page 676: ...DRSCA0 1H NDFDTR0 2H NDFMCR1 2H NDRSCD0 2H NDFDTR1 3H NDFMCR1 3H 3H NDFDTR1 4H NDECCRD0 4H NDRSCA1 4H 5H NDECCRD0 5H NDRSCA1 5H 6H NDECCRD1 6H NDRSCD1 6H 7H NDECCRD1 7H 7H 8H NDECCRD2 8H NDRSCA2 8H 9H NDECCRD2 9H NDRSCA2 9H AH NDECCRD3 AH NDRSCD2 AH BH NDECCRD3 BH BH CH NDECCRD4 CH NDRSCA3 CH DH NDECCRD4 DH NDRSCA3 DH EH EH NDRSCD3 EH FH FH FH ...

Page 677: ...MACA3 9H HDMACA0 9H HDMACA1 9H HDMACA2 9H HDMACA3 AH HDMACB0 AH HDMACB1 AH HDMACB2 AH HDMACB3 BH HDMACB0 BH HDMACB1 BH HDMACB2 BH HDMACB3 CH HDMAM0 CH HDMAM1 CH HDMAM2 CH HDMAM3 DH DH DH DH EH EH EH EH FH FH FH FH Address Name Address Name Address Name 0940H HDMAS4 0950H HDMAS5 0970H 1H HDMAS4 1H HDMAS5 1H 2H HDMAS4 2H HDMAS5 2H 3H 3H 3H 4H HDMAD4 4H HDMAD5 4H 5H HDMAD4 5H HDMAD5 5H 6H HDMAD4 6H H...

Page 678: ...DH TA7FFCR EH EH EH FH FH FH 15 16 bit timer 16 SIO 17 SBI Address Name Address Name Address Name Address Name 1180H TB0RUN 1190H TB1RUN 1200H SC0BUF 1240H SBI0CR1 1H 1H 1H SC0CR 1H SBI0DBR 2H TB0MOD 2H TB1MOD 2H SC0MOD0 2H I2C0AR 3H TB0FFCR 3H TB1FFCR 3H BR0CR 3H SBI0CR2 SBI0SR 4H 4H 4H BR0ADD 4H SBI0BR0 5H 5H 5H SC0MOD1 5H 6H 6H 6H 6H 7H 7H 7H SIRCR 7H SBI0CR0 8H TB0RG0L 8H TB1RG0L 8H 8H 9H TB0R...

Page 679: ...H 7H ADREG3H 7H ADCM1REGH 7H 8H ADREG4L 8H ADMOD0 8H 9H ADREG4H 9H ADMOD1 9H AH ADREG5L AH ADMOD2 AH BH ADREG5H BH ADMOD3 BH CH Reserved CH ADMOD4 CH DH Reserved DH ADMOD5 DH EH Reserved EH EH FH Reserved FH ADCCLK FH 20 RTC 21 MLD Address Name Address Name 1320H SECR 1330H ALM 1H MINR 1H MELALMC 2H HOURR 2H MELFL 3H DAYR 3H MELFH 4H DATER 4H ALMINT 5H MONTHR 5H 6H YEARR 6H 7H PAGER 7H 8H RESTR 8H...

Page 680: ...2H MACMA 2H 3H 3H 3H MACMA 3H 4H 4H 4H MACMB 4H 5H 5H 5H MACMB 5H 6H 6H 6H MACMB 6H 7H 7H 7H MACMB 7H 8H I2S0CTL 8H I2S1CTL 8H MACORL 8H 9H I2S0CTL 9H I2S1CTL 9H MACORL 9H AH I2S0C AH I2S1C AH MACORL AH BH I2S0C BH I2S1C BH MACORL BH CH CH CH MACORH CH MACCR DH DH DH MACORH DH EH EH EH MACORH EH FH FH FH MACORH FH Note Do not access no allocated name address ...

Page 681: ...0024H Data from external port Data from external port Output latch register is set to 1 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 R PA PORTA 0028H Data from external port PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 R W PC PORTC 0030H Data from external port Output latch register is set to 1 PF7 PF5 PF4 PF3 PF2 PF1 PF0 R W R W PF PORTF 003CH 1 Data from external port Output latch register is set to 1 PG5 PG4 PG3 PG2 PG1...

Page 682: ...external port Output latch register is cleared to 0 PV7 PV6 PV4 PV3 PV2 PV1 PV0 R W R W PV PORTV 00A8H Data from external port Output latch register is cleared to 0 Data from external port Output latch register is cleared to 0 PW7 PW6 PW5 PW4 PW3 PW2 PW1 PW0 R W PW PORTW 00ACH Data from external port Output latch register is cleared to 0 PX7 PX5 PX4 R W R W PX PORTX 00B0H Data from external port O...

Page 683: ...C P61C P60C W 0 0 0 0 0 0 0 0 P6CR PORT6 control register 001AH Prohibit RMW 0 Input 1 Output P67F P66F P65F P64F P63F P62F P61F P60F W 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 P6FC PORT6 function register 001BH Prohibit RMW 0 Port 1 Address bus A16 A23 P76C P75C P74C P73C P72C P71C W W W W W W 0 0 0 0 0 0 P7CR PORT7 control register 001EH Prohibit RMW 0 Input port WAIT 1 Output port 0 Input port NDR B 1 O...

Page 684: ...2 PORT8 function fegister2 0021H Prohibit RMW 0 CSXB 1 ND1CE 0 CSZD 1 ND0CE 0 Port 3 CS 1 CSXA 0 Output port 2 CS 1 CSZA SDCS 0 P81F 1 SDCS P92C P91C P90C W 0 0 0 P9CR PORT9 control register 0026H Prohibit RMW 0 Input port 0 CTS 1 Output port SCLK0 0 Input port RXD0 1 Output port 0 Input port 1 Output port TXD0 P96F P92F P90F W W W 0 0 0 P9FC PORT9 function register 0027H Prohibit RMW 0 Input port...

Page 685: ...ut port TA2IN 0 Input port INT2 1 Output port 0 Input port INT1 1 Output port TA0IN 0 Input port INT0 1 Output port PC7F PC6F PC5F PC4F PC3F PC2F PC1F PC0F W 0 0 0 0 0 0 0 0 PCFC PORTC function register 0033H Prohibit RMW 0 Port 1 KO output Open Drain 0 Port 1 EA28 0 Port 1 EA27 0 Port 1 EA26 0 Port 1 INT3 TA2IN 0 Port 1 INT2 0 Port 1 INT1 TA0IN 0 Port 1 INT0 PF5C PF4C PF3C PF2C PF1C PF0C W 0 0 0 ...

Page 686: ... Port 1 SDLUDQM 0 Port 1 SDLLDQM 0 Port 1 SDWE SRWR 0 Port 1 SDCAS SRLUB 0 Port 1 SDRAS SRLLB PK7F PK6F PK5F PK4F PK3F PK2F PK1F PK0F W 0 0 0 0 0 0 0 0 PKFC PORTK function register 0053H Prohibit RMW 0 Port 1 LGOE2 0 Port 1 LGOE1 0 Port 1 LGOE0 0 Port 1 LHSYNC 0 Port 1 LVSYNC 0 Port 1 LFR 0 Port 1 LLOAD 0 Port 1 LCP0 PL7F PL6F PL5F PL4F PL3F PL2F PL1F PL0F W 0 0 0 0 0 0 0 0 PLFC PORTL function reg...

Page 687: ... function register 0063H Prohibit RMW 0 Port 1 TB1OUT0 0 Port 1 TB0OUT0 0 Port 1 TB1IN0 PP5C 1 INT7 PP5C 0 0 Port 1 TB0IN0 PP4C 1 INT6 PP4C 0 0 Port 1 TA7OUT PP3C 1 INT5 PP3C 0 0 Port 1 TA5OUT 0 Port 1 TA3OUT PR3C PR2C PR1C PR0C W 0 0 0 0 PRCR PORTR control register 0066H Prohibit RMW 0 Input 1 Output PR3F PR2F PR1F PR0F W 0 0 0 0 PRFC PORTR function register 0067H Prohibit RMW 0 Port 1 SPCLK 0 Po...

Page 688: ...V2F PV1F PV0F W W 0 0 0 0 0 PVFC PORTV function register 00ABH Prohibit RMW 0 Port 1 SCL 0 Port 1 SDA 0 Port 1 Reserved 0 Port 1 Reserved 0 Port 1 SCLK0 PV0C 1 PW7C PW6C PW5C PW4C PW3C PW2C PW1C PW0C W 0 0 0 0 0 0 0 0 PWCR PORTW control register 00AEH Prohibit RMW 0 Input 1 Output PW7F PW6F PW5F PW4F PW3F PW2F PW1F PW0F W 0 0 0 0 0 0 0 0 PWFC PORTW function register 00AFH Prohibit RMW 0 Port 1 Res...

Page 689: ...4D P63D P62D P61D P60D R W 1 1 1 1 1 1 1 1 P6DR PORT6 drive register 0086H Input Output buffer drive register for standby mode P76D P75D P74D P73D P72D P71D P70D R W 1 1 1 1 1 1 1 P7DR PORT7 drive register 0087H Input Output buffer drive register for standby mode P87D P86D P85D P84D P83D P82D P81D P80D R W 1 1 1 1 1 1 1 1 P8DR PORT8 drive register 0088H Input Output buffer drive register for stand...

Page 690: ...put Output buffer drive register for standby mode PN7D PN6D PN5D PN4D PN3D PN2D PN1D PN0D R W 1 1 1 1 1 1 1 1 PNDR PORTN drive register 0097H Input Output buffer drive register for standby mode PP7D PP6D PP5D PP4D PP3D PP2D PP1D R W 1 1 1 1 1 1 1 PPDR PORTP drive register 0098H Input Output buffer drive register for standby mode PR3D PR2D PR1D PR0D R W 1 1 1 1 PRDR PORTR drive register 0099H Input...

Page 691: ... PWDR PORTW drive register 009EH Input Output buffer drive register for standby mode PX7D PX5D PX4D R W 1 1 1 PXDR PORTX drive register 009FH Input Output buffer drive register for standby mode PZ7D PZ6D PZ5D PZ4D PZ3D PZ2D PZ1D PZ0D R W 1 1 1 1 1 1 1 1 PZDR PORTZ drive register 009AH Input Output buffer drive register for standby mode ...

Page 692: ...00D5H 0 0 0 0 0 0 0 0 INTTA5 TMRA5 INTTA4 TMRA4 ITA5C ITA5M2 ITA5M1 ITA5M0 ITA4C ITA4M2 ITA4M1 ITA4M0 R R W R R W INTETA45 INTTA4 INTTA5 enable 00D6H 0 0 0 0 0 0 0 0 INTTA7 TMRA7 INTTA6 TMRA6 ITA7C ITA7M2 ITA7M1 ITA7M0 ITA6C ITA6M2 ITA6M1 ITA6M0 R R W R R W INTETA67 INTTA6 INTTA7 enable 00D7H 0 0 0 0 0 0 0 0 INTTB01 TMRB0 INTTB00 TMRB0 ITB01C ITB01M2 ITB01M1 ITB01M0 ITB00C ITB00M2 ITB00M1 ITB00M0 ...

Page 693: ...H Always write 0 0 0 0 0 INTLCD ILCD1C ILCDM2 ILCDM1 ILCDM0 R R W INTELCD INTLCD enable 00EAH Always write 0 0 0 0 0 INTI2S1 INTI2S0 II2S1C II2S1M2 II2S1M1 II2S1M0 II2S0C II2S0M2 II2S0M1 II2S0M0 R R W R R W INTEI2S01 INTI2S0 INTI2S1 enable 00EBH 0 0 0 0 0 0 0 0 INTRSC INTRDY IRSCC IRSCM2 IRSCM1 IRSCM0 IRDYC IRDYM2 IRDYM1 IRDYM0 R R W R R W INTENDFC INTRSC INTRDY enable 00ECH 0 0 0 0 0 0 0 0 INTP0 ...

Page 694: ...0 0 0 0 0 0 INTTC7 DMA7 INTTC6 DMA6 ITC7C ITC7M2 ITC7M1 ITC7M0 ITC6C ITC6M2 ITC6M1 ITC6M0 R R W R R W INTETC67 INTTC6 INTTC7 enable 00F4H 0 0 0 0 0 0 0 0 IR0LE W W W 0 0 1 SIMC SIO interrupt mode control 00F5H Prohibit RMW Always write 0 Always write 0 0 INTRX0 edge mode 1 INTRX0 level mode I5EDGE I4EDGE I3EDGE I2EDGE I1EDGE I0EDGE I0LE W W W W W W R W R W 0 0 0 0 0 0 0 0 IIMC0 Interrupt input mod...

Page 695: ...start vector DMA5V5 DMA5V4 DMA5V3 DMA5V2 DMA5V1 DMA5V0 R W 0 0 0 0 0 0 DMA5V DMA5 start vector 0105H DMA5 start vector DMA6V5 DMA6V4 DMA6V3 DMA6V2 DMA6V1 DMA6V0 R W 0 0 0 0 0 0 DMA6V DMA6 start vector 0106H DMA6 start vector DMA7V5 DMA7V4 DMA7V3 DMA7V2 DMA7V1 DMA7V0 R W 0 0 0 0 0 0 DMA7V DMA7 start vector 0107H DMA7 start vector DBST7 DBST6 DBST5 DBST4 DBST3 DBST2 DBST1 DBST0 R W 0 0 0 0 0 0 0 0 D...

Page 696: ...its 1011 8 waits 1101 10 waits 1111 16 waits 0010 1 waits 0110 3 waits 1000 5 waits 1010 7 waits 1100 9 waits 1110 12 waits 0100 20 waits 0011 6 states WAIT pin input mode 0011 6 states WAIT pin input mode B1CSL BLOCK1 CS WAIT control register low 0144H Prohibit RMW Others Reserved Others Reserved B1E B1REC B1OM1 B1OM0 B1BUS1 B1BUS0 R W R W 0 0 0 0 0 0 B1CSH BLOCK1 CS WAIT control register high 01...

Page 697: ...e 1 Enable Dummy cycle 0 No insert 1 Insert 00 ROM SRAM 01 Reserved 10 Reserved 11 Reserved Data bus width 00 8 bits 01 16 bits 10 Reserved 11 Don t set BEXWW3 BEXWW2 BEXWW1 BEXWW0 BEXWR3 BEXWR2 BEXWR1 BEXWR0 R W 0 0 1 0 0 0 1 0 Write waits Read waits 0001 0 waits 0101 2 waits 0111 4 waits 1001 6 waits 1011 8 waits 1101 10 waits 1111 16 waits 0010 1 waits 0110 3 waits 1000 5 waits 1010 7 waits 110...

Page 698: ...e M1S23 M1S22 M1S21 M1S20 M1S19 M1S18 M1S17 M1S16 R W 1 1 1 1 1 1 1 1 MSAR1 Memory start address register 1 0147H Set start address A23 to A16 M2V22 M2V21 M2V20 M2V19 M2V18 M2V17 M2V16 M2V15 R W 1 1 1 1 1 1 1 1 MAMR2 Memory address mask register 2 014AH 0 Compare enable 1 Compare disable M2S23 M2S22 M2S21 M2S20 M2S19 M2S18 M2S17 M2S16 R W 1 1 1 1 1 1 1 1 MSAR2 Memory start address register 2 014BH...

Page 699: ...0 2 5 fSYS 11 3 5 fSYS B1TCRS1 B1TCRS0 B1TCRH1 B1TCRH0 B0TCRS1 B0TCRS0 B0TCRH1 B0TCRH0 R W 0 0 0 0 0 0 0 0 RDTMGCR0 Adjust for Timing of control signal 016AH Select delay time TCRS 00 0 5 fSYS 01 1 5 fSYS 10 2 5 fSYS 11 3 5 fSYS Select delay time TCRH 00 0 fSYS 01 1 fSYS 10 2 fSYS 11 3 fSYS Select delay time TCRS 00 0 5 fSYS 01 1 5 fSYS 10 2 5 fSYS 11 3 5 fSYS Select delay time TCRH 00 0 fSYS 01 1...

Page 700: ...e control of Port 96 97 0 Enable 1 Disable Detection condition 0 no touch 1 touch INT4 interrupt control 0 Disable 1 Enable SPY 0 OFF 1 ON SPX 0 OFF 1 ON SMY 0 OFF 1 ON SMX 0 OFF 1 ON DBC7 DB1024 DB256 DB64 DB8 DB4 DB2 DB1 R W 0 0 0 0 0 0 0 0 1024 256 64 8 4 2 1 TSICR1 TSI control register1 01F1H 0 Disable 1 Enable De bounce time is set by N 64 16 fSYS formula N is sum of number which is set to 1 ...

Page 701: ...111 8 CLK SSAE SRS2 SRS1 SRS0 SRC R W R W 0 1 0 0 0 0 SDRCR SDRAM refresh control register 0252H Always write 0 Self Refresh auto exit function 0 Disable 1 Enable Refresh interval 000 47 states 100 468 states 001 78 states 101 624 states 010 156 states 110 936 states 011 312 states 111 1248 states Auto Refresh 0 Disable 1 Enable SCMM2 SCMM1 SCMM0 R W 0 0 0 SDCMM SDRAM command register 0253H Comman...

Page 702: ...lection 0 LLOAD 1 LVSYNC FR edge 0 LHSYNC front edge 1 LHSYNC back edge LD bus transfer speed 0 normal 1 1 3 FMP3 FMP2 FMP1 FMP0 FML3 FML2 FML1 FML0 R W 0 0 0 0 0 0 0 0 LCDDVM0 LCD divide frame0 register 0283H LCP0 DVM bits 3 0 LHSYNC DVM bits 3 0 FMP7 FMP6 FMP5 FMP4 FML7 FML6 FML5 FML4 R W 0 0 0 0 0 0 0 0 LCDDVM1 LCD divide frame1 register 0288H LCP0 DVM bits 7 4 LHSYNC DVM bit 7 4 COM3 COM2 COM1...

Page 703: ...LH1 LH0 W 0 0 0 0 0 0 0 0 LCDHSP LHSYNC Pulse register 028AH LHSYNC period bits 7 0 LH15 LH14 LH13 LH12 LH11 LH10 LH9 LH8 W 0 0 0 0 0 0 0 0 LCDHSP LHSYNC Pulse register 028BH LHSYNC period bits 15 8 LVP7 LVP6 LVP5 LVP4 LVP3 LVP2 LVP1 LVP0 W 0 0 0 0 0 0 0 0 LCDVSP LVSYNC Pulse register 028CH LVSYNC period bits 7 0 LVP9 LVP8 W 0 0 LCDVSP LVSYNC Pulse register 028DH LVSYNC period bits 9 8 PLV6 PLV5 P...

Page 704: ...ster 0294H Setting bit7 0 for LHSYNC Width LDW7 LDW6 LDW5 LDW4 LDW3 LDW2 LDW1 LDW0 W 0 0 0 0 0 0 0 0 LCDLDW LLOAD width register 0295H LHSYNC width bits 7 0 O0W7 O0W6 O0W5 O0W4 O0W3 O0W2 O0W1 O0W0 W 0 0 0 0 0 0 0 0 LCDHO0W LGOE0 width register 0296H LLOAD width bits 7 0 O1W7 O1W6 O1W5 O1W4 O1W3 O1W2 O1W1 O1W0 W 0 0 0 0 0 0 0 0 LCDHO1W LGOE1 width register 0297H LGOE1 width bits 7 0 O2W7 O2W6 O2W5 ...

Page 705: ...SSA23 LSSA22 LSSA21 LSSA20 LSSA19 LSSA18 LSSA17 LSSA16 R W 0 1 0 0 0 0 0 0 LSASH Start address register LCD sub H 02A6H LCD sub area start address A23 A16 SAHX7 SAHX6 SAHX5 SAHX4 SAHX3 SAHX2 SAHX1 SAHX0 R W 0 0 0 0 0 0 0 0 LSAHX Hot point register LCD sub X 02A8H LCD sub area HOT point 7 0 SAHX9 SAHX8 R W 0 0 LSAHX Hot point register LCD sub X 02A9H LCD sub area HOT point 9 8 SAHY7 SAHY6 SAHY5 SAH...

Page 706: ... WUTM0 02A0H R W W R W R W After system reset 0 0 0 0 After Hot reset Data retained Data retained Data retained PMCCTL PMC Control Register Power Cut Mode 0 Disable 1 Enable Always write 0 Always read as 0 Warm up time 00 29 15 625 ms 01 210 31 25 ms 10 211 62 5 ms 11 212 125 ms ...

Page 707: ...riptor RAM383 Descriptor RAM 383 register 067FH Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined EP0_DATA7 EP0_DATA6 EP0_DATA5 EP0_DATA4 EP0_DATA3 EP0_DATA2 EP0_DATA1 EP0_DATA0 R W Endpoint0 Endpoint 0 register 0780H Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined EP1_DATA7 EP1_DATA6 EP1_DATA5 EP1_DATA4 EP1_DATA3 EP1_DATA2 EP1_DATA1 EP...

Page 708: ...gister Low A 0799H 1 0 0 0 1 0 0 0 PKT_ACTIVE DATASIZE6 DATASIZE5 DATASIZE4 DATASIZE3 DATASIZE2 DATASIZE1 DATASIZE0 R EP2_SIZE_L_A Endpoint 2 size register Low A 079AH 1 0 0 0 1 0 0 0 PKT_ACTIVE DATASIZE6 DATASIZE5 DATASIZE4 DATASIZE3 DATASIZE2 DATASIZE1 DATASIZE0 R EP3_SIZE_L_A Endpoint 3 size register Low A 079BH 1 0 0 0 1 0 0 0 PKT_ACTIVE DATASIZE6 DATASIZE5 DATASIZE4 DATASIZE3 DATASIZE2 DATASI...

Page 709: ... 07C1H 0 0 0 0 0 0 0 0 VALUE_L7 VALUE_L6 VALUE_L5 VALUE_L4 VALUE_L3 VALUE_L2 VALUE_L1 VALUE_L0 R wValue_L wValue register Low 07C2H 0 0 0 0 0 0 0 0 VALUE_H7 VALUE_H6 VALUE_H5 VALUE_H4 VALUE_H3 VALUE_H2 VALUE_H1 VALUE_H0 R wValue_H wValue register High 07C3H 0 0 0 0 0 0 0 0 INDEX_L7 INDEX_L6 INDEX_L5 INDEX_L4 INDEX_L3 INDEX_L2 INDEX_L1 INDEX_L0 R wIndex_L wIndex register Low 07C4H 0 0 0 0 0 0 0 0 I...

Page 710: ..._A EP5_DSET_B EP5_DSET_A EP4_DSET_B EP4_DSET_A R DATASET2 DATASET 2 register 07CDH 0 0 0 0 0 0 0 0 Configured Addressed Default R W R USB_STATE USB state register 07CEH 0 0 1 EP7_EOPB EP6_EOPB EP5_EOPB EP4_EOPB EP3_EOPB EP2_EOPB EP1_EOPB EP0_EOPB W EOP EOP register 07CFH 1 1 1 1 1 1 1 1 EP 2 EP 1 EP 0 Command 3 Command 2 Command 1 Command 0 W COMMAND Command register 07D0H 0 0 0 0 0 0 0 EP3_SELECT...

Page 711: ..._CLKON R W 0 0 0 0 0 0 USBINTFR1 USB interrupt flag register 1 07F0H Prohibit RMW When read 0 Not generate interrupt 1 Generate interrupt When write 0 Clear flag 1 EP1_FULL_A EP1_Empty_A EP1_FULL_B EP1_Empty_B EP2_FULL_A EP2_Empty_A EP2_FULL_B EP2_Empty_B R W 0 0 0 0 0 0 0 0 USBINTFR2 USB interrupt flag register 2 07F1H Prohibit RMW When read 0 Not generate interrupt 1 Generate interrupt When writ...

Page 712: ...EP2_MSK_FB EP2_MSK_EB R W 1 1 1 1 1 1 1 1 USBINTMR2 USB interrupt mask register 2 07F5H 0 Be not masked 1 Be masked EP3_MSK_FA EP3_MSK_EA R W 1 1 USBINTMR3 USB interrupt mask register 3 07F6H 0 Be not masked 1 Be masked MSK_SETUP MSK_EP0 MSK_STAS MSK_STASN MSK_EP1N MSK_EP2N MSK_EP3N R W 1 1 1 1 1 1 1 USBINTMR4 USB interrupt mask register 4 07F7H 0 Be not masked 1 Be masked TRNS_USE WAKEUP SPEED US...

Page 713: ...TXE FDPXE RXMOD RXE R W 0 1 0 0 0 0 0 0 0822H communica tion control 0 disable 1 enable SPCS pin 0 output 0 1 output 1 Data length 0 8bit 1 16bit Transmit mode 0 UNIT 1 Sequential Transmit control 0 disable 1 enable Alignment in Full duplex 0 disable 1 enable Receive Mode 0 UNIT 1 Sequential Receive control 0 disable 1 enable CRC16_7_B CRCRX_TX_B CRCRESET_B R W 0 0 0 SPICT SPI Control register 082...

Page 714: ...ansmit data register 15 8 TXD7 TXD6 TXD5 TXD4 TXD3 TXD2 TXD1 TXD0 R W 0 0 0 0 0 0 0 0 0832H Transmit data register 7 0 TXD15 TXD14 TXD13 TXD12 TXD11 TXD10 TXD9 TXD8 R W 0 0 0 0 0 0 0 0 SPITD1 SPI transmission data1 register 0833H Transmit data register 15 8 RXD7 RXD6 RXD5 RXD4 RXD3 RXD2 RXD1 RXD0 R 0 0 0 0 0 0 0 0 0834H Receive data register 7 0 RXD15 RXD14 RXD13 RXD12 RXD11 RXD10 RXD9 RXD8 R 0 0 ...

Page 715: ...Y2 Y1 Y0 R W 0 0 0 0 0 0 LOCALPY LOCALY register for program 0882H Set BANK number for LOCAL Y 3 is disabled because of overlapped with Common area LYE R W 0 LOCALPY LOCALY register for program 0883H LOCALY BANK 0 disable 1 enable Z7 Z6 Z5 Z4 Z3 Z2 Z1 Z0 R W 0 0 0 0 0 0 0 0 LOCALPZ LOCALZ register for program 0884H Set BANK number for LOCAL Z 3 is disabled because of overlapped with Common area LZ...

Page 716: ... Y3 Y2 Y1 Y0 R W 0 0 0 0 0 0 LOCALLY LOCALY register for LCD 088AH Set BANK number for LOCAL Y 3 is disabled because of overlapped with Common area LYE R W 0 LOCALLY LOCALY register for LCD 088BH LOCALY BANK 0 disable 1 enable Z7 Z6 Z5 Z4 Z3 Z2 Z1 Z0 R W 0 0 0 0 0 0 0 0 LOCALLZ LOCALZ register for LCD 088CH Set BANK number for LOCAL Z 3 is disabled because of overlapped with Common area LZE Z8 R W...

Page 717: ...Y3 Y2 Y1 Y0 R W 0 0 0 0 0 0 LOCALRY LOCALY register for read 0892H Set BANK number for LOCAL Y 3 is disabled because of overlapped with Common area LYE R W 0 LOCALRY LOCALY register for read 0893H LOCALY BANK 0 disable 1 enable Z7 Z6 Z5 Z4 Z3 Z2 Z1 Z0 R W 0 0 0 0 0 0 0 0 LOCALRZ LOCALZ register for read 0894H Set BANK number for LOCAL Z 3 is disabled because of overlapped with Common area LZE Z8 R...

Page 718: ...3 Y2 Y1 Y0 R W 0 0 0 0 0 0 LOCALWY LOCALY register for write 089AH Set BANK number for LOCAL Y 3 is disabled because of overlapped with Common area LYE R W 0 LOCALWY LOCALY register for write 089BH LOCALY BANK 0 disable 1 enable Z7 Z6 Z5 Z4 Z3 Z2 Z1 Z0 R W 0 0 0 0 0 0 0 0 LOCALWZ LOCALZ register for write 089CH Set BANK number for LOCAL Z 3 is disabled because of overlapped with Common area LZE Z8...

Page 719: ...1 Y0 R W 0 0 0 0 0 0 LOCALESY LOCALY register for DMA source 08A2H Set BANK number for LOCAL Y 3 is disabled because of overlapped with Common area LYE R W 0 LOCALESY LOCALY register for DMA source 08A3H LOCALY BANK 0 disable 1 enable Z7 Z6 Z5 Z4 Z3 Z2 Z1 Z0 R W 0 0 0 0 0 0 0 0 LOCALESZ LOCALZ register for DMA source 08A4H Set BANK number for LOCAL Z 3 is disabled because of overlapped with Common...

Page 720: ...R W 0 0 0 0 0 0 LOCALEDY LOCALY register for DMA destination 08AAH Set BANK number for LOCAL Y 3 is disabled because of overlapped with Common area LYE R W 0 LOCALEDY LOCALY register for DMA destination 08ABH LOCALY BANK 0 disable 1 enable Z7 Z6 Z5 Z4 Z3 Z2 Z1 Z0 R W 0 0 0 0 0 0 0 0 LOCALEDZ LOCALZ register for DMA destination 08ACH Set BANK number for LOCAL Z 3 is disabled because of overlapped w...

Page 721: ...1 Y0 R W 0 0 0 0 0 0 LOCALOSY LOCALY register for DMA source 08B2H Set BANK number for LOCAL Y 3 is disabled because of overlapped with Common area LYE R W 0 LOCALOSY LOCALY register for DMA source 08B3H LOCALY BANK 0 disable 1 enable Z7 Z6 Z5 Z4 Z3 Z2 Z1 Z0 R W 0 0 0 0 0 0 0 0 LOCALOSZ LOCALZ register for DMA source 08B4H Set BANK number for LOCAL Z 3 is disabled because of overlapped with Common...

Page 722: ...R W 0 0 0 0 0 0 LOCALODY LOCALY register for DMA destination 08BAH Set BANK number for LOCAL Y 3 is disabled because of overlapped with Common area LYE R W 0 LOCALODY LOCALY register for DMA destination 08BBH LOCALY BANK 0 disable 1 enable Z7 Z6 Z5 Z4 Z3 Z2 Z1 Z0 R W 0 0 0 0 0 0 0 0 LOCALODZ LOCALZ register for DMA destination 08BCH Set BANK number for LOCAL Z 3 is disabled because of overlapped w...

Page 723: ...calculation start 0 1 Start Always read as 0 Reed Solomon ECC generator write control 0 Disable 1 Enable INTERDY INTRSC BUSW ECCS SYSCKE R W R W R W R W R W 0 0 0 0 0 08C2H Ready interrupt 0 Disable 1 Enable Reed Solomon calculation end interrupt 0 Disable 1 Enable Data bus width 0 8 bit 1 16 bit ECC calculation 0 Hamming 1 Reed Solomon Clock control 0 Disable 1 Enable STATE3 STATE2 STATE1 STATE0 ...

Page 724: ... Flash ECC Register 15 8 ECCD7 ECCD6 ECCD5 ECCD4 ECCD3 ECCD2 ECCD1 ECCD0 R 0 0 0 0 0 0 0 0 08CAH NAND Flash ECC Register 7 0 ECCD15 ECCD14 ECCD13 ECCD12 ECCD11 ECCD10 ECCD9 ECCD8 R 0 0 0 0 0 0 0 0 NDECCRD3 NANDF Code ECC Register3 08CBH NAND Flash ECC Register 15 8 ECCD7 ECCD6 ECCD5 ECCD4 ECCD3 ECCD2 ECCD1 ECCD0 R 0 0 0 0 0 0 0 0 08CCH NAND Flash ECC Register 7 0 ECCD15 ECCD14 ECCD13 ECCD12 ECCD11...

Page 725: ...eed Solomon Calculation Result Address Register 7 0 RS1A9 RS1A8 R 0 0 NDRSCA1 NANDF read solomon Result address Register1 08D5H NAND Flash Reed Solomon Calculation Result Address Register 9 8 RS1D7 RS1D6 RS1D5 RS1D4 RS1D3 RS1D2 RS1D1 RS1D0 R 0 0 0 0 0 0 0 0 NDRSCD1 NANDF read solomon Result data Register1 08D6H NAND Flash Reed Solomon Calculation Result Data Register 7 0 RS2A7 RS2A6 RS2A5 RS2A4 RS...

Page 726: ...h Reed Solomon Calculation Result Data Register 7 0 D7 D6 D5 D4 D3 D2 D1 D0 R W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 1FF0H NAND Flash Data Register 7 0 D15 D14 D13 D12 D11 D10 D9 D8 R W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined NDFDTR0 NANDF Data Register0 1FF1H NAND Flash Data Register 15 8 D7 D6 D5 D4 D3 D2 D1 D0 R ...

Page 727: ...s Register0 0906H Destination address for DMA0 23 16 D0CA7 D0CA6 D0CA5 D0CA4 D0CA3 D0CA2 D0CA1 D0CA0 R W 0 0 0 0 0 0 0 0 0908H Transfer count A 7 0 for DMA0 D0CA15 D0CA14 D0CA13 D0CA12 D0CA11 D0CA10 D0CA9 D0CA8 R W 0 0 0 0 0 0 0 0 HDMACA0 DMA Transfer count number A Register0 0909H Transfer count A 15 8 for DMA0 D0CB7 D0CB6 D0CB5 D0CB4 D0CB3 D0CB2 D0CB1 D0CB0 R W 0 0 0 0 0 0 0 0 090AH Transfer cou...

Page 728: ...16H Set destination address for DMA1 23 16 D1CA7 D1CA6 D1CA5 D1CA4 D1CA3 D1CA2 D1CA1 D1CA0 R W 0 0 0 0 0 0 0 0 0918H Set transfer count number A for DMA1 7 0 D1CA15 D1CA14 D1CA13 D1CA12 D1CA11 D1CA10 D1CA9 D1CA8 R W 0 0 0 0 0 0 0 0 HDMACA1 DMA Transfer count number A Register1 0919H Set transfer count number A for DMA1 15 8 D1CB7 D1CB6 D1CB5 D1CB4 D1CB3 D1CB2 D1CB1 D1CB0 R W 0 0 0 0 0 0 0 0 091AH ...

Page 729: ...s Register2 0926H Destination address for DMA2 23 16 D2CA7 D2CA6 D2CA5 D2CA4 D2CA3 D2CA2 D2CA1 D2CA0 R W 0 0 0 0 0 0 0 0 0928H Transfer count A 7 0 for DMA2 D2CA15 D2CA14 D2CA13 D2CA12 D2CA11 D2CA10 D2CA9 D2CA8 R W 0 0 0 0 0 0 0 0 HDMACA2 DMA Transfer count number A Register2 0929H Transfer count A 15 8 for DMA2 D2CB7 D2CB6 D2CB5 D2CB4 D2CB3 D2CB2 D2CB1 D2CB0 R W 0 0 0 0 0 0 0 0 092AH Transfer cou...

Page 730: ...n address Register3 0936H Set destination address for DMA3 23 16 D3CA7 D3CA6 D3CA5 D3CA4 D3CA3 D3CA2 D3CA1 D3CA0 R W 0 0 0 0 0 0 0 0 0938H Transfer count A 7 0 for DMA3 D3CA15 D3CA14 D3CA13 D3CA12 D3CA11 D3CA10 D3CA9 D3CA8 R W 0 0 0 0 0 0 0 0 HDMACA3 DMA Transfer count number A Register3 0939H Transfer count A 15 8 for DMA3 D3CB7 D3CB6 D3CB5 D3CB4 D3CB3 D3CB2 D3CB1 D3CB0 R W 0 0 0 0 0 0 0 0 093AH ...

Page 731: ...s Register4 0946H Destination address for DMA4 23 16 D4CA7 D4CA6 D4CA5 D4CA4 D4CA3 D4CA2 D4CA1 D4CA0 R W 0 0 0 0 0 0 0 0 0948H Transfer count A 15 8 for DMA4 D4CA15 D4CA14 D4CA13 D4CA12 D4CA11 D4CA10 D4CA9 D4CA8 R W 0 0 0 0 0 0 0 0 HDMACA4 DMA Transfer count number A Register4 0949H Transfer count A 15 8 for DMA4 D4CB7 D4CB6 D4CB5 D4CB4 D4CB3 D4CB2 D4CB1 D4CB0 R W 0 0 0 0 0 0 0 0 094AH Transfer co...

Page 732: ...s Register5 0956H Destination address for DMA5 23 16 D5CA7 D5CA6 D5CA5 D5CA4 D5CA3 D5CA2 D54CA1 D5CA0 R W 0 0 0 0 0 0 0 0 0958H Transfer count A 7 0 for DMA5 D5CA15 D5CA14 D5CA13 D5CA12 D5CA11 D5CA10 D5CA9 D5CA8 R W 0 0 0 0 0 0 0 0 HDMACA5 DMA Transfer count number A Register5 0959H Transfer count A 15 8 for DMA5 D5CB7 D5CB6 D5CB5 D5CB4 D5CB3 D5CB2 D5CB1 D5CB0 R W 0 0 0 0 0 0 0 0 095AH Transfer co...

Page 733: ... Register 097EH DMA channel operation 0 Disable 1 Enable DMATE DMATR6 DMATR5 DMATR4 DMATR3 DMATR2 DMATR1 DMATR0 R W 0 0 0 0 0 0 0 0 HDMATR DMA timer Register 097FH Timer operation 0 Disable 1 Enable Maximum bus occupancy time setting The value to be set in DMATR6 0 should be obtained by Maximum bus occupancy time 256 fSYS 00H cannot be set ...

Page 734: ...inputted frequency 11 216 inputted frequency HALT mode 00 Reserved 01 STOP mode 10 IDLE1 mode 11 IDLE2 mode PROTECT EXTIN DRVOSCH DRVOSCL R R W R W R W R W 0 0 0 1 1 EMCCR0 EMC control register0 10E3H Protect flag 0 OFF 1 ON Always write 0 1 External clock fc oscillator drive ability 1 NORMAL 0 WEAK fs oscillator drive ability 1 NORMAL 0 WEAK EMCCR1 EMC control register1 10E4H EMCCR2 EMC control r...

Page 735: ...Invert TA1FF 01 Set TA1FF 10 Clear TA1FF 11 Don t care TA1FF control for inversion 0 Disable 1 Enable TA1FF inversion select 0 TMRA0 1 TMRA1 TA2RDE I2TA23 TA23PRUN TA3RUN TA2RUN R W R W 0 0 0 0 0 TMRA23 prescaler Up counter UC3 Up counter UC2 TA23RUN TMRA23 RUN register 1108H Double buffer 0 Disable 1 Enable IDLE2 0 Stop 1 Operate 0 Stop and clear 1 Run Count up W TA2REG 8 bit timer register 2 110...

Page 736: ...nvert TA5FF 01 Set TA5FF 10 Clear TA5FF 11 Don t care TA5FF control for inversion 0 Disable 1 Enable TA5FF inversion select 0 TMRA4 1 TMRA5 TA6RDE I2TA67 TA67PRUN TA7RUN TA6RUN R W R W 0 0 0 0 0 TMRA67 prescaler Up counter UC7 Up counter UC6 TA67RUN TMRA67 RUN register 1118H Double buffer 0 Disable 1 Enable IDLE2 0 Stop 1 Operate 0 Stop and clear 1 Run Count up W TA6REG 8 bit timer register 2 111A...

Page 737: ...MRB1 source clock 00 TB0IN0 input 01 φT1 10 φT4 11 φT16 TB0CT1 TB0C0T1 TB0E1T1 TB0E0T1 TB0FF0C1 TB0FF0C0 W R W W 1 1 0 0 0 0 1 1 TB1FF0 inversion trigger 0 Disable trigger 1 Enable trigger TB0FFCR TMRB0 Flip Flop control register 1183H Prohibit RMW Always write 11 Always read as 11 When capture UC10 to TB0CP1H L When capture UC10 to TB0CP0H L When UC10 matches with TB0RG1H L When UC10 matches with...

Page 738: ...MRB1 source clock 00 TB1IN0 input 01 φT1 10 φT4 11 φT16 TB1CT1 TB1C0T1 TB1E1T1 TB1E0T1 TB1FF0C1 TB1FF0C0 W R W W 1 1 0 0 0 0 1 1 TB1FF0 inversion trigger 0 Disable trigger 1 Enable trigger TB1FFCR TMRB1 Flip Flop control register 1193H Prohibit RMW Always write 11 Always read as 11 When capture UC12 to TB1CP1H L When capture UC12 to TB0CP0H L When UC12 matches with TB1RG1H L When UC12 matches with...

Page 739: ...interface Mode 01 7 bit UART Mode 10 8 bit UART Mode 11 9 bit UART Mode 00 TA0TRG 01 Baud rate generator 10 Internal clock φ1 11 External clock SCLK0 input BR0ADDE BR0CK1 BR0CK0 BR0S3 BR0S2 BR0S1 BR0S0 R W 0 0 0 0 0 0 0 0 BR0CR Serial channel 0 baud rate control register 1203H Always write 0 16 K 16 division 0 Disable 1 Enable 00 φT0 01 φT2 10 φT8 11 φT32 Divided frequency N setting 0 F BR0K3 BR0K...

Page 740: ... bus status monitor 0 Free 1 Busy INTSBI request monitor 0 Request 1 Cancel Arbitration lost detection monitor 0 1 Detected Slave Address match detection monitor 0 Undetected 1 Detected General call detection monitor 0 Undetected 1 Detected Last receive bit monitor 0 0 1 1 SBICR2 When write Serial bus interface control register 2 1243H Prohibit RMW Master Slave status monitor 0 Slave 1 Master Tran...

Page 741: ...R26 ADR25 ADR24 ADR23 ADR22 R 0 0 0 0 0 0 0 0 ADREG2H AD conversion result register 2 high 12A5H Store Upper 8 bits of an AN2 conversion result ADR31 ADR30 OVR3 ADR3RF R R R 0 0 0 0 ADREG3L AD conversion result register 3 low 12A6H Store Lower 2 bits of AN3 AD conversion result Overrun flag 0 No generate 1 Generate AD conversion result store flag 1 Stored ADR39 ADR38 ADR37 ADR36 ADR35 ADR34 ADR33 ...

Page 742: ...mpare criterion ADR29 ADR28 ADR27 ADR26 ADR25 ADR24 ADR23 ADR22 R W 0 0 0 0 0 0 0 0 ADCM0REGH AD Conversion Result Compare Criterion Register 0 High 12B5H Store Upper 8 bits of an AD conversion result compare criterion ADR21 ADR20 R W 0 0 ADCM1REGL AD Conversion Result Compare Criterion Register 1 Low 12B6H Store Lower 2 bits of an AD conversion result compare criterion ADR29 ADR28 ADR27 ADR26 ADR...

Page 743: ...sion sequence High priority AD conversion BUSY Flag 0 Stop conversion 1 During conversion Start High priority AD conversion 0 Don t Care 1 Start AD conversion Always read as 0 High priority AD conversion at Hard ware trigger 0 Disable 1 Enable Select Hard ware trigger 00 INTTB10 interrupt 01 Reserved 10 ADTRG 11 I2S Sampling Counter Output HADCH2 HADCH1 HADCH0 R W R W 0 0 0 0 ADMOD3 AD mode contro...

Page 744: ...W R W 1 0 0 0 0 0 WDMOD WDT mode register 1300H WDT control 1 Enable Select detecting time 00 2 15 fIO 01 2 17 fIO 10 2 19 fIO 11 2 21 fIO IDLE2 0 Stop 1 Operate 1 Internally connects WDT out to the reset pin Always write 0 W WDCR WDT control register 1301H Prohibit RMW B1H WDT disable code 4E WDT clear code ...

Page 745: ...s 1 day MO4 MO3 MO2 MO1 MO0 R W 1325H Undefined PAGE0 0 is read 10 month 8 month 4 month 2 month 1 month MONTHR Month register PAGE1 0 is read 0 Indicator for 12 hours 1 Indicator for 24 hours YE7 YE6 YE5 YE4 YE3 YE2 YE1 YE0 R W 1326H Undefined PAGE0 80 years 40 years 20 years 10 years 8 years 4 years 2 years 1 year YEARR Year register PAGE1 0 is read Leap year setting 00 Leap year 01 One year aft...

Page 746: ...vert 1 Invert Always write 0 Output frequency 0 Alarm 1 Melody ML7 ML6 ML5 ML4 ML3 ML2 ML1 ML0 R W 0 0 0 0 0 0 0 0 MELFL Melody frequency L register 1332H Melody frequency set Low 8bit MELON ML11 ML10 ML9 ML8 R W R W 0 0 0 0 0 MELFH Melody frequency H register 1333H Melody counter control 0 Stop and clear 1 Start Melody frequency set Upper 4 bits IALM4E IALM3E IALM2E IALM1E IALM0E R W 0 0 0 0 0 0 ...

Page 747: ... B019 B018 B017 B016 W Undefined I2S0BUF I2S Transmission Buffer Register0 1800H Prohibit RMW Transmission buffer register FIFO 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 B115 B114 B113 B112 B111 B110 B109 B108 B107 B106 B105 B104 B103 B102 B101 B100 W Undefined Transmission buffer register FIFO 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 B131 B130 B129 B128 B127 B126 B125 B124 B123 B122 B121 B120 ...

Page 748: ...04 WS03 WS02 WS01 WS00 R W 0 0 0 0 0 0 I2S0C I2S0 Divider Value Setting Register 180BH Divider value for WS signal 6 bit counter TXE1 CNTE1 DIR1 BIT1 DTFMT11 DTFMT10 SYSCKE1 R W R W R W R W R W R W R W 0 0 0 0 0 0 0 1818H Transmit 0 Stop 1 Start Counter control 0 Clear 1 Start Transmis sion start BIT 0 MSB 1 LSB Bit length 0 8 bits 1 16 bits Output format 00 I2S 10 Right 01 Left 11 Reserved System...

Page 749: ...ined MACMB_LH Data register Multiplier B LH 1BE5H Multiplier B data register 15 8 MB23 MB22 MB21 MB20 MB19 MB18 MB17 MB16 R W Undefined MACMB_HL Data register Multiplier B HL 1BE6H Multiplier B data register 23 16 MB31 MB30 MB29 MB28 MB27 MB26 MB25 MB24 R W Undefined MACMB_HH Data register Multiplier B HH 1BE7H Multiplier B data register 31 24 OR7 OR6 OR5 OR4 OR3 OR2 OR1 OR0 R W Undefined MACOR_LL...

Page 750: ...L 1BEEH Multiply and Accumulate data register 55 48 OR63 OR62 OR61 OR60 OR59 OR58 OR57 OR56 R W Undefined MACOR_HHH Data register Multiply and Accumulate HHH 1BEFH Multiply and Accumulate data register 63 56 MOVF MOPST MSTTG2 MSTTG1 MSTTG0 MSGMD MOPMD1 MOPMD0 R W W R W R W R W 0 0 0 0 0 0 0 0 MACCR MAC Control Register 1BFCH Over flow flag 0 no over flow 1 generate over flow Start calculation cont...

Page 751: ...TMP92CZ26A 92CZ26A 748 6 Package P FBGA228 1515 0 80A5 TOP VIEW BOTTOM VIEW ...

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