TMP92CZ26A
92CZ26A-16
Figure 3.1.1 TMP92CZ26A Reset timing chart
R e a d
W r i t e
f
sy
s
A
23
∼
0
DATA-IN
D0
∼
15
D0
∼
15
Sampling
(After reset is released, it is started
from 1 wait read
cycle)
: High-Z
Sampling
RESET
RD
WRxx
SRWR
0FF
FF00
H
DATA-IN
DAT
A
-O
UT
CS0,1, 3
CS2
SRxxB
SRxxB
f
SYS
×
(15.5
∼
16
.5) Clock