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4. CIRCUIT OPERATION
Block diagram of CC / EDS circuit is shown in figure 13-4,
and block diagram of QM01 is shown in figure 13-5.
Video signal which is input to pin 9 of UM01 is changed to
1 Vp-p signal which is band-limited to 600kHz by the
input circuit, and it is supplied to pin 7 of QM01. Inside
QA01, line 21 signal is extracted from input video signal,
and is recovered on clock and data. Recovered data is
decoded by command processor and converted to display
signal of R, G, B, Ys in Output Logic section. The display
signal is output at pins 18, 2, 3 and 17 in the CMOS level
of positive polarity. The display output and OSD are
switched by QR01 in UM01, and the selected signal is sent
to
V/C/D IC. When the display of CC/EDS and OSD are
superimposed, OSD is the first priority. H. sync signal with
negative CMOS level is input to pin 5 of QM01. This signal
becomes the standard signal of PLL circuit in IC.
Loop filter for PLL circuit is connected to pin 9. QM01 is
controlled by I2C bus connected to pins 14 and 15.
Summary of Contents for CF35E50
Page 6: ...6 SECTION I OUTLINE ...
Page 13: ...13 7 CN32D90 BLOCK DIAGRAM ...
Page 16: ...16 SECTION II TUNER IF MTS S PRO MODULE ...
Page 24: ...24 SECTION III CHANNEL SELECTION CIRCUIT ...
Page 41: ...41 SECTION IV AUDIO OUTPUT CIRCUIT ...
Page 44: ...44 SECTION V A V SWITCHING CIRCUIT ...
Page 47: ...47 SECTION VI VIDEO PROCESSING CIRCUIT ...
Page 52: ...52 SECTION VII V C D IC ...
Page 55: ...55 SECTION VIII PIP MODULE ...
Page 58: ...58 SECTION IX SYNC SEPARATION H AFC H OSCILLATOR CIRCUITS ...
Page 63: ...63 SECTION X VERTICAL OUTPUT CIRCUIT ...
Page 69: ...69 SECTION XI HORIZONTAL DEFLECTION CIRCUIT ...
Page 85: ...85 SECTION XII DEFLECTION DISTORTION CORRECTION CIRCUIT Side DPC Circuit ...
Page 92: ...92 SECTION XIII CLOSED CAPTION EDS CIRCUIT ...
Page 98: ...98 SECTION XIV POWER CIRCUIT ...
Page 109: ...109 SECTION XV DSP CIRCUIT ...
Page 125: ...125 SECTION XVI FAILURE DIAGNOSIS PROCEDURES ...
Page 139: ......