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114
5. DSP (Digital Surround Processor) IC
Input signal entered into analog input pin 4 of DSP IC QD03
(YM7128B) is converted to 14 bit digital signal with the
sampling frequency 23.6 kHz by A/D converter of 14 bit
floating system, and enters digital delay circuit through
digital attenuator VM and doubler.
The digital delay circuit has nine output taps, and the delay
time of each tap can be controlled independently, also each
tap position can be switched by T0 to T8 register.
In a minute, the T0 output passes through the primary FIR
(Finite Impulse Response) type low pass filter, and reduction
processing is performed by VC, then it feed-backed to the
delay input after it is added to the doubler described above.
The output of eight taps T1 to T8 is added after performing
reduction processing by GL1~GL8, GR1~GR8, and reduction
processing is performed by the digital attenuator VL or VR,
and an analog output is created by D/A converter after
passing through digital filter, comes out from pin 7 or 8.
The digital attenuated value, delay time and the coefficient
of FIR type low pass filter are set by writing the data on the
register.
This process is performed by loading three data from sub
microcomputer to microcomputer interface.
This unit has four modes as surround mode. The setting
values are described in Table 15-1.
Table 15-1 DSP control factor
Mode
OFF
DOLBY
THEATER
STADIUM
NIGHT CLUB
CONCERT
UNIT
Control
SURROUND
HALL HALL
-VM (IN)
-
¥
P-0
P0
P0
P0
P0
dB
VL (LO)
-
¥
P0~ -
¥
P0~ -
¥
P0~ --
¥
P0~ --
¥
VR (RO)
P0
P0
P0
P0
P0
VC (Echo)
-
¥
-
¥
M-6
M-10
M-8
GL1
P-4
M-2
M-2
P-2
2
M-6
-
¥
P-4
P-10
3
P-12
P-6
P-16
4
P-12
M-10
-
¥
5
-
¥
-
¥
6
7
8
GR1
P0
2
-
¥
P0
3
P-18
4
-
¥
5
P-2
P-6
P-4
6
M-2
M-6
P-8
7
P-8
M-10
P-8
8
P-10
P-12
P-14
T0 (Delay)
0
0
0
100.0
19.4
51.6
msec
1
19.4
12.9
93.6
12.9
71.0
2
0
38.7
100.0
19.4
83.9
3
71.0
100.0
22.6
100.0
4
87.1
0
29.0
0
5
29.0
6.5
64.5
6
45.2
9.7
80.7
7
83.9
25.3
90.4
8
100.0
35.5
100.0
C0 (Filter)
0
0.71875
0.59375
0.875
—
1
0.28125
0.40625
0.125
—
Summary of Contents for CF35E50
Page 6: ...6 SECTION I OUTLINE ...
Page 13: ...13 7 CN32D90 BLOCK DIAGRAM ...
Page 16: ...16 SECTION II TUNER IF MTS S PRO MODULE ...
Page 24: ...24 SECTION III CHANNEL SELECTION CIRCUIT ...
Page 41: ...41 SECTION IV AUDIO OUTPUT CIRCUIT ...
Page 44: ...44 SECTION V A V SWITCHING CIRCUIT ...
Page 47: ...47 SECTION VI VIDEO PROCESSING CIRCUIT ...
Page 52: ...52 SECTION VII V C D IC ...
Page 55: ...55 SECTION VIII PIP MODULE ...
Page 58: ...58 SECTION IX SYNC SEPARATION H AFC H OSCILLATOR CIRCUITS ...
Page 63: ...63 SECTION X VERTICAL OUTPUT CIRCUIT ...
Page 69: ...69 SECTION XI HORIZONTAL DEFLECTION CIRCUIT ...
Page 85: ...85 SECTION XII DEFLECTION DISTORTION CORRECTION CIRCUIT Side DPC Circuit ...
Page 92: ...92 SECTION XIII CLOSED CAPTION EDS CIRCUIT ...
Page 98: ...98 SECTION XIV POWER CIRCUIT ...
Page 109: ...109 SECTION XV DSP CIRCUIT ...
Page 125: ...125 SECTION XVI FAILURE DIAGNOSIS PROCEDURES ...
Page 139: ......