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89
Fig. 12-7
4. ACTUAL CIRCUIT
In the actual circuit, the resonant capacitor is split into two as
shown in Fig. 12-7. One, C440, is inserted between the
collector of the H. OUT transistor and ground and another
C444 inserted between the collector and emitter. In Fig. 16-
7, C440 is expressed as C1 and C444 as C2, and the resonant
current path for the flyback period is shown by arrows.
In a conventional circuit, when brightness of a picture tube
varies, high voltage current varies and the high voltage also
varies. As a result, horizontal amplitude also varies.
However, in this circuit, the horizontal amplitude variation
can be suppressed to near zero if the high voltage current
varies with variation of the high voltage.
When the scanning period completes, the energy stored in
the deflection yoke LDY is transferred to the resonant
capacitor in a form of current Iy. In this case, the current is
split into two; Iy1 passing through C1, C3 and Iy2 passing
through C2. In the same way, the energy stored in the
primary winding of the FBT is transferred to the resonant
capacitor in the form of Ip. In this case, the current (path) is
also split into two; Ip1 passing through C1 and Ip2 passing
through C2, C3. Concequently, the current differences
between Iy1 and Ip2 (Iy1-Ip2) passes through C3.
When the high voltage current IH reduces with a dark
picture, the current Ip in the primary circuit decreases, so Ip1
and Ip2 also decrease. However, a current flowing into (Iy1-
Ip2) increases as Ip2 decreases. As a result, the pulse
developing at the point B increases and the voltage Vm at
Csm also increases as shown in Fig. 12-8. That is, when a
dark picture appears, the voltage across S-curve capacitor Cs
increases as shown in Fig. 12-8, the high voltage rises, and
the horizontal amplitude is going to decrease. But, as Vs
increases, the deflection yoke current increases and this
works to increase the horizontal amplitude. Accordingly, if
the brightness of picture changes, the horizontal amplitude is
maintained at a constant value. This is one of the fine features
the circuit has.
Fig. 12-8
FBT
I
H
V
B
Vm
Csm
C
3
V
S
C
S
Lm
C
2
I
P2
I
Y1
I
Y1
C
1
I
Y
I
P2
I
P1
L
DY
H.
OUT
I
P
VS
V
B
0
Vm
Summary of Contents for CF35E50
Page 6: ...6 SECTION I OUTLINE ...
Page 13: ...13 7 CN32D90 BLOCK DIAGRAM ...
Page 16: ...16 SECTION II TUNER IF MTS S PRO MODULE ...
Page 24: ...24 SECTION III CHANNEL SELECTION CIRCUIT ...
Page 41: ...41 SECTION IV AUDIO OUTPUT CIRCUIT ...
Page 44: ...44 SECTION V A V SWITCHING CIRCUIT ...
Page 47: ...47 SECTION VI VIDEO PROCESSING CIRCUIT ...
Page 52: ...52 SECTION VII V C D IC ...
Page 55: ...55 SECTION VIII PIP MODULE ...
Page 58: ...58 SECTION IX SYNC SEPARATION H AFC H OSCILLATOR CIRCUITS ...
Page 63: ...63 SECTION X VERTICAL OUTPUT CIRCUIT ...
Page 69: ...69 SECTION XI HORIZONTAL DEFLECTION CIRCUIT ...
Page 85: ...85 SECTION XII DEFLECTION DISTORTION CORRECTION CIRCUIT Side DPC Circuit ...
Page 92: ...92 SECTION XIII CLOSED CAPTION EDS CIRCUIT ...
Page 98: ...98 SECTION XIV POWER CIRCUIT ...
Page 109: ...109 SECTION XV DSP CIRCUIT ...
Page 125: ...125 SECTION XVI FAILURE DIAGNOSIS PROCEDURES ...
Page 139: ......