Toshiba CF35E50, Technical Training Manual

Page: 61 / 139

61
distortion due to phase difference are incompatible. That
is,to improve the jitter under poor field strength, response
speed must be slowed by lowering the AFC sensitivity. On
the other hand, to improve distortion due to the phase
difference, the response must be increased by increasing the
AFC sensitivity.
In a conventional AFC circuit, setting of the sensitivity is
carried out at one part only, so an compromise point for both
characteristics must be found. However, with the double
AFC circuit employed this time, for the jitter the AFCI loop
works best with decreasing the sensitivity and for the phase
distortion the AFCII loop works with increasing the
sensitivity.
3. H OSCILLATOR CIRCUIT
3-1. Outline
A 503 kHz (32 x fH) voltage controlled type oscillator with
a ceramic oscillation element is used to generate a clock
pulse and the clock is counted down, thereby obviating the
need of adjustments for both the H and V deflection process
circuit.
3-2. Theory of Operation
(1) The H sync signal used as a reference signal enters from
the sync separation circuit to the AFCI circuit. At the
same time, the fH pulse created by counting down the
32 x fH pulse generated in the ceramic oscillator enters
the H AFCI circuit. Phase difference between these two
signals enters an integration circuit (low pas filter)
connected to pin 4 and converted into a DC voltage
(AFC voltage).
Fig. 9-4
17 20 21
SYNC
IN
2V
P-P
H Vcc
SYNC
SEPARATION
CIRCUIT
H AFC I
CIRCUIT
32 x fH
VCO
H COUNT
DOWN
H AFC II
CIRCUIT
TA1222N