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TOPWAY

LCD Module User Manual

LMT070DICFWD-NJN

URL:

www.topwaydisplay.com

Document Name: LMT070DICFWD-NJN-Manual-Rev0.2.DOC

Page: 21 of 33

REG[89h] PLL Control Register 2 (PLLC2)

Bit

Description

Default

Access

7-3 NA

0

RO

2-0

PLLDIVK[2:0]

PLL Output divider
000b : divided by 1.
001b : divided by 2.
010b : divided by 4.
011b : divided by 8.
100b : divided by 16.
101b : divided by 32.
110b : divided by 64.
111b : divided by 128.

03h

RW

REG[8Ah] PWM1 Control Register (P1CR)

Bit

Description

Default

Access

7

PWM1 Enable

0 : Disable, PWM1_OUT level depends on P1CR bit6.
1 : Enable.

0

RW

6

PWM1 Disable Level

0 : PWM1_OUT is Normal L when PWM disable or Sleep
     mode.
1 : PWM1_OUT is Normal H when PWM disable or Sleep
     mode.
The bit is only usable when P1CR bit 4 is  0

0

RW

5

Reserved

0

RO

4

PWM1 Function Selection

0 : PWM1 function.
1 : PWM1 output a fixed frequency signal and it is equal to 1
     /16  oscillator clock.
PWM1 = F

OSC

/ 16(

Note

)

0

RW

3-0

PWM1 Clock Source Divide Ratio

0000b : SYS_CLK / 1

1000b : SYS_CLK / 256

0001b : SYS_CLK / 2

1001b : SYS_CLK / 512

0010b : SYS_CLK / 4

1010b : SYS_CLK / 1024

0011b : SYS_CLK / 8

1011b : SYS_CLK / 2048

0100b : SYS_CLK / 16

1100b : SYS_CLK / 4096

0101b : SYS_CLK / 32

1101b : SYS_CLK / 8192

0110b : SYS_CLK / 64

1110b : SYS_CLK / 16384

0111b : SYS_CLK / 128

1111b : SYS_CLK / 32768

For example, if the system clock is 20MHz and Bit[3:0]
=0001b, when the clock source of PWM1 is 10MHz.

0

RW

Note : FOSC is the frequency of external oscillator.

REG[8Bh] PWM1 Duty cycle Register (P1DCR)

Bit

Description

Default

Access

7-0

PWM Cycle Duty Selection Bit

00h   1 / 256 Duty with PWM1 clock source.
01h   2 / 256 Duty with PWM1 clock source.
02h   3 / 256 Duty with PWM1 clock source.
:
:
FEh   255 / 256 Duty with PWM1 clock source.
FFh   256 / 256 Duty with PWM1 clock source.

0

RW

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Summary of Contents for LMT070DICFWD-NJN

Page 1: ...70DICFWD NJN Manual Rev0 2 DOC Page 1 of 33 LMT070DICFWD NJN LCD Module User Manual Prepared by Liutihou Checked by Approved by Date 2016 11 23 Date Date Rev Descriptions Release Date 0 1 Preliminary 2016 06 27 0 2 Update 5 1 describe 2016 11 23 ...

Page 2: ...eral Specification 3 2 Block Diagram 3 3 Terminal Functions 4 3 1 Interface 4 4 Absolute Maximum Ratings 5 5 Electrical Characteristics 5 5 1 DC Characteristics MCU terminal 5 6 AC Characteristics 5 6 1 AC Timing 5 6 2 TFT Controller Reset Timing 6 6 3 Panel Setting of Timing 7 7 Commands 8 8 Optical Characteristics 31 9 Precautions of using LCD Modules 33 ...

Page 3: ...e Diagonal 7 0 Outline Dimension 190 0 x 112 0x 12 1max mm see attached drawing for details Active Area 154 08 x 85 92 mm Color Depth 65k Number of dots 800 x 480 Pixel Pitch 0 1296 x0 179 mm Pixel Configuration R G B Vertical Stripe Backlight White LED Surface Treatment Anti Glare Treatment Viewing Direction 6 o clock Gray scale Inversion 2 12 o clock 3 Operating Temperature 20 70 C Storage Tempe...

Page 4: ...D H Data or Instruction latch into the LCD module 6 RD I WR H RD L Data or Status read form the LCD module 7 CS I Chip Select CS L enable access to the LCD interface CS H disable access to the LCD interface 8 VSS 0V P Power Ground 9 WAIT O Controller busy signal output MCU should poll this signal before accessing the LCD module 10 INT O Interrupt signal output 11 RST I Reset signal RST L Initializ...

Page 5: ...AX Unit Applicable Pin Operating Voltage VDD 4 7 5 0 5 3 V VDD Input High Voltage VIH 3 0V 3 3 V RD WR RS CS DB0 DB15 RST Input Low Voltage VIL VSS 0 5 V Output Signal High Voltage VOH 3 3 V DB0 DB15 WAIT INT Output Signal Low Voltage VOL VSS V Operating Current IDD 350 mA All black Backlight ON 1 120 mA All black Backlight OFF 2 Note 1 REG 8Ch 40H For Backlight ON 2 REG 8Ch 00H For Backlight OFF ...

Page 6: ... com Document Name LMT070DICFWD NJN Manual Rev0 2 DOC Page 6 of 33 Register Write Read timing for CPU 16 Bit 6 2 TFT Controller Reset Timing VSS 0V VDD 5 0V TOP 25 C Item Symbol MIN TYP MAX Unit Reset setup time trs 2 ms Reset pulse trst 0 2 ms Reset hold time trh 2 ms ...

Page 7: ...mark MIN TYP MAX Horizontal Display Area thd 800 CLKIN CLKIN Frequency 60HZ fclk 30 50 MHZ One Horizontal Line th 889 928 1143 CLKIN HSD pulse width thpw 1 48 255 CLKIN HSD Blanking thb 88 CLKIN HSD Front Porch thfp 1 40 255 CLKIN Vertical Display Area tvd 480 TH VSD period time tv 513 525 767 TH VSD pulse width tvpw 3 3 255 TH VSD Blanking tvb tvb 32 TH VSD Front Porch tvfp tvfp 1 13 255 TH ...

Page 8: ...0 WO REG 02h Memory Read Write Command MRWC Bit Description Default Access 7 0 Write Function Memory Write Data Data to write in memory corresponding to the setting of MWCR1 3 2 Continuous data write cycle can be accepted in bulk data write case Read Function Memory Read Data Data to read from memory corresponding to the setting of MWCR1 3 2 Continuous data read cycle can be accepted in bulk data ...

Page 9: ...erial Flash ROM CLK Setting Register SFCLR Bit Description Default Access 7 2 NA 0 RO 1 0 Serial Flash ROM Clock Frequency Setting 0xb SFCL frequency System clock frequency When DMA enable and Color depth 256 color SFCL frequency System clock frequency 2 10b SFCL frequency System clock frequency 2 11b SFCL frequency System clock frequency 4 0 RW REG 10h System Configuration Register SYSR Bit Descr...

Page 10: ...ter HNDR Bit Description Default Access 7 5 NA 0 RO 4 0 Horizontal Non Display Period HNDP Bit 4 0 This register specifies the horizontal non display period Horizontal Non Display Period pixels HNDR 1 x8 HNDFTR 2 1 x2 2 0 RW REG 17h HSYNC Start Position Register HSTR Bit Description Default Access 7 5 NA 0 RO 4 0 HSYNC Start Position 4 0 The starting position from the end of display area to the be...

Page 11: ... VSYNC VSYNC Start Position Line VSTR 1 0 RW REG 1Eh VSYNC Start Position Register VSTR1 Bit Description Default Access 7 1 NA 0 RO 0 VSYNC Start Position 8 The starting from the end of display area to the beginning of VSYNC VSYNC Start Position Line VSTR 1 0 RW REG 1Fh VSYNC Pulse Width Register VPWR Bit Description Default Access 7 VSYNC Polarity 0 Low active 1 High active 0 RW 6 0 VSYNC Pulse W...

Page 12: ...d coding of ISO IEC 8859 1 4 which supports English and most of European country languages 00b ISO IEC 8859 1 01b ISO IEC 8859 2 10b ISO IEC 8859 3 11b ISO IEC 8859 4 0 RW REG 22h Font Control Register1 FNCR1 Bit Description Default Access 7 Full Alignment Selection Bit 0 Full alignment is disable 1 Full alignment is enable 0 RW 6 Font Transparency 0 Font with background color 1 Font with backgrou...

Page 13: ...l Offset 9 8 The display offset of the v ertical direction changing the value will cause the effect of scrolling at vertical direction 0 RW REG 29h Font Line Distance Setting Register FLDR Bit Description Default Access 7 5 NA 0 RO 4 0 Font Line Distance Setting Setting the font character line distance when setting memory font write cursor auto move Unit pixel 0 RW REG 2Ah Font Write Cursor Horizo...

Page 14: ...30H24T3Y 011b GT30L24M1Z 100b GT30L32S4W GT30H32S4W 0 RW 4 2 FONT ROM Coding Setting For specific GT serial Font ROM the coding method must be set for decoding 000b GB2312 001b GB12345 GB18030 010b BIG5 011b UNICODE 100b ASCII 101b UNI Japanese 110b JIS0208 111b Latin Greek Cyrillic Arabic 0 RW 1 0 ASCII Latin Greek Cyrillic Arabic Latin ASCII Latin Greek Cyrillic Arabic Latin 00b Normal Normal NA...

Page 15: ...ndow HSSW0 Bit Description Default Access 7 0 Horizontal Start Point of Scroll Window 7 0 0 RW REG 39h Horizontal Start Point 1 of Scroll Window HSSW1 Bit Description Default Access 7 2 NA 0 RO 1 0 Horizontal Start Point of Scroll Window 9 8 0 RW REG 3Ah Vertical Start Point 0 of Scroll Window VSSW0 Bit Description Default Access 7 0 Vertical Start Point of Scroll Window 7 0 0 RW REG 3Bh Vertical ...

Page 16: ... 0 RW 0 Memory Read Cursor Auto Increase Disable 0 Cursor auto increases when memory read 1 Cursor doesn t auto increases when memory read 0 RW REG 41h Memory Write Control Register 1 MWCR1 Bit Description Default Access 7 Graphic Cursor Enable 0 Graphic Cursor disable 1 Graphic Cursor enable 0 RW 6 4 Graphic Cursor Selection Bit Select one from eight graphic cursor types 000b to 111b 000b Graphic...

Page 17: ...REG 49h Memory Write Cursor Vertical Position Register 1 CURV1 Bit Description Default Access 7 1 NA 0 RO 0 Memory Write Cursor Vertical Location 8 0 RW REG 4Ah Memory Read Cursor Horizontal Position Register 0 RCURH0 Bit Description Default Access 7 0 Memory Read Cursor Horizontal Location 7 0 0 RW REG 4Bh Memory Read Cursor Horizontal Position Register 1 RCURH01 Bit Description Default Access 7 ...

Page 18: ...uous block of memory 0 RW 4 0 NA 0 RO REG 51h BTE Function Control Register1 BECR1 Bit Description Default Access 7 5 BTE ROP Code Bit 3 0 ROP is the acronym for Raster Operation Some of BTE operation code has to collocate with ROP for the detailed function Please refer to the Section 7 6 0 RW 4 0 BTE Operation Code Bit 3 0 RA8875 includes a 2D BTE Engine it can execute 13 BTE functions the operat...

Page 19: ...ystem CLK x 4 011b System CLK 8 100b System CLK x 16 101b System CLK 32 110b System CLK x64 111b System CLK 128 0 RW REG 71h Touch Panel Control Register 1 TPCR1 Bit Description Default Access 7 N A 0 RO 6 TP Manual Mode Enable 0 Auto mode 1 Using the manual mode 0 RW 5 TP ADC Reference Voltage Source 0 Vref generated from internal circuit No external voltage is needed 1 Vref from external source ...

Page 20: ...raphic Cursor Horizontal Location 9 8 0 RW REG 82h Graphic Cursor Vertical Position Register 0 GCVP0 Bit Description Default Access 7 0 Graphic Cursor Vertical Location 7 0 0 RW REG 83h Graphic Cursor Vertical Position Register 1 GCVP1 Bit Description Default Access 7 1 NA 0 RO 0 Graphic Cursor Vertical Location 8 0 RW REG 84h Graphic Cursor Color 0 GCC0 Bit Description Default Access 7 0 Graphic ...

Page 21: ...served 0 RO 4 PWM1 Function Selection 0 PWM1 function 1 PWM1 output a fixed frequency signal and it is equal to 1 16 oscillator clock PWM1 FOSC 16 Note 0 RW 3 0 PWM1 Clock Source Divide Ratio 0000b SYS_CLK 1 1000b SYS_CLK 256 0001b SYS_CLK 2 1001b SYS_CLK 512 0010b SYS_CLK 4 1010b SYS_CLK 1024 0011b SYS_CLK 8 1011b SYS_CLK 2048 0100b SYS_CLK 16 1100b SYS_CLK 4096 0101b SYS_CLK 32 1101b SYS_CLK 819...

Page 22: ... 8192 0110b SYS_CLK 64 1110b SYS_CLK 16384 0111b SYS_CLK 128 1111b SYS_CLK 32768 For example if the system clock is 20MHz and Bit 3 0 0010b then the clock source of PWM2 is 5MHz 0 RW REG 8Dh PWM2 Control Register P2DCR Bit Description Default Access 7 0 PWM Cycle Duty Selection Bit 00h 1 256 Duty with PWM2 clock source 01h 2 256 Duty with PWM2 clock source 02h 3 256 Duty with PWM2 clock source FEh...

Page 23: ... Start Address Register0 DLHSR0 Bit Description Default Access 7 0 Draw Line Square Horizontal Start Address 7 0 0 RW REG 92h Draw Line Square Horizontal Start Address Register1 DLHSR1 Bit Description Default Access 7 2 NA 0 RO 1 0 Draw Line Square Horizontal Start Address 9 8 0 RW REG 93h Draw Line Square Vertical Start Address Register0 DLVSR0 Bit Description Default Access 7 0 Draw Line Square ...

Page 24: ...w Circle Center Vertical Address 8 0 RW REG 9Dh Draw Circle Radius Register DCRR Bit Description Default Access 7 0 Draw Circle Radius 7 0 0 RW REG A0h Draw Ellipse Ellipse Curve Circle Square Control Register Bit Description Default Access 7 Draw Ellipse Circle Square start Signal Write Function 0 Stop the drawing function 1 Start the drawing function Read Function 0 Drawing function complete 1 D...

Page 25: ...ertical Address 7 0 0 RW REG A8h Draw Ellipse Circle Square Center Vertical Address Register1 DEVR1 Bit Description Default Access 7 1 NA 0 RO 0 Draw Ellipse Circle Square Center Vertical Address 8 0 RW REG A9h Draw Triangle Point 2 Horizontal Address Register0 DTPH0 Bit Description Default Access 7 0 Draw Triangle Point 2 Horizontal Address 7 0 0 RW REG AAh Draw Triangle Point 2 Horizontal Addres...

Page 26: ...h bit 1 1 Block Mode DMA Block Height 7 0 0 RW REG B7h Block Height REG 1 BHR1 Bit Description Default Access 7 2 NA 0 RO 1 0 DMA Block Height 9 8 0 RW REG B8h Source Picture Width REG 0 SPWR0 DMA Transfer Number REG 2 DTNR2 Bit Description Default Access 7 3 DMA Source Picture Width 7 3 0 RW 2 0 When REG BFh bit 1 0 Continuous Mode DMA Transfer Number 18 16 When REG BFh bit 1 1 Block Mode DMA Sou...

Page 27: ... Scan Controller Register 2 KSCR2 Bit Description Default Access 7 Key Scan Wakeup Function Enable Bit 0 Key Scan Wakeup function is disable 1 Key Scan Wakeup function is enable 0 RW 6 4 NA 0 RO 3 2 Long Key Timing Adjustment System Clock 20MH 40MHz 60MHz 00b 1 25 sec 0 625 sec 0 3125 sec 01b 2 5 sec 1 25 sec 0 625 sec 10b 3 75 sec 1 875 sec 0 9375 sec 11b 5 sec 2 5 sec 1 25 sec 0 RW 1 0 Numbers o...

Page 28: ...ng Windows Start Address YA 0 FWSAYA0 Bit Description Default Access 7 0 Floating Windows Start Address YA 7 0 0 RW REG D3h Floating Windows Start Address YA 1 FWSAYA1 Bit Description Default Access 7 1 NA 0 RO 0 Floating Windows Start Address YA 8 0 RW REG D4h Floating Windows Width 0 FWW0 Bit Description Default Access 7 0 Floating Windows Width Setting 7 0 0 RW REG D5h Floating Windows Width 1 ...

Page 29: ...ss 7 0 Direct access mode Read Data buffer 0 RO REG F0h Interrupt Control Register1 INTC1 Bit Description Default Access 7 5 NA 0 RO 4 KEYSCAN Interrupt Enable Bit 0 Disable KEYSCAN interrupt 1 Enable KEYSCAN interrupt 0 RW 3 DMA Interrupt Enable Bit 0 Disable DMA interrupt 1 Enable DMA interrupt 0 RW 2 Touch Panel Interrupt Enable Bit 0 Disable Touch interrupt 1 Enable Touch interrupt 0 RW 1 BTE ...

Page 30: ...atus 0 No Touch Panel interrupt happens 1 Touch Panel interrupt happens 0 RW 1 Write Function BTE Process Complete Interrupt Clear Bit 0 No operation 1 Clear BTE process complete interrupt Read Function BTE Interrupt Status 0 No BTE process complete interrupt happens 1 BTE process complete interrupt happens 0 RW 0 When MCU relative BTE operation is selected 1 and BTE Function is Enabled REG 50h Bi...

Page 31: ...θ 0o 500 600 Note 1 3 Response Time Ton 25 20 30 msec Note 1 4 Toff msec Chromaticlty White X Backlight is on 0 260 0 310 0 360 Note 1 5 Y 0 280 0 330 0 380 Red X 0 540 0 590 0 640 Y 0 300 0 350 0 400 Green X 0 298 0 348 0 398 Y 0 520 0 570 0 620 Blue X 0 095 0 145 0 195 Y 0 060 0 110 0 160 Luminance L 200 250 cd m2 Note 1 6 NTSC 50 Note 5 Luminance uniformity U 75 80 Note 1 7 Test Conditions 1 IF...

Page 32: ...nance When LCD is at White state Luminance When LCD is at Black state Contrast Ratio is measured in optimum common electrode voltage Note 4 Definition of Response time Test LCD using BM 7A 2 The output signals of photo detector are measured when the input signals are changed from black to white falling time and from white to black rising time respectively The response time is defined as the time i...

Page 33: ...dule User Manual LMT070DICFWD NJN URL www topwaydisplay com Document Name LMT070DICFWD NJN Manual Rev0 2 DOC Page 33 of 33 9 Precautions of using LCD Modules Please refer to LCD Module Design Handling Precaution pdf ...

Page 34: ......

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