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Description
•
Press and release the EVM RESET (S1) button and the on EVM current monitor will provide rail #1
load current.
5.9
Closed Loop Voltage Margining
The output voltage of VR1-4 can be varied from nominal in a closed loop fashion for voltage margining.
Four duty cycle modulated GPIO signals (FPWM1-4) are filtered to control the rail output voltage. Two
GPIO – feedback node filter configurations are provided; simple R-C-R or R-C-buffer-R. Jumpers provide
selection of either the simple or buffered method. Install J22, J25, J30, or J33 in either the RC (for R-C-R)
or MRGx (for R-C-buffer-R).
5.9.1
Basic Process for Voltage Margining a Rail
A basic procedure to voltage margin rail #1, starting with the EVM default configuration will follow. For
more information on voltage margining please refer to application note (
SLVA375
). Ensure that rail #1 is
selected in the upper right corner.
NOTE:
Ensure that S10 (STAT LED) is in the EN position.
25
SLVU347 – December 2009
Evaluation Module for UCD90120 and UCD90124
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