Software Control
14
SLAU374B – December 2011 – Revised May 2016
Copyright © 2011–2016, Texas Instruments Incorporated
TSW308x Evaluation Module
must be set to F
DAC
/interpolation/4.
•
CLK4: DAC3482 FIFO OSTR Clock. This clock type is AC coupled LVPECL.
–
The OSTR signal can be a slower periodic signal or a pulse depending on the application.
–
The OSTR clock rate must be at most F
DAC
/interpolation/16 for word-wide interface and
F
DAC
/interpolation/8 for byte-wide interface. See the DAC348x data sheet for more detail.
–
The FIFO OSTR clock must be disabled when the DAC348x is using the on-chip PLL for DACCLK
generation.
•
CLK6: Spare output clock at SMA J5.
•
CLK0: Spare output clock at SMA J2 and J3.
The following LMK04806 outputs are used by the TSW30H84EVM:
•
CLK4: DAC34H84 DAC sampling clock. This clock type is AC coupled LVPECL. If the DAC34H84 is
configured for internal PLL mode, this becomes the reference clock input for the PLL block.
•
CLK8: TSW1400/TSW3100 FPGA input clock (#1). This clock type is AC coupled LVDS. The clock
rate must be set to F
DAC
/interpolation/4.
•
CLK9: TSW1400 FPGA input clock (#2). This clock type is AC coupled LVDS. It is required to evaluate
the TSW30H84 and TSW30SH84 with the TSW1400. The clock rate must be set to
F
DAC
/interpolation/4.
•
CLK3: DAC34H84 FIFO OSTR Clock. This clock type is AC coupled LVPECL.
–
The OSTR signal can be a slower periodic signal or a pulse depending on the application.
–
The OSTR clock rate must be at most F
DAC
/interpolation/8. See the DAC34H84 data sheet for more
detail.
–
The FIFO OSTR clock must be disabled when the DAC348x is using the on-chip PLL for DACCLK
generation.
•
CLK6: Spare output clock at SMA J5.
•
CLK0: Spare output clock at SMA J2 and J3.
The clock settings are divided into subcontrol sections. These sections allow the user to set the divide
ratio, digital delay, type, analog delay, and ON/OFF control. Note that clock pairs share several settings.
The OSCout control section allows the user to configure the settings for the OSCIN input. The
TSW308xEVM uses this input as the reference input for Single Loop mode of operation (default
configuration). This mode uses PLL2 of the device. This reference can be provided by either the onboard
10-MHz oscillator (default) or from an external source brought in through SMA J11. For details, see
The PLL2 Settings control section allows the user to configure the settings for the internal PLL2. The
LMK04800 family contains four devices that cover internal VCO frequencies from 1840 MHz to 3072 MHz.
The VCO range of the LMK04806B is 2370 MHz to 2600 MHz . The TSW308xEVM default test case uses
settings to set the internal VCO to 2457.6 MHz and is locked to the 10-MHz input source on OSCIN.
The default Single Loop PLL settings provided by the example file provide a 1228.8 MHz of DAC sampling
clock, the divided-down FPGA clock(s) for the TSW1400/TSW3100 pattern generator FPGA input clock,
and the divided-down OSTR clock for DAC348x's OSTR input. The CLK6 (J5) is configured as a divided-
by-100 CMOS clock. This can be used as part of EVM functionality verification. For details, see
.
After the default settings are loaded, the output clocks are synchronized with the onboard 10-MHz
reference oscillator as indicated by
LMK LOCK
LED(D7) being illuminated.
Clicking on the Advance Settings tab at the bottom of the GUI opens a new window allowing the user to
set other internal registers for different modes of operation as shown in
