Layout Considerations
Table 2. Layout Guidelines and Descriptions (continued)
Item Signal Name
Description
Layout Guidelines
4
L1, L2, L3, L4
These are the connections to the mid
The pin carries the output current including inductor current
point of the power stage consisting of the
ripple. It charges the output capacitor through the high side
high- and low-side switch. The output
switch and inductor from the input supply and through the
inductor is connected here.
inductor and GND while the high side switch is open and low
side switch is closed. As the L pins toggle with the switching
frequency with high slew rates the trace should be routed
apart from sensitive signals such as the feedback connection
to the error amplifier (VDCDCx pins). It is acceptable to
increase the trace length in order to place the input capacitor
close to the device. Having the input capacitor close to
TPS65912x is more critical than having a short connection to
the output inductor as long as the L-trace is shielded to the
feedback trace.
5
VDCDC1,
Voltage feedback pins for DCDC1 to
The pins are high impedance (MR) and sensible to noise from
VDCDC2,
DCDC4
the switch node. The trace should not be routed in parallel to
DCDC3,VDCDC
the L-traces and should be tied to the V+-pad of the output
4
capacitor directly.
DCDC1 and DCDC4 allow remote sense, so the pin could
alternatively be routed to the input capacitor on the load side.
Coupling from fast switching signals must be avoided.
6
VDCDC1_GND,
GND-terminal for remote sense
The pins are the GND connections for remote sense and can
VDCDC4_GND
either be tied to the GND pad of the output capacitor or
simply to the GND plane. DO NOT CONNECT TO PGND
PINS DIRECTLY.
7
Vcc
Analog supply voltage pin
Must be bypassed with a separate input capacitor, does not
carry high currents.
8
AGND, DGND
Analog and digital GND connection
These GND pins need to be tied to the GND plane. The
current is quite small but they are the GND connection of the
analog and digital circuitry such as the control loop, so the
connection to a solid GND plane needs to be done without
using long traces- preferably by a via to the GND plane.
14
TPS65912xEVM-081
SLVU750A – July 2012 – Revised May 2013
Copyright © 2012–2013, Texas Instruments Incorporated