Layout Considerations
5
Layout Considerations
This section describes basic layout requirements for the TPS65912x.
5.1
General Layout
As for all switching power supplies, the layout is an important step in the design. Proper function of the
device demands careful attention to PCB layout. Follow board layout instructions carefully to attain the
specified performance. If the layout is not carefully done, the regulators may show poor line and/or load
regulation and stability issues as well as EMI problems. It is critical to provide a low impedance ground
path. Therefore, use wide and short traces for the main current paths. Place input capacitors as close as
possible to the IC pins as well as the inductor and output capacitor. Keep the common path to the GND
pins, which returns the small signal components, and the high current of the output capacitors as short as
possible to avoid ground noise. Connect the VDCDCx trace right to the output capacitor and routed away
from noisy components and traces (for example, the L1, L2, L3 and L4 traces).
5.2
Critical Signals for Layout
As outlined above, a number of signals require careful layout. Item numbers are assigned in
linking them to the examples in
.
Table 2. Layout Guidelines and Descriptions
Item Signal Name
Description
Layout Guidelines
1
PGND1,
Power-ground connection for DCDC1 to
Connect to the GND plane. Ideally, route this signal on the
PGND2,
DCDC4. This pin is internally tied to the
same layer that the device is placed. Use multiple vias to the
PGND3, PGND4 source of the low side transistor and
GND plane if it is on a different layer. As DCDC1 and DCDC4
carries the full output c inductor
are designed (operated) for larger output current, they are
current ripple.
more critical than DCDC2 and DCDC3. The GND-terminal of
the output capacitor requires a low-impedance connection to
the respective PGND pin, as in case where the internal low-
side switch is closed, the current flows in the path of output
inductor, output capacitor, PGND pin and L pin. Do not
connect VDCDCx_GND (the GND-SENSE connection for
DCDC1 and DCDC4) directly to the PGND pins. Tie
VDCDCx_GND to the GND-pad of the output capacitor or
directly to the GND plane. Tie AGND directly to the GND
plane. Connect PGND to the GND-plane independently of
other pins, not coupling noise on PGND into other pins.
2
VINDCDC1,
Input supply to the power stage for
Connect to the supply voltage trace. Place an input capacitor
VINDCDC2,VIN
DCDC1 to DCDC4. This pin is connected
on each of the VINDCDCx pins with low impedance to GND
DCDC3,
to the high-side power switch and carries
and low impedance to the VINDCDCx pin. The input capacitor
VINDCDC4
the full output c inductor current
will have to buffer the input current rising within less than
ripple. As there is only an input current
10ns to the average output current (in PWM mode) minus the
when the internal high-side switch is
inductor current ripple.
closed, the input current of a step-down
converter is discontinuous. This causes
current spikes on the input and requires
an input capacitor on each of the
VINDCDCx pins.
3
VINDCD-ANA
Analog supply input to the DCDC1-to-
This pin needs to be powered by the same voltage
DCDC4 converters. It supplies part of the
VINDCDC1 to VINDCDC4 are tied to. Its input should be
gate driver and other analog circuitry.
properly bypassed with a capacitor and routed to the supply
voltage separately from VINDCDCx in order to avoid noise
generated by the power stages being coupled into
VINDCDC_ANA. Its input current is only a few mA, so the
trace does not have to be very wide.
13
SLVU750A – July 2012 – Revised May 2013
TPS65912xEVM-081
Copyright © 2012–2013, Texas Instruments Incorporated
