5–2
5.5 V
OSCC
OSCR
(clock in)
VCC
OUT
C01
C02
C03
C04
C22
CA
CI
4 Reset Pulses
5 V
tsu2
C01 – C22
22 Security Bits
CA – C1
9 Configuration Bits
tw4
tw5
Figure 5–1. EEPROM Read Mode
5.2.2
Program Write Mode
The procedure to write the 31 security code and configuration bits to memory is described below (see
Section 3 for timing diagram):
1.
Set V
CC
to 5 V.
2.
Apply V
CC
+ 0.5 V to OSCC. This voltage on OSCC forces the device into the program mode,
and the terminals are in the following configuration:
•
OSCR: program/read external clock input
•
OSCC: input for high-voltage programming pulse used to permanently store data in memory
(see Figure 5–2).
•
OUT: serial output of 31 data bits currently stored in EEPROM
•
IN: serial input for 31 bits of data to be stored
3.
After applying V
CC
+ 0.5 V to OSCC (step 2), wait at least 50 ms to allow device to go into the
program mode.
4.
Apply exactly four clock reset pulses to OSCR (clock input). These reset pulses are applied
before clock input pulses for the 31 data bits that contain the security code and configuration bits.
The minimum duration of the clock reset pulses must be t
w6
= t
w7
= > 5
µ
s, which equates to a
clock frequency <100 kHz.
5.
Apply exactly 31 clock input pulses to OSCR. This serves to clock in the 31 data bits that should
be applied to IN (C01,C02,...C22, and CA,CB,...CI). Each of the 31 data bits must be present
on the falling edges of the clock input pulses applied to OSCR with the setup and hold times being
1
µ
s minimum.
6.
The data at OUT is previous data that was stored in EEPROM before this operation. If the device
has never been programmed, this data is a random factory test code. The newly programmed
data can be read only after it is loaded.
7.
Apply a logic low to OSCR for at least 10
µ
s.
Summary of Contents for TMS3637P
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