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Preface

SPRUEE7A – May 2006 – Revised September 2007

Read This First

This document describes the Pulse-Width Modulator (PWM) on the TMS320DM35x Digital Media
System-on-Chip (DMSoC).

Notational Conventions

This document uses the following conventions.

Hexadecimal numbers are shown with the suffix h. For example, the following number is 40
hexadecimal (decimal 64): 40h.

Registers in this document are shown in figures and described in tables.

Each register figure shows a rectangle divided into fields that represent the fields of the register.
Each field is labeled with its bit name, its beginning and ending bit numbers above, and its
read/write properties below. A legend explains the notation used for the properties.

Reserved bits in a register figure designate a bit that is used for future device expansion.

TMS320DM355 Digital Media System-on-Chip (DMSoC)

Related Documentation From Texas Instruments

The following documents describe the TMS320DM355 Digital Media System-on-Chip (DMSoC). Copies of
these documents are available on the internet at www.ti.com. Contact your TI representative for Extranet
access.

SPRS463— TMS320DM355 Digital Media System-on-Chip (DMSoC) Data Manual This document

describes the overall TMS320DM355 system, including device architecture and features, memory
map, pin descriptions, timing characteristics and requirements, device mechanicals, etc.

SPRZ264— TMS320DM355 DMSoC Silicon Errata Describes the known exceptions to the functional

specifications for the TMS320DM355 DMSoC.

SPRUFB3— TMS320DM355 ARM Subsystem Reference Guide This document describes the ARM

Subsystem in the TMS320DM355 Digital Media System-on-Chip (DMSoC). The ARM subsystem is
designed to give the ARM926EJ-S (ARM9) master control of the device. In general, the ARM is
responsible for configuration and control of the device; including the components of the ARM
Subsystem, the peripherals, and the external memories.

SPRUED1— TMS320DM35x DMSoC Asynchronous External Memory Interface (EMIF) Reference

Guide This document describes the asynchronous external memory interface (EMIF) in the
TMS320DM35x Digital Media System-on-Chip (DMSoC). The EMIF supports a glueless interface to
a variety of external devices.

SPRUED2— TMS320DM35x DMSoC Universal Serial Bus (USB) Controller Reference Guide This

document describes the universal serial bus (USB) controller in the TMS320DM35x Digital Media
System-on-Chip (DMSoC). The USB controller supports data throughput rates up to 480 Mbps. It
provides a mechanism for data transfer between USB devices and also supports host negotiation.

SPRUED3— TMS320DM35x DMSoC Audio Serial Port (ASP) Reference Guide This document

describes the operation of the audio serial port (ASP) audio interface in the TMS320DM35x Digital
Media System-on-Chip (DMSoC). The primary audio modes that are supported by the ASP are the
AC97 and IIS modes. In addition to the primary audio modes, the ASP supports general serial port
receive and transmit operation, but is not intended to be used as a high-speed interface.

SPRUEE7A – May 2006 – Revised September 2007

Preface

5

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Summary of Contents for TMS320DM35 Series

Page 1: ...TMS320DM35x Digital Media System on Chip DMSoC Pulse Width Modulator PWM Reference Guide Literature Number SPRUEE7A May 2006 Revised September 2007...

Page 2: ...2 SPRUEE7A May 2006 Revised September 2007 Submit Documentation Feedback...

Page 3: ...ulation Considerations 13 3 Registers 14 3 1 Pulse Width Modulator PWM Peripheral Identification Register PID 14 3 2 Pulse Width Modulator PWM Peripheral Control Register PCR 14 3 3 Pulse Width Modula...

Page 4: ...ulse Width Modulator PWM Period Register PER 17 11 Pulse Width Modulator PWM First Phase Duration Register PH1D 17 List of Tables 1 Pulse Width Modulator PWM Registers 14 2 Pulse Width Modulator PWM P...

Page 5: ...he functional specifications for the TMS320DM355 DMSoC SPRUFB3 TMS320DM355 ARM Subsystem Reference Guide This document describes the ARM Subsystem in the TMS320DM355 Digital Media System on Chip DMSoC...

Page 6: ...on between the MMC SD controller and MMC SD card s is performed by the MMC SD protocol SPRUEE4 TMS320DM35x DMSoC Enhanced Direct Memory Access EDMA Controller Reference Guide This document describes t...

Page 7: ...es the Real Time Out RTO controller in the TMS320DM35x Digital Media System on Chip DMSoC The following documents describe TMS320DM35x Digital Media System on Chip DMSoC that are not available by lite...

Page 8: ...where bit width of the period and first phase duration are both programmable The PWM has the following features 32 bit period counter 32 bit first phase duration counter 8 bit repeat counter for one...

Page 9: ...nfiguring the INACTOUT bit in the PWM configuration register CFG First phase active state During the first phase of an active PWM period the output signal is driven to the state defined in the P1OUT b...

Page 10: ...e level during the second phase When the prescribed number of RPT 1 periods of pulses expire the peripheral sends an interrupt to the system if the interrupt is enabled in CFG The PWM then becomes ina...

Page 11: ...evel during the second phase Once a period expires the next period starts When a period starts the PWM copies the period and first phase duration registers into a set of internal shadow registers and...

Page 12: ...phase duration to the PWM first phase duration register PH1D 3 If one shot mode will be used write the desired repeat value to the PWM repeat count register RPT 4 Configure the operating mode inactiv...

Page 13: ...er and Sleep Controller PSC The PSC acts as a master controller for power management for all of the peripherals on the device For detailed information on power management procedures using the PSC see...

Page 14: ...ion Register Section 3 7 The pulse width modulator PWM peripheral identification register PID contains identification data type class and revision for the peripheral PID is shown in Figure 5 and descr...

Page 15: ...se width modulator PWM configuration register CFG is shown in Figure 7 and described in Table 4 Figure 7 Pulse Width Modulator PWM Configuration Register CFG 31 18 17 16 Reserved OPST CURLEV R 0 R 0 R...

Page 16: ...d The pulse width modulator PWM start register START is shown in Figure 8 and described in Table 5 Figure 8 Pulse Width Modulator PWM Start Register START 31 16 Reserved R 0 15 1 0 Reserved START R 0...

Page 17: ...d register PER is shown in Figure 10 and described in Table 7 Figure 10 Pulse Width Modulator PWM Period Register PER 31 16 PER R W 0 15 0 PER R W 0 LEGEND R W Read Write n value after reset Table 7 P...

Page 18: ...irst Phase Duration Register PH1D Field Descriptions Bit Field Value Description 31 0 PH1D 0 FFFF FFFFh First phase duration is PH1D clock cycles 18 Pulse Width Modulator PWM Peripheral SPRUEE7A May 2...

Page 19: ...ce and is an unfair and deceptive business practice TI is not responsible or liable for any such statements TI products are not authorized for use in safety critical applications such as life support...

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