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2.3

Functional Operation

2.3.1

One-Shot Mode Operation

Write

PWM START

PWM START

Write

P1D

PER+1

PWM output

Interrupt

2.3.1.1

Event-Triggered One-Shot Mode Operation

Peripheral Architecture

The PWM module can operate in either one-shot or continuous mode. In both modes, the PWM peripheral
has a first-phase duration register (PH1D) and a period register (PER) to specify, respectively, the
first-phase duration and period of the waveform. The first-phase output level can be configured to be
either high or low in the P1OUT bit of the PWM configuration register (CFG) and the second phase output
is automatically the opposite polarity of the first-phase level. The inactive state before and after the PWM
operation can also be configured to be either a 0 or a 1 in the INACTOUT bit of CFG. For one-shot mode
operation, see

Section 2.3.1

for continuous mode operation, see

Section 2.3.2

.

In one-shot mode operation, the PWM produces a series of periods but does not run continuously. The
number of periods in the series is controlled by the repeat count contained in the PWM repeat count
register (RPT). To select one-shot mode, configure the MODE bit in the PWM configuration register (CFG)
to 1h.

For one-shot mode operation, the PWM should first be configured for mode, period, and first-phase
duration, along with other configuration options. The PWM uses the last programmed set of parameters
once it is started by writing a 1 to the START bit in the PWM start register (START).

Once started, the PWM asserts/deasserts the output as configured, driving to the first-phase output level
during the first phase and the opposite level during the second phase. When the prescribed number of
RPT + 1 periods of pulses expire, the peripheral sends an interrupt to the system (if the interrupt is
enabled in CFG). The PWM then becomes inactive until the START bit is written a 1 again.

The PWM is stopped during one-shot mode operation by changing the MODE bit to 0 (disable). When the
PWM is disabled, the output is immediately driven to the configured inactive state.

Figure 2

shows the one-shot mode operation. The waveform generation is started by writing to the START

bit (assuming event triggering is disabled). After RPT + 1 number of periods, the waveform stops and an
interrupt is generated. The polarity is configured as inactive low, first phase high-then-low.

Figure 2. PWM One-Shot Mode Operation (P1OUT = 1, INACTOUT = 0, EVTRIG = 0, PWM_RPT = 2)

In one-shot mode, the PWM senses a rising or falling transition on an event-trigger input signal to start the
operation. This event trigger input is synchronized to the PWM clock inside the module and is driven by
the video processing subsystem CCDC_VD output signal. This capability is provided to allow the PWM to
be used as a CCD timer.

The trigger event can be detected on the rising edge or the falling edge of CCDC_VD. After event
triggering is enabled as part of the configuration process, a write to the PWM START register (START)
starts the sensing circuitry in the PWM and after the first event, the PWM starts the period counting.

Figure 3

shows the event-triggered one-shot mode operation. Note that each subsequent event does not

restart period counting. It takes another write to the START bit to sense the event signal again. Also note,
that events received within the PWM period are ignored as well.

10

Pulse-Width Modulator (PWM) Peripheral

SPRUEE7A – May 2006 – Revised September 2007

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Summary of Contents for TMS320DM35 Series

Page 1: ...TMS320DM35x Digital Media System on Chip DMSoC Pulse Width Modulator PWM Reference Guide Literature Number SPRUEE7A May 2006 Revised September 2007...

Page 2: ...2 SPRUEE7A May 2006 Revised September 2007 Submit Documentation Feedback...

Page 3: ...ulation Considerations 13 3 Registers 14 3 1 Pulse Width Modulator PWM Peripheral Identification Register PID 14 3 2 Pulse Width Modulator PWM Peripheral Control Register PCR 14 3 3 Pulse Width Modula...

Page 4: ...ulse Width Modulator PWM Period Register PER 17 11 Pulse Width Modulator PWM First Phase Duration Register PH1D 17 List of Tables 1 Pulse Width Modulator PWM Registers 14 2 Pulse Width Modulator PWM P...

Page 5: ...he functional specifications for the TMS320DM355 DMSoC SPRUFB3 TMS320DM355 ARM Subsystem Reference Guide This document describes the ARM Subsystem in the TMS320DM355 Digital Media System on Chip DMSoC...

Page 6: ...on between the MMC SD controller and MMC SD card s is performed by the MMC SD protocol SPRUEE4 TMS320DM35x DMSoC Enhanced Direct Memory Access EDMA Controller Reference Guide This document describes t...

Page 7: ...es the Real Time Out RTO controller in the TMS320DM35x Digital Media System on Chip DMSoC The following documents describe TMS320DM35x Digital Media System on Chip DMSoC that are not available by lite...

Page 8: ...where bit width of the period and first phase duration are both programmable The PWM has the following features 32 bit period counter 32 bit first phase duration counter 8 bit repeat counter for one...

Page 9: ...nfiguring the INACTOUT bit in the PWM configuration register CFG First phase active state During the first phase of an active PWM period the output signal is driven to the state defined in the P1OUT b...

Page 10: ...e level during the second phase When the prescribed number of RPT 1 periods of pulses expire the peripheral sends an interrupt to the system if the interrupt is enabled in CFG The PWM then becomes ina...

Page 11: ...evel during the second phase Once a period expires the next period starts When a period starts the PWM copies the period and first phase duration registers into a set of internal shadow registers and...

Page 12: ...phase duration to the PWM first phase duration register PH1D 3 If one shot mode will be used write the desired repeat value to the PWM repeat count register RPT 4 Configure the operating mode inactiv...

Page 13: ...er and Sleep Controller PSC The PSC acts as a master controller for power management for all of the peripherals on the device For detailed information on power management procedures using the PSC see...

Page 14: ...ion Register Section 3 7 The pulse width modulator PWM peripheral identification register PID contains identification data type class and revision for the peripheral PID is shown in Figure 5 and descr...

Page 15: ...se width modulator PWM configuration register CFG is shown in Figure 7 and described in Table 4 Figure 7 Pulse Width Modulator PWM Configuration Register CFG 31 18 17 16 Reserved OPST CURLEV R 0 R 0 R...

Page 16: ...d The pulse width modulator PWM start register START is shown in Figure 8 and described in Table 5 Figure 8 Pulse Width Modulator PWM Start Register START 31 16 Reserved R 0 15 1 0 Reserved START R 0...

Page 17: ...d register PER is shown in Figure 10 and described in Table 7 Figure 10 Pulse Width Modulator PWM Period Register PER 31 16 PER R W 0 15 0 PER R W 0 LEGEND R W Read Write n value after reset Table 7 P...

Page 18: ...irst Phase Duration Register PH1D Field Descriptions Bit Field Value Description 31 0 PH1D 0 FFFF FFFFh First phase duration is PH1D clock cycles 18 Pulse Width Modulator PWM Peripheral SPRUEE7A May 2...

Page 19: ...ce and is an unfair and deceptive business practice TI is not responsible or liable for any such statements TI products are not authorized for use in safety critical applications such as life support...

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