Contents
1
1.1
Purpose of the Peripheral
.......................................................................................
1.2
Features
1.3
Industry Standard(s) Compliance Statement
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2
Peripheral Architecture
................................................................................................
2.1
Clock Control
2.2
Signal Descriptions
..............................................................................................
2.3
Functional Operation
...........................................................................................
2.4
Reset Considerations
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2.5
Initialization
2.6
Interrupt Support
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2.7
EDMA Event Support
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2.8
Power Management
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2.9
Emulation Considerations
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3
3.1
Pulse Width Modulator (PWM) Peripheral Identification Register (PID)
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3.2
Pulse Width Modulator (PWM) Peripheral Control Register (PCR)
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3.3
Pulse Width Modulator (PWM) Configuration Register (CFG)
............................................
3.4
Pulse Width Modulator (PWM) Start Register (START)
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3.5
Pulse Width Modulator (PWM) Repeat Count Register (RPT)
...........................................
3.6
Pulse Width Modulator (PWM) Period Register (PER)
....................................................
3.7
Pulse Width Modulator (PWM) First-Phase Duration Register (PH1D)
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SPRUEE7A – May 2006 – Revised September 2007
Table of Contents
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