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Pipeline Operation Overview

Pipeline

4-4

SPRU733

Figure 4

−

3(a) shows the decode phases in sequential order from left to right.

Figure 4

−

3(b) shows a fetch packet that contains two execute packets as they

are processed through the decode stage of the pipeline. The last six instruc-
tions of the fetch packet (FP) are parallel and form an execute packet (EP).
This EP is in the dispatch phase (DP) of the decode stage. The arrows indicate
each instruction’s assigned functional unit for execution during the same cycle.
The

NOP

instruction in the eighth slot of the FP is not dispatched to a functional

unit because there is no execution associated with it.

The first two slots of the fetch packet (shaded below) represent an execute
packet of two parallel instructions that were dispatched on the previous cycle.
This execute packet contains two

MPY

instructions that are now in decode

(DC) one cycle before execution. There are no instructions decoded for the .L,
.S, and .D functional units for the situation illustrated.

Figure 4

−

3. Decode Phases of the Pipeline

(b)

DC

DP

(a)

DP

32

32

32

32

32

32

32

32

NOP

†

ADDK

STW

STW

ADD

DC

MPYH

MPYH

.L1

.S1

.D1

.M1

.L2

.S2

.D2

.M2

Decode

ADD

Functional

units

†

NOP is not dispatched to a functional unit.

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Summary of Contents for TMS320C67X+ DSP

Page 1: ...TMS320C67x C67x DSP CPU and Instruction Set Reference Guide Literature Number SPRU733 May 2005 ...

Page 2: ...tute a license from TI to use such products or services or a warranty or endorsement thereof Use of such information may require a license from a third party under the patents or other intellectual property of the third party or a license from TI under the patents or other intellectual property of TI Reproduction of information in TI data books or data sheets is permissible only if reproduction is...

Page 3: ... following conventions Any reference to the C67x DSP or C67x CPU also applies unless other wise noted to the C67x DSP and C67x CPU respectively Hexadecimal numbers are shown with the suffix h For example the following number is 40 hexadecimal decimal 64 40h Related Documentation From Texas Instruments The following documents describe the C6000 devices and related support tools Copies of these docu...

Page 4: ...ribes the Code Composer Studio application programming interface API which allows you to pro gram custom plug ins for Code Composer TMS320C6x Peripheral Support Library Programmer s Reference literature number SPRU273 describes the contents of the TMS320C6000 peripheral support library of functions and macros It lists functions and macros both by header file and alphabetically provides a complete ...

Page 5: ...r File Cross Paths 2 6 2 5 Memory Load and Store Paths 2 6 2 6 Data Address Paths 2 7 2 7 Control Register File 2 7 2 7 1 Register Addresses for Accessing the Control Registers 2 8 2 7 2 Pipeline Timing of Control Register Accesses 2 9 2 7 3 Addressing Mode Register AMR 2 10 2 7 4 Control Status Register CSR 2 13 2 7 5 Interrupt Clear Register ICR 2 16 2 7 6 Interrupt Enable Register IER 2 17 2 7 ...

Page 6: ...n Register Writes 3 25 3 7 8 Constraints on Floating Point Instructions 3 26 3 8 Addressing Modes 3 30 3 8 1 Linear Addressing Mode 3 30 3 8 2 Circular Addressing Mode 3 31 3 8 3 Syntax for Load Store Address Generation 3 32 3 9 Instruction Compatibility 3 34 3 10 Instruction Descriptions 3 34 ABS Absolute Value With Saturation 3 38 ABSDP Absolute Value Double Precision Floating Point 3 40 ABSSP A...

Page 7: ...ing Point Value 3 117 INTDPU Convert Unsigned Integer to Double Precision Floating Point Value 3 119 INTSP Convert Signed Integer to Single Precision Floating Point Value 3 121 INTSPU Convert Unsigned Integer to Single Precision Floating Point Value 3 122 LDB U Load Byte From Memory With a 5 Bit Unsigned Constant Offset or Register Offset 3 123 LDB U Load Byte From Memory With a 15 Bit Unsigned Co...

Page 8: ...nto Upper Bits of Register 3 185 MVKL Move Signed Constant Into Register and Sign Extend Used with MVKH 3 187 NEG Negate 3 189 NOP No Operation 3 190 NORM Normalize Integer 3 192 NOT Bitwise NOT 3 194 OR Bitwise OR 3 195 RCPDP Double Precision Floating Point Reciprocal Approximation 3 197 RCPSP Single Precision Floating Point Reciprocal Approximation 3 199 RSQRDP Double Precision Floating Point Sq...

Page 9: ...t Using Halfword Addressing Mode 3 255 SUBAW Subtract Using Word Addressing Mode 3 256 SUBC Subtract Conditionally and Shift Used for Division 3 258 SUBDP Subtract Two Double Precision Floating Point Values 3 260 SUBSP Subtract Two Single Precision Floating Point Values 3 263 SUBU Subtract Two Unsigned Integers Without Saturation 3 266 SUB2 Subtract Two 16 Bit Integers on Upper and Lower Register ...

Page 10: ...ignals Used 5 2 5 1 2 Interrupt Service Table IST 5 6 5 1 3 Summary of Interrupt Control Registers 5 10 5 2 Globally Enabling and Disabling Interrupts 5 11 5 3 Individual Interrupt Control 5 13 5 3 1 Enabling and Disabling Interrupts 5 13 5 3 2 Status of Interrupts 5 14 5 3 3 Setting and Clearing Interrupts 5 14 5 3 4 Returning From Interrupt Servicing 5 15 5 4 Interrupt Detection and Processing 5...

Page 11: ...nal Unit D 2 D 2 Opcode Map Symbols and Meanings D 3 D 3 32 Bit Opcode Maps D 4 E M Unit Instructions and Opcode Maps E 1 Lists the instructions that execute in the M functional unit and illustrates the opcode maps for these instructions E 1 Instructions Executing in the M Functional Unit E 2 E 2 Opcode Map Symbols and Meanings E 3 E 3 32 Bit Opcode Maps E 4 F S Unit Instructions and Opcode Maps F...

Page 12: ... Multiplier Configuration Register FMCR 2 31 3 1 Single Precision Floating Point Fields 3 11 3 2 Double Precision Floating Point Fields 3 12 3 3 Basic Format of a Fetch Packet 3 16 3 4 Examples of the Detectability of Write Conflicts by the Assembler 3 25 4 1 Pipeline Stages 4 2 4 2 Fetch Phases of the Pipeline 4 3 4 3 Decode Phases of the Pipeline 4 4 4 4 Execute Phases of the Pipeline 4 5 4 5 Pi...

Page 13: ...RESET Interrupt Detection and Processing Pipeline Operation 5 19 C 1 1 or 2 Sources Instruction Format C 5 C 2 Extended D Unit 1 or 2 Sources Instruction Format C 5 C 3 Load Store Basic Operations C 5 C 4 Load Store Long Immediate Operations C 5 D 1 1 or 2 Sources Instruction Format D 4 D 2 1 or 2 Sources Nonconditional Instruction Format D 4 D 3 Unary Instruction Format D 4 E 1 Extended M Unit wi...

Page 14: ...ation Register FMCR Field Descriptions 2 31 3 1 Instruction Operation and Execution Notations 3 2 3 2 Instruction Syntax and Opcode Notations 3 7 3 3 IEEE Floating Point Notations 3 10 3 4 Special Single Precision Values 3 11 3 5 Hexadecimal and Decimal Representation for Selected Single Precision Values 3 12 3 6 Special Double Precision Values 3 13 3 7 Hexadecimal and Decimal Representation for S...

Page 15: ...straints 4 34 4 19 DP Compare S Unit Instruction Constraints 4 35 4 20 2 Cycle DP S Unit Instruction Constraints 4 36 4 21 ADDSP SUBSP S Unit Instruction Constraints 4 37 4 22 ADDDP SUBDP S Unit Instruction Constraints 4 38 4 23 Branch S Unit Instruction Constraints 4 39 4 24 16 16 Multiply M Unit Instruction Constraints 4 40 4 25 4 Cycle M Unit Instruction Constraints 4 41 4 26 MPYI M Unit Instru...

Page 16: ...ol Definitions C 3 C 3 Address Generator Options for Load Store C 4 D 1 Instructions Executing in the L Functional Unit D 2 D 2 L Unit Opcode Map Symbol Definitions D 3 E 1 Instructions Executing in the M Functional Unit E 2 E 2 M Unit Opcode Map Symbol Definitions E 3 F 1 Instructions Executing in the S Functional Unit F 2 F 2 S Unit Opcode Map Symbol Definitions F 3 G 1 Instructions Executing Wi...

Page 17: ...12 5 4 Code Sequence to Enable an Individual Interrupt INT9 5 13 5 5 Code Sequence to Disable an Individual Interrupt INT9 5 13 5 6 Code to Set an Individual Interrupt INT6 and Read the Flag Register 5 14 5 7 Code to Clear an Individual Interrupt INT6 and Read the Flag Register 5 14 5 8 Code to Return From NMI 5 15 5 9 Code to Return from a Maskable Interrupt 5 15 5 10 Code Without Single Assignme...

Page 18: ...iTI architecture a high performance advanced very long instruction word VLIW architecture making these DSPs excellent choices for multi channel and multifunction applications The TMS320C67x DSP is an enhancement of the C67x DSP with added functionality and an expanded instruction set Any reference to the C67x DSP or C67x CPU also applies unless otherwise noted to the C67x DSP and C67x CPU respecti...

Page 19: ...e system architects unlimited possibilities to differentiate their products High performance ease of use and affordable pricing make the C6000 generation the ideal solution for multichannel multifunction applications such as Pooled modems Wireless local loop base stations Remote access servers RAS Digital subscriber loop DSL systems Cable modems Multichannel telephony systems The C6000 generation ...

Page 20: ...s Numeric control Power line monitoring Robotics Security access Instrumentation Medical Military Digital filtering Function generation Pattern matching Phase locked loops Seismic processing Spectrum analysis Transient analysis Diagnostic equipment Fetal monitoring Hearing aids Patient monitoring Prosthetics Ultrasound equipment Image processing Missile guidance Navigation Radar processing Radio f...

Page 21: ...90 IEEE Standard Test Access Port and Boundary Scan Architecture Features of the C6000 devices include Advanced VLIW CPU with eight functional units including two multipliers and six arithmetic units Executes up to eight instructions per cycle for up to ten times the performance of typical DSPs Allows designers to develop highly effective RISC like code for fast development time Instruction packin...

Page 22: ...These additional features include Execute packets can span fetch packets Register file size is increased to 64 registers 32 in each datapath Floating point addition and subtraction capability in the S unit Mixed precision multiply instructions 32 KByte instruction cache that supports execution from both on chip RAM and ROM as well as from external memory through a VBUSP based external memory inter...

Page 23: ...key to extremely high performance taking these DSPs well beyond the performance capabilities of traditional superscalar designs VelociTI is a highly deterministic architecture having few restrictions on how or when instructions are fetched executed or stored It is this architectural flexibility that is key to the breakthrough efficiency levels of the TMS320C6000 Optimizing C compiler VelociTI s ad...

Page 24: ... you have Figure 1 1 TMS320C67x DSP Block Diagram ÁÁÁ ÁÁÁ 256 bit data 32 bit address Program cache program memory Á Á Á Á Á Á ÁÁ Á Á ÁÁ Á Á Á Á ÁÁ Á Á ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ 8 16 32 bit data 32 bit address Data cache data memory etc serial ports Timers Additional p...

Page 25: ...s the means to configure and control various processor operations To understand how instructions are fetched dispatched decoded and executed in the data path see Chapter 4 1 4 2 Internal Memory The C67x DSP has a 32 bit byte addressable address space Internal on chip memory is organized in separate data and program spaces When off chip memory is used these spaces are unified on most devices to a s...

Page 26: ...ilar to the HPI or in synchronous master slave mode This allows the device to interface to a variety of host bus protocols Synchronous FIFOs and asynchronous peripheral I O devices may interface to the expansion bus McBSP multichannel buffered serial port is based on the standard serial port interface found on the TMS320C2000 and TMS320C5000 devices In addition the port can buffer serial samples i...

Page 27: ...rol registers The two register files and the data cross paths are described Topic Page 2 1 Introduction 2 2 2 2 General Purpose Register Files 2 2 2 3 Functional Units 2 5 2 4 Register File Cross Paths 2 6 2 5 Memory Load and Store Paths 2 6 2 6 Data Address Paths 2 7 2 7 Control Register File 2 7 2 8 Control Register File Extensions 2 23 Chapter 2 ...

Page 28: ...d point and 64 bit floating point data Values larger than 32 bits such as 40 bit long and 64 bit float quantities are stored in register pairs In these the 32 LSBs of data are placed in an even numbered register and the remaining 8 or 32 MSBs in the next upper register that is always an odd numbered register Packed data types store either four 8 bit values or two 16 bit values in a single 32 bit r...

Page 29: ...ÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ 2X 1X L2 S2 M2 D2 B0 B15 A0 A15 Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á D1 M1 Á Á Á Á Á ÁÁ Á Á Á Á Á S1 Á ÁÁ Á Á Á Á L1 long src dst src2 src1 Á Á Á Á Á Á Á Á Á src1 src1 src1 src1 src1 src1 src1 8 8 long dst long dst dst dst dst dst dst dst dst src2 src2 src2 src2 src2 src2 src2 long src Control register file Á ...

Page 30: ...B13 B12 A15 A14 B15 B14 A17 A16 B17 B16 C67x DSP only A19 A18 B19 B18 A21 A20 B21 B20 A23 A22 B23 B22 A25 A24 B25 B24 A27 A26 B27 B26 A29 A28 B29 B28 A31 A30 B31 B30 Figure 2 2 Storage Scheme for 40 Bit Data in a Register Pair ÍÍÍÍÍÍÍÍÍ ÍÍÍÍÍÍÍÍÍ 31 0 31 0 Odd register Even register 39 32 31 0 Zero filled 40 bit data 39 32 31 0 40 bit data Á Á Á Á Á Á Odd register Even register Read from registers...

Page 31: ...arallel every cycle See Appendix B for a list of the instructions that execute on each functional unit Table 2 2 Functional Units and Operations Performed Functional Unit Fixed Point Operations Floating Point Operations L unit L1 L2 32 40 bit arithmetic and compare operations 32 bit logical operations Leftmost 1 or 0 counting for 32 bits Normalization count for 32 and 40 bits Arithmetic operations...

Page 32: ...r file Only two cross paths 1X and 2X exist in the C6000 architecture Thus the limit is one source read from each data path s opposite register file per cycle or a total of two cross path source reads per cycle In the C67x DSP only one functional unit per data path per execute packet can get an operand from the opposite register file 2 5 Memory Load and Store Paths The C67x DSP has two 32 bit path...

Page 33: ...ional unit fields for load and store instructions For example the following load instruction uses the D1 unit to generate the address but is using the LD2 path resource from DA2 to place the data in the B register file The use of the DA2 resource is indicated with the T2 designation LDW D1T2 A0 3 B1 2 7 Control Register File Table 2 3 lists the control registers contained in the control register f...

Page 34: ...errupt processing is complete the B IRP instruction in the interrupt service routine restores the pre interrupt value of the GIE Similarly saturating instructions like SADD set the SAT saturation bit in the control status register CSR Table 2 4 Register Addresses for Accessing the Control Registers Acronym Register Name Address Read Write AMR Addressing mode register 00000 R W CSR Control status r...

Page 35: ...bits MVC completes this ISR ICR write in a single E1 cycle but the modification of the IFR bits occurs one clock later For more information on the manipulation of ISR ICR and IFR see section 2 7 9 section 2 7 5 and section 2 7 7 Saturating instructions such as SADD set the saturation flag bit SAT in CSR indirectly As a result several of these instructions update the SAT bit one full clock cycle af...

Page 36: ...5 MODE A4 MODE R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 Legend R Readable by the MVC instruction W Writeable by the MVC instruction n value after reset Table 2 5 Addressing Mode Register AMR Field Descriptions Bit Field Value Description 31 26 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 25 21 BK1 0 1Fh Block size field 1 A 5 ...

Page 37: ...ressing using the BK0 field 2h Circular addressing using the BK1 field 3h Reserved 9 8 B4 MODE 0 3h Address mode selection for register file B4 0 Linear modification default at reset 1h Circular addressing using the BK0 field 2h Circular addressing using the BK1 field 3h Reserved 7 6 A7 MODE 0 3h Address mode selection for register file A7 0 Linear modification default at reset 1h Circular address...

Page 38: ... addressing using the BK0 field 2h Circular addressing using the BK1 field 3h Reserved Table 2 6 Block Size Calculations BKn Value Block Size BKn Value Block Size 00000 2 10000 131 072 00001 4 10001 262 144 00010 8 10010 524 288 00011 16 10011 1 048 576 00100 32 10100 2 097 152 00101 64 10101 4 194 304 00110 128 10110 8 388 608 00111 256 10111 16 777 216 01000 512 11000 33 554 432 01001 1 024 1100...

Page 39: ... time A logic 0 should be used when writing to the reserved bit bit 15 of the PWRD field Figure 2 4 Control Status Register CSR 31 24 23 16 CPU ID REVISION ID R 0 R x 15 10 9 8 7 5 4 2 1 0 PWRD SAT EN PCC DCC PGIE GIE R W 0 R WC 0 R x R W 0 R W 0 R W 0 R W 0 Legend R Readable by the MVC instruction W Writeable by the MVC instruction WC Bit is cleared on write n value after reset x value is indeter...

Page 40: ...Power down mode PD1 wake by an enabled interrupt Ah 10h Reserved 11h Power down mode PD1 wake by an enabled or nonenabled interrupt 12h 19h Reserved 1Ah Power down mode PD2 wake by a device reset 1Bh Reserved 1Ch Power down mode PD3 wake by a device reset 1D 3Fh Reserved 9 SAT Saturate bit Can be cleared only by the MVC instruction and can be set only by a functional unit The set by a functional u...

Page 41: ...C621x C671x DSP Two Level Internal Memory Reference Guide SPRU609 0 2 way cache enabled 1h Reserved 2h 2 way cache enabled 3h 7h Reserved 1 PGIE Previous GIE global interrupt enable Copy of GIE bit at point when interrupt is taken Physically the same bit as SGIE bit in the interrupt task state register ITSR Writeable by the MVC instruction 0 Disables saving GIE bit when an interrupt is taken 1 Ena...

Page 42: ...d by the MVC instruction in IFR until two cycles after the write to ICR Any write to ICR is ignored by a simultaneous write to the same bit in the interrupt set register ISR Figure 2 6 Interrupt Clear Register ICR 31 16 Reserved R 0 15 14 13 12 11 10 9 8 7 6 5 4 3 0 IC15 IC14 IC13 IC12 IC11 IC10 IC9 IC8 IC7 IC6 IC5 IC4 Reserved W 0 R 0 Legend R Read only W Writeable by the MVC instruction n value ...

Page 43: ... 15 4 IEn Interrupt enable An interrupt triggers interrupt processing only if the corresponding bit is set to 1 0 Interrupt is disabled 1 Interrupt is enabled 3 2 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 1 NMIE Nonmaskable interrupt enable An interrupt triggers interrupt processing only if the bit is set to 1 The NMIE bit is clea...

Page 44: ...IF5 IF4 Reserved NMIF 0 R 0 R 0 R 0 R 0 Legend R Readable by the MVC instruction n value after reset Table 2 10 Interrupt Flag Register IFR Field Descriptions Bit Field Value Description 31 16 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 15 4 IFn Interrupt flag Indicates the status of the corresponding maskable interrupt An interrupt...

Page 45: ... interrupt service routine returns to the program flow when interrupt servicing is complete The IRP is shown in Figure 2 9 The IRP contains the 32 bit address of the first execute packet in the program flow that was not executed because of a maskable interrupt Although you can write a value to IRP any subsequent interrupt processing may overwrite that value Figure 2 9 Interrupt Return Pointer Regi...

Page 46: ...R until two cycles after the write to ISR Any write to the interrupt clear register ICR is ignored by a simultaneous write to the same bit in ISR Figure 2 10 Interrupt Set Register ISR 31 16 Reserved R 0 15 14 13 12 11 10 9 8 7 6 5 4 3 0 IS15 IS14 IS13 IS12 IS11 IS10 IS9 IS8 IS7 IS6 IS5 IS4 Reserved W 0 R 0 Legend R Read only W Writeable by the MVC instruction n value after reset Table 2 11 Interr...

Page 47: ...inter Register ISTP Field Descriptions Bit Field Value Description 31 10 ISTB 0 3F FFFFh Interrupt service table base portion of the IST address This field is cleared to 0 on reset therefore upon startup the IST must reside at address 0 After reset you can relocate the IST by writing a new value to ISTB If relocated the first ISFP corresponding to RESET is never executed via interrupt processing b...

Page 48: ...ress of the first execute packet in the program flow that was not executed because of a nonmaskable interrupt Although you can write a value to NRP any subsequent interrupt processing may overwrite that value Figure 2 12 NMI Return Pointer Register NRP 31 0 NRP R W x Legend R Readable by the MVC instruction W Writeable by the MVC instruction x value is indeterminate after reset 2 7 12 E1 Phase Pro...

Page 49: ...ction FADCR Floating point adder configuration register 2 8 1 FAUCR Floating point auxiliary configuration register 2 8 2 FMCR Floating point multiplier configuration register 2 8 3 2 8 1 Floating Point Adder Configuration Register FADCR The floating point adder configuration register FADCR contains fields that specify underflow or overflow the rounding mode NaNs denormalized numbers and inexact r...

Page 50: ... FADCR Field Descriptions Bit Field Value Description 31 27 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 26 25 RMODE 0 3h Rounding mode select for L2 0 Round toward nearest representable floating point number 1h Round toward 0 truncate 2h Round toward infinity round up 3h Round toward negative infinity round down 24 UNDER Result unde...

Page 51: ...normalized number 18 DEN1 Denormalized number select for L2 src1 0 src1 is not a denormalized number 1 src1 is a denormalized number 17 NAN2 NaN select for L2 src2 0 src2 is not NaN 1 src2 is NaN 16 NAN1 NaN select for L2 src1 0 src1 is not NaN 1 src1 is NaN 15 11 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 10 9 RMODE 0 3h Rounding ...

Page 52: ...overflows 5 INFO Signed infinity for L1 0 Result is not signed infinity 1 Result is signed infinity 4 INVAL 0 A signed NaN SNaN is not a source 1 A signed NaN SNaN is a source NaN is a source in a floating point to integer conversion or when infinity is subtracted from infinity 3 DEN2 Denormalized number select for L1 src2 0 src2 is not a denormalized number 1 src2 is a denormalized number 2 DEN1 ...

Page 53: ... the warnings produced by the ADDSP ADDDP SUBSP SUBDP instructions on the S functional unit but not other instruc tions executing on the S functional unit Figure 2 15 Floating Point Auxiliary Configuration Register FAUCR 31 27 26 25 24 23 22 21 20 19 18 17 16 Reserved DIV0 UNORD UND INEX OVER INFO INVAL DEN2 DEN1 NAN2 NAN1 R 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 15 11...

Page 54: ...would have been computed had the exponent range and precision been unbounded never set with INVAL 22 OVER Result overflow status for S2 0 Result does not overflow 1 Result overflows 21 INFO Signed infinity for S2 0 Result is not signed infinity 1 Result is signed infinity 20 INVAL 0 A signed NaN SNaN is not a source 1 A signed NaN SNaN is a source NaN is a source in a floating point to integer con...

Page 55: ...this field has no effect 10 DIV0 Source to reciprocal operation for S1 0 0 is not source to reciprocal operation 1 0 is source to reciprocal operation 9 UNORD Source to a compare operation for S1 0 NaN is not a source to a compare operation 1 NaN is a source to a compare operation 8 UND Result underflow status for S1 0 Result does not underflow 1 Result underflows 7 INEX Inexact results status for...

Page 56: ... SNaN is not a source 1 A signed NaN SNaN is a source NaN is a source in a floating point to integer conversion or when infinity is subtracted from infinity 3 DEN2 Denormalized number select for S1 src2 0 src2 is not a denormalized number 1 src2 is a denormalized number 2 DEN1 Denormalized number select for S1 src1 0 src1 is not a denormalized number 1 src1 is a denormalized number 1 NAN2 NaN sele...

Page 57: ...EN2 DEN1 NAN2 NAN1 R 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 15 11 10 9 8 7 6 5 4 3 2 1 0 Reserved RMODE UNDER INEX OVER INFO INVAL DEN2 DEN1 NAN2 NAN1 R 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 Legend R Readable by the MVC instruction W Writeable by the MVC instruction n value after reset Table 2 16 Floating Point Multiplier Configuration Register FMCR F...

Page 58: ...overflows 21 INFO Signed infinity for M2 0 Result is not signed infinity 1 Result is signed infinity 20 INVAL 0 A signed NaN SNaN is not a source 1 A signed NaN SNaN is a source NaN is a source in a floating point to integer conversion or when infinity is subtracted from infinity 19 DEN2 Denormalized number select for M2 src2 0 src2 is not a denormalized number 1 src2 is a denormalized number 18 D...

Page 59: ...wn 8 UNDER Result underflow status for M1 0 Result does not underflow 1 Result underflows 7 INEX Inexact results status for M1 0 1 Result differs from what would have been computed had the exponent range and precision been unbounded never set with INVAL 6 OVER Result overflow status for M1 0 Result does not overflow 1 Result overflows 5 INFO Signed infinity for M1 0 Result is not signed infinity 1...

Page 60: ...guration Register FMCR Field Descriptions Continued Bit Description Value Field 2 DEN1 Denormalized number select for M1 src1 0 src1 is not a denormalized number 1 src1 is a denormalized number 1 NAN2 NaN select for M1 src2 0 src2 is not NaN 1 src2 is NaN 0 NAN1 NaN select for M1 src1 0 src1 is not NaN 1 src1 is NaN ...

Page 61: ...to the C67x DSP These specific instructions are for 32 bit integer multiply double word load and floating point operations including addition subtraction and multiplication Topic Page 3 1 Instruction Operation and Execution Notations 3 2 3 2 Instruction Syntax and Opcode Notations 3 7 3 3 Overview of IEEE Standard Single and Double Precision Formats 3 9 3 4 Delay Slots 3 14 3 5 Parallel Operations...

Page 62: ...t byte position in 32 bit register bits 8 15 byte2 8 bit value in the next to most significant byte position in 32 bit register bits 16 23 byte3 8 bit value in the most significant byte position in 32 bit register bits 24 31 bv2 Bit vector of two flags for s2 or u2 data type bv4 Bit vector of four flags for s4 or u4 data type by z Selection of bits y through z of bit string b cond Check for either...

Page 63: ...cant bits for example msb16 nop No operation norm x Leftmost nonredundant sign bit of x not Bitwise logical complement op Opfields or Bitwise OR R Any general purpose register rcp x Reciprocal approximation of x ROTL Rotate left sat Saturate sbyte0 Signed 8 bit value in the least significant byte position in 32 bit register bits 0 7 sbyte1 Signed 8 bit value in the next to least significant byte p...

Page 64: ...ter s4 Four packed signed 8 bit integers in a single 32 bit register s Perform 2s complement subtraction and saturate the result to the result size if an overflow occurs s Perform 2s complement addition and saturate the result to the result size if an overflow occurs ubyte0 Unsigned 8 bit value in the least significant byte position in 32 bit register bits 0 7 ubyte1 Unsigned 8 bit value in the ne...

Page 65: ...clusive OR xsint Signed 32 bit integer value that can optionally use cross path xslsb16 Signed 16 LSB of register that can optionally use cross path xsmsb16 Signed 16 MSB of register that can optionally use cross path xsp Single precision floating point register value that can optionally use cross path xs2 Two packed signed 16 bit integers in a single 32 bit register that can optionally use cross ...

Page 66: ...U733 Table 3 1 Instruction Operation and Execution Notations Continued Symbol Meaning Greater than Greater than or equal to Less than Less than or equal to Shift left Shift right s Shift right with sign extension z Shift right with a zero fill Logical inverse Logical AND ...

Page 67: ... csta constant a cstb constant b cstn n bit constant field dst destination dstms dw doubleword 0 word 1 doubleword iin bit n of the constant ii ld st load or store 0 store 1 load mode addressing mode see section 3 8 offsetR register offset op opfield field within opcode that specifies a unique instruction opn bit n of the opfield p parallel execution 0 next instruction is not executed in parallel ...

Page 68: ... sn sign src source src1 source 1 src2 source 2 srcms stgn bit n of the constant stg t side of source destination src dst register 0 side A 1 side B ucstn n bit unsigned constant field ucstn bit n of the unsigned constant field unit unit decode x cross path for src2 0 do not use cross path 1 use cross path y D1 or D2 unit 0 D1 unit 1 D2 unit z test for equality with zero or nonzero ...

Page 69: ...ructions that produce a double precision result write the low 32 bit word one cycle before writing the high 32 bit word If an instruction that writes a DP result is followed by an instruction that uses the result as its DP source and it reads the upper and low er words on separate cycles then the second instruction can be scheduled on the same cycle that the high 32 bit word of the result is writt...

Page 70: ...eld x Can have value of 0 or 1 don t care NaN Not a Number SNaN or QNaN SNaN Signal NaN QNaN Quiet NaN NaN_out QNaN with all bits in the f field 1 Inf Infinity LFPN Largest floating point number SFPN Smallest floating point number LDFPN Largest denormalized floating point number SDFPN Smallest denormalized floating point number signed Inf infinity or infinity signed NaN_out NaN_out with s 0 or 1 ...

Page 71: ... 0 e 255 Denormalized Subnormal 1s 2 126 0 f e 0 f nonzero Table 3 4 shows the s e and f values for special single precision floating point numbers Table 3 4 Special Single Precision Values ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ Symbol ÁÁÁÁÁ ÁÁÁÁÁ Sign s ÁÁÁÁÁ ÁÁÁÁÁ Exponent e ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ Fraction f ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 0 ÁÁÁÁÁ ÁÁÁÁÁ 0 ÁÁÁÁÁ ÁÁÁÁÁ 0 ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ 0 ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ 0 ÁÁÁÁÁ ÁÁÁÁÁ 1 ÁÁÁÁÁ ÁÁÁÁÁ 0 ...

Page 72: ...000 0 0 0 8000 0000 0 0 1 3F80 0000 1 0 2 4000 0000 2 0 LFPN 7F7F FFFF 3 40282347e 38 SFPN 0080 0000 1 17549435e 38 LDFPN 007F FFFF 1 17549421e 38 SDFPN 0000 0001 1 40129846e 45 Figure 3 2 Double Precision Floating Point Fields 31 e 20 19 0 31 0 30 s Odd register Even register f f Legend s sign bit 0 positive 1 negative e 11 bit exponent 0 e 2047 f 52 bit fraction 0 f 1 2 1 1 2 2 1 2 52 or 0 f 252...

Page 73: ...nzero QNaN x 2047 1xx x SNaN x 2047 0xx x and nonzero Table 3 7 shows hexadecimal and decimal values for some double precision floating point numbers Table 3 7 Hexadecimal and Decimal Representation for Selected Double Precision Values Symbol Hex Value Decimal Value NaN_out 7FFF FFFF FFFF FFFF QNaN 0 0000 0000 0000 0000 0 0 0 8000 0000 0000 0000 0 0 1 3FF0 0000 0000 0000 1 0 2 4000 0000 0000 0000 ...

Page 74: ... floating point addition subtraction multiplication compare and the 32 bit integer multiply instructions also have a functional unit latency that is greater than 1 The functional unit latency is equivalent to the number of cycles that the instruction uses the functional unit read ports For example the ADDDP instruction has a functional unit latency of 2 Operands are read on cycle i and cycle i 1 T...

Page 75: ...i 2 cycle DP 1 1 i i i 1 DP compare 1 2 i i 1 1 1 4 cycle 3 1 i i 3 INTDP 4 1 i i 3 i 4 Load 4 1 i i i 4 MPYSP2DP 4 2 i i 3 i 4 ADDDP SUBDP 6 2 i i 1 i 5 i 6 MPYSPDP 6 3 i i 1 i 5 i 6 MPYI 8 4 i i 1 1 2 i 3 i 8 MPYID 9 4 i i 1 1 2 i 3 i 8 i 9 MPYDP 9 4 i i 1 1 2 i 3 i 8 i 9 Cycle i is in the E1 pipeline phase A write on cycle i 4 uses a separate write port from other D unit instructions ...

Page 76: ...igher address If the p bit of instruction i is 1 then instruction i 1 is to be executed in parallel with in the the same cycle as instruction i If the p bit of instruction i is 0 then instruction i 1 is executed in the cycle after instruction i All instructions executing in parallel constitute an execute packet An execute packet can contain up to eight instructions Each instruction in an execute p...

Page 77: ...ecution sequence Cycle Execute Packet Instructions 1 A 2 B 3 C 4 D 5 E 6 F 7 G 8 H The eight instructions are executed sequentially Example 3 2 Fully Parallel p Bit Pattern in a Fetch Packet This p bit pattern 1 1 1 1 1 1 1 0 Instruction A Instruction B Instruction C Instruction D Instruction E Instruction F Instruction G Instruction H 31 0 31 0 31 0 31 0 31 0 31 0 31 0 31 0 results in this execut...

Page 78: ...ify that an instruction is to execute in parallel with the previous instruction The code for the fetch packet in Example 3 3 would be represented as this instruction A instruction B instruction C instruction D instruction E instruction F instruction G instruction H 3 5 2 Branching Into the Middle of an Execute Packet If a branch into the middle of an execute packet occurs all instructions at lower...

Page 79: ...ied C diti l creg z Conditional Register Bit 31 30 29 28 Unconditional 0 0 0 0 Reserved 0 0 0 1 B0 0 0 1 z B1 0 1 0 z B2 0 1 1 z A1 1 0 0 z A2 1 0 1 z Reserved 1 1 x x This value is reserved for software breakpoints that are used for emulation purposes x can be any value Conditional instructions are represented in code by using square brackets surrounding the condition register name The following ...

Page 80: ...structions Using the Same Functional Unit Two instructions using the same functional unit cannot be issued in the same execute packet The following execute packet is invalid ADD S1 A0 A1 A2 S1 is used for SHR S1 A3 15 A4 both instructions The following execute packet is valid ADD L1 A0 A1 A2 Two different functional SHR S1 A3 15 A4 units are used 3 7 2 Constraints on the Same Functional Unit Writi...

Page 81: ... The following execute packet is invalid because the 1X cross path is being used for two different B register operands MV S1X B0 A0 Invalid Instructions are using the 1X cross path MV L1X B1 A1 with different B registers The following execute packet is valid because all uses of the 1X cross path are for the same B register operand and all uses of the 2X cross path are for the same A register opera...

Page 82: ...te packet is invalid LDW D1 A0 A1 D2 unit must use the address LDW D2 A2 B2 register from the B register file The following execute packet is valid LDW D1 A0 A1 Address registers from correct LDW D2 B0 B2 register files Two loads and or stores loading to and or storing from the same register file cannot be issued in the same execute packet The following execute packet is invalid LDW D1 A4 A5 Loadi...

Page 83: ... in the same execute packet as a store The following execute packet is invalid ADD L1 A5 A4 A1 A3 A2 Long read operation and a STW D1 A8 A9 store The following execute packet is valid ADD L1 A4 A1 A3 A2 No long read with STW D1 A8 A9 the store On the C67x DSP doubleword load instructions conflict with long results from the S units All stores conflict with a long source on the S unit The following ...

Page 84: ...le Conditional registers are not included in this count The following execute packets are invalid MPY M1 A1 A1 A4 five reads of register A1 ADD L1 A1 A1 A5 SUB D1 A1 A2 A3 MPY M1 A1 A1 A4 five reads of register A1 ADD L1 A1 A1 A5 SUB D2x A1 B2 B3 The following execute packet is valid MPY M1 A1 A1 A4 only four reads of A1 A1 ADD L1 A0 A1 A5 SUB D1 A1 A2 A3 ...

Page 85: ...L1 write to the same register This conflict is easily detectable MPY in packet L2 and ADD in packet L3 might both write to B2 simultaneously however if a branch instruction causes the execute packet after L2 to be something other than L3 a conflict would not occur Thus the potential conflict in L2 and L3 might not be detected by the assembler The instructions in L4 do not constitute a write confli...

Page 86: ... 2 and i 3 MPYID No other instruction can use the functional unit on cycles i i 1 i 2 and i 3 MPYDP No other instruction can use the functional unit on cycles i i 1 i 2 and i 3 MPYSPDP No other instruction can use the functional unit on cycles i and i 1 MPYSP2DP No other instruction can use the functional unit on cycles i and i 1 If a cross path is used to read a source in an instruction with a mu...

Page 87: ...ycle i 1 4 cycle A single cycle instruction cannot be scheduled on that functional unit on cycle i 3 due to a write hazard on cycle i 3 A multiply 16 16 bit instruction cannot be scheduled on that functional unit on cycle i 2 due to a write hazard on cycle i 3 ADDDP SUBDP A single cycle instruction cannot be scheduled on that functional unit on cycle i 5 or i 6 due to a write hazard on cycle i 5 o...

Page 88: ...YDP instruction cannot be scheduled on that func tional unit on cycle i 4 i 5 or i 6 A MPYSPDP instruction cannot be scheduled on that functional unit on cycle i 4 i 5 or i 6 A MPYSP2DP instruction cannot be scheduled on that functional unit on cycle i 4 i 5 or i 6 A multiply 16 16 bit instruction cannot be scheduled on that functional unit on cycle i 7 or i 8 due to a write hazard on cycle i 8 or...

Page 89: ...e i 3 or i 4 respectively All of the above cases deal with double precision floating point instructions or the MPYI or MPYID instructions except for the 4 cycle case A 4 cycle instruc tion consists of both single and double precision floating point instructions Therefore the 4 cycle case is important for the following single precision float ing point instructions ADDSP SUBSP SPINT SPTRUNC INTSP MP...

Page 90: ...ng Mode 3 8 1 1 LD and ST Instructions For load and store instructions linear mode simply shifts the offsetR cst operand to the left by 3 2 1 or 0 for doubleword word halfword or byte access respectively and then performs an add or a subtract to baseR depending on the operation specified For the preincrement predecrement positive offset and negative offset address generation options the result of ...

Page 91: ...ize of the offsetR cst The circular buffer size in AMR is not scaled for example a block size of 8 is 8 bytes not 8 times the data size byte halfword word So to perform circular addressing on an array of 8 words a size of 32 should be specified or N 4 Example 3 4 shows an LDW performed with register A4 in circular mode and BK0 4 so the buffer size is 32 bytes 16 halfwords or 8 words The value in A...

Page 92: ...so the buffer size is 32 bytes 16 halfwords or 8 words The value in AMR for this example is 0004 0001h Example 3 5 ADDAH Instruction in Circular Mode ADDAH D1 A4 A1 A4 Before ADDAH 1 cycle after ADDAH A4 0000 0100h A4 0000 0106h A1 0000 0013h A1 0000 0013h Note 13h halfwords is 26h bytes 26h bytes is 6 bytes beyond the 32 byte 20h boundary 100h 11Fh thus it is wrapped around to 126h 20h 106h 3 8 3...

Page 93: ...ffset B14 B15 ucst15 not supported not supported Base index R offsetR R offsetR R offsetR R offsetR R offsetR R offsetR Table 3 11 Address Generator Options for Load Store Mode Field Syntax Modification Performed 0 0 0 0 R ucst5 Negative offset 0 0 0 1 R ucst5 Positive offset 0 1 0 0 R offsetR Negative offset 0 1 0 1 R offsetR Positive offset 1 0 0 0 R ucst5 Predecrement 1 0 0 1 R ucst5 Preincreme...

Page 94: ...detailed information on the instruction set Each instruction may present the following information Assembler syntax Functional units Compatibility Operands Opcode Description Execution Pipeline Instruction type Delay slots Functional Unit Latency Examples The ADD instruction is used as an example to familiarize you with the way each instruction is described The example describes the kind of inform...

Page 95: ...is is documented for the ADD instruction This instruction has three opcode map fields src1 src2 and dst In the seventh group the operands have the types cst5 long and long for src1 src2 and dst respectively The ordering of these fields implies cst5 long long where represents the operation being performed by the ADD This operation can be done on L1 or L2 both are specified in the unit column The s ...

Page 96: ...operand type Unit Opfield src1 src2 dst sint xsint sint L1 L2 000 0011 src1 src2 dst sint xsint slong L1 L2 010 0011 src1 src2 dst xsint slong slong L1 L2 010 0001 src1 src2 dst scst5 xsint sint L1 L2 000 0010 src1 src2 dst scst5 slong slong L1 L2 010 0000 src1 src2 dst sint xsint sint S1 S2 00 0111 src1 src2 dst scst5 xsint sint S1 S2 00 0110 src2 src1 dst sint sint sint D1 D2 01 0000 src2 src1 d...

Page 97: ...e nop The execution describes the processing that takes place when the instruction is executed The symbols are defined in Table 3 1 page 3 2 Pipeline This section contains a table that shows the sources read from the destina tions written to and the functional unit used during each execution cycle of the instruction Instruction Type This section gives the type of instruction See section 4 2 page 4...

Page 98: ...int sint L1 L2 001 1010 src2 dst slong slong L1 L2 011 1000 Description The absolute value of src2 is placed in dst Execution if cond abs src2 dst else nop The absolute value of src2 when src2 is an sint is determined as follows 1 If src2 0 then src2 dst 2 If src2 0 and src2 231 then src2 dst 3 If src2 231 then 231 1 dst The absolute value of src2 when src2 is an slong is determined as follows 1 I...

Page 99: ...DP ABSSP Example 1 ABS L1 A1 A5 Before instruction 1 cycle after instruction A1 8000 4E3Dh 2147463619 A1 8000 4E3Dh 2147463619 A5 xxxx xxxxh A5 7FFF B1C3h 2147463619 Example 2 ABS L1 A1 A5 Before instruction 1 cycle after instruction A1 3FF6 0010h 1073086480 A1 3FF6 0010h 1073086480 A5 xxxx xxxxh A5 3FF6 0010h 1073086480 ...

Page 100: ...alue of src2 is placed in dst The 64 bit double precision operand is read in one cycle by using the src2 port for the 32 MSBs and the src1 port for the 32 LSBs Execution if cond abs src2 dst else nop The absolute value of src2 is determined as follows 1 If src2 0 then src2 dst 2 If src2 0 then src2 dst Notes 1 If scr2 is SNaN NaN_out is placed in dst and the INVAL and NAN2 bits are set 2 If src2 i...

Page 101: ...e number of delay slots can be reduced by one because these instructions read the lower word of the DP source one cycle before the upper word of the DP source Instruction Type 2 cycle DP Delay Slots 1 Functional Unit Latency 1 See Also ABS ABSSP Example ABSDP S1 A1 A0 A3 A2 Before instruction 2 cycles after instruction A1 A0 C004 0000h 0000 0000h 2 5 A1 A0 c004 0000h 0000 0000h 2 5 A3 A2 xxxx xxxx...

Page 102: ...operand type Unit src2 dst xsp sp S1 S2 Description The absolute value in src2 is placed in dst Execution if cond abs src2 dst else nop The absolute value of src2 is determined as follows 1 If src2 0 then src2 dst 2 If src2 0 then src2 dst Notes 1 If scr2 is SNaN NaN_out is placed in dst and the INVAL and NAN2 bits are set 2 If src2 is QNaN NaN_out is placed in dst and the NAN2 bit is set 3 If src...

Page 103: ...peline Stage E1 Read src2 Written dst Unit in use S Instruction Type Single cycle Delay Slots 0 Functional Unit Latency 1 See Also ABS ABSDP Example ABSSP S1X B1 A5 Before instruction 1 cycle after instruction B1 c020 0000h 2 5 B1 c020 0000h 2 5 A5 xxxx xxxxh A5 4020 0000h 2 5 Pipeline ...

Page 104: ... C64x C67x and C67x CPU Opcode L unit 31 29 28 27 23 22 18 17 13 12 11 5 4 3 2 1 0 creg z dst src2 src1 x op 1 1 0 s p 3 1 5 5 5 1 7 1 1 Opcode map field used For operand type Unit Opfield src1 src2 dst sint xsint sint L1 L2 000 0011 src1 src2 dst sint xsint slong L1 L2 010 0011 src1 src2 dst xsint slong slong L1 L2 010 0001 src1 src2 dst scst5 xsint sint L1 L2 000 0010 src1 src2 dst scst5 slong s...

Page 105: ...st src2 src1 x op 1 0 0 0 s p 3 1 5 5 5 1 6 1 1 Opcode map field used For operand type Unit Opfield src1 src2 dst sint xsint sint S1 S2 00 0111 src1 src2 dst scst5 xsint sint S1 S2 00 0110 Description for L1 L2 and S1 S2 Opcodes src2 is added to src1 The result is placed in dst Execution for L1 L2 and S1 S2 Opcodes if cond src1 src2 dst else nop ...

Page 106: ... operand type Unit Opfield src2 src1 dst sint sint sint D1 D2 01 0000 src2 src1 dst sint ucst5 sint D1 D2 01 0010 Description for D1 D2 Opcodes src1 is added to src2 The result is placed in dst Execution for D1 D2 Opcodes if cond src2 src1 dst else nop Pipeline Stage E1 Read src1 src2 Written dst Unit in use L S or D Instruction Type Single cycle Delay Slots 0 See Also ADDDP ADDK ADDSP ADDU ADD2 S...

Page 107: ...ction 1 cycle after instruction A1 0000 325Ah 12890 A1 0000 325Ah A3 A2 0000 00FFh FFFF FF12h 228 A3 A2 0000 00FFh FFFF FF12h A5 A4 0000 0000h 0000 0000h 0 A5 A4 0000 0000h 0000 316Ch 12652 Signed 40 bit long integer Example 3 ADD L1 13 A1 A6 Before instruction 1 cycle after instruction A1 0000 325Ah 12890 A1 0000 325Ah A6 xxxx xxxxh A6 0000 324Dh 12877 Example 4 ADD D1 A1 26 A6 Before instruction...

Page 108: ...t sint sint sint D1 D2 11 0000 src2 src1 dst sint ucst5 sint D1 D2 11 0010 Description src1 is added to src2 using the byte addressing mode specified for src2 The addition defaults to linear mode However if src2 is one of A4 A7 or B4 B7 the mode can be changed to circular mode by writing the appropriate value to the AMR see section 2 7 3 page 2 10 The result is placed in dst Execution if cond src2...

Page 109: ...00 000Bh A2 0000 000Bh A4 0000 0100h A4 0000 0103h AMR 0002 0001h AMR 0002 0001h BK0 2 size 8 A4 in circular addressing mode using BK0 Example 2 ADDAB D1X B14 42h A4 Before instruction 1 cycle after instruction B14 0020 1000h A4 0020 1042h Example 3 ADDAB D2 B14 7FFFh B4 Before instruction 1 cycle after instruction B14 0010 0000h B4 0010 7FFFh ...

Page 110: ...t sint D1 D2 11 1100 src2 src1 dst sint ucst5 sint D1 D2 11 1101 Description src1 is added to src2 using the doubleword addressing mode specified for src2 The addition defaults to linear mode However if src2 is one of A4 A7 or B4 B7 the mode can be changed to circular mode by writing the appropri ate value to the AMR see section 2 7 3 page 2 10 src1 is left shifted by 3 due to doubleword data size...

Page 111: ...Instruction Type Single cycle Delay Slots 0 Functional Unit Latency 1 See Also ADD ADDAB ADDAH ADDAW Example ADDAD D1 A1 A2 A3 Before instruction 1 cycle after instruction A1 0000 1234h 4660 A1 0000 1234h 4660 A2 0000 0002h 2 A2 0000 0002h 2 A3 xxxx xxxxh A3 0000 1244h 4676 ...

Page 112: ... sint D1 D2 11 0100 src2 src1 dst sint ucst5 sint D1 D2 11 0110 Description src1 is added to src2 using the halfword addressing mode specified for src2 The addition defaults to linear mode However if src2 is one of A4 A7 or B4 B7 the mode can be changed to circular mode by writing the appropriate value to the AMR see section 2 7 3 page 2 10 src1 is left shifted by 1 The result is placed in dst Exe...

Page 113: ...0000 000Bh A2 0000 000Bh A4 0000 0100h A4 0000 0106h AMR 0002 0001h AMR 0002 0001h BK0 2 size 8 A4 in circular addressing mode using BK0 Example 2 ADDAH D1X B14 42h A4 Before instruction 1 cycle after instruction B14 0020 1000h A4 0020 1084h Example 3 ADDAH D2 B14 7FFFh B4 Before instruction 1 cycle after instruction B14 0010 0000h B4 0010 FFFEh ...

Page 114: ...int D1 D2 11 1000 src2 src1 dst sint ucst5 sint D1 D2 11 1010 Description src1 is added to src2 using the word addressing mode specified for src2 The addition defaults to linear mode However if src2 is one of A4 A7 or B4 B7 the mode can be changed to circular mode by writing the appropriate value to the AMR see section 2 7 3 page 2 10 src1 is left shifted by 2 The result is placed in dst Execution...

Page 115: ...truction A4 0002 0000h A4 0002 0000h AMR 0002 0001h AMR 0002 0001h BK0 2 size 8 A4 in circular addressing mode using BK0 Example 2 ADDAW D1X B14 42h A4 Before instruction 1 cycle after instruction B14 0020 1000h A4 0020 1108h Example 3 ADDAW D2 B14 7FFFh B4 Before instruction 1 cycle after instruction B14 0010 0000h B4 0011 FFFCh ...

Page 116: ... src1 src2 dst C67x CPU only unit S1 or S2 Compatibility C67x and C67x CPU Opcode 31 29 28 27 23 22 18 17 13 12 11 5 4 3 2 1 0 creg z dst src2 src1 x op 1 1 0 s p 3 1 5 5 5 1 7 1 1 Opcode map field used For operand type Unit Opfield src1 src2 dst dp xdp dp L1 L2 001 1000 src1 src2 dst dp xdp dp S1 S2 111 0010 Description src2 is added to src1 The result is placed in dst Execution if cond src1 src2...

Page 117: ...lts are rounded as follows LFPN is the largest floating point number Overflow Output Rounding Mode Result Sign Nearest Even Zero Infinity Infinity infinity LFPN infinity LFPN infinity LFPN LFPN infinity 7 If underflow occurs the INEX and UNDER bits are set and the results are rounded as follows SPFN is the smallest floating point number Underflow Output Rounding Mode Result Sign Nearest Even Zero ...

Page 118: ...result is written out one cycle earlier than the high half If dst is used as the source for the ADDDP CMPEQDP CMPLTDP CMPGTDP MPYDP MPYSPDP MPYSP2DP or SUBDP instruction the number of delay slots can be reduced by one because these instructions read the lower word of the DP source one cycle before the upper word of the DP source Instruction Type ADDDP SUBDP Delay Slots 6 Functional Unit Latency 2 ...

Page 119: ...0 0 s p 3 1 5 16 1 1 Opcode map field used For operand type Unit cst16 dst scst16 uint S1 S2 Description A 16 bit signed constant cst16 is added to the dst register specified The result is placed in dst Execution if cond cst dst dst else nop Pipeline Stage E1 Read cst16 Written dst Unit in use S Instruction Type Single cycle Delay Slots 0 Example ADDK S1 15401 A1 Before instruction 1 cycle after i...

Page 120: ... src1 src2 dst C67x CPU only unit S1 or S2 Compatibility C67x and C67x CPU Opcode 31 29 28 27 23 22 18 17 13 12 11 5 4 3 2 1 0 creg z dst src2 src1 x op 1 1 0 s p 3 1 5 5 5 1 7 1 1 Opcode map field used For operand type Unit Opfield src1 src2 dst sp xsp sp L1 L2 001 0000 src1 src2 dst sp xsp sp S1 S2 111 0000 Description src2 is added to src1 The result is placed in dst Execution if cond src1 src2...

Page 121: ... are rounded as follows LFPN is the largest floating point number Overflow Output Rounding Mode Result Sign Nearest Even Zero Infinity Infinity infinity LFPN infinity LFPN infinity LFPN LFPN infinity 7 If underflow occurs the INEX and UNDER bits are set and the results are rounded as follows SPFN is the smallest floating point number Underflow Output Rounding Mode Result Sign Nearest Even Zero Inf...

Page 122: ...c1 src2 Written dst Unit in use L or S Instruction Type 4 cycle Delay Slots 3 Functional Unit Latency 1 See Also ADD ADDDP ADDU SUBSP Example ADDSP L1 A1 A2 A3 Before instruction 4 cycles after instruction A1 C020 0000h 2 5 A1 C020 0000h 2 5 A2 4109 999Ah 8 6 A2 4109 999Ah 8 6 A3 xxxx xxxxh A3 40C3 3334h 6 1 Pipeline ...

Page 123: ...2 11 5 4 3 2 1 0 creg z dst src2 src1 x op 1 1 0 s p 3 1 5 5 5 1 7 1 1 Opcode map field used For operand type Unit Opfield src1 src2 dst uint xuint ulong L1 L2 010 1011 src1 src2 dst xuint ulong ulong L1 L2 010 1001 Description src2 is added to src1 The result is placed in dst Execution if cond src1 src2 dst else nop Pipeline Stage E1 Read src1 src2 Written dst Unit in use L Instruction Type Singl...

Page 124: ...FFFF FF12h A5 A4 xxxx xxxxh A5 A4 0000 0001h 0000 316Ch 4294979948 Unsigned 32 bit integer Unsigned 40 bit long integer Example 2 ADDU L1 A1 A3 A2 A5 A4 Before instruction 1 cycle after instruction A1 0000 325Ah 12890 A1 0000 325Ah A3 A2 0000 00FFh FFFF FF12h 1099511627538 A3 A2 0000 00FFh FFFF FF12h A5 A4 0000 0000h 0000 0000h 0 A5 A4 0000 0000h 0000 316Ch 12652 Unsigned 32 bit integer Unsigned 4...

Page 125: ...tion The upper and lower halves of the src1 operand are added to the upper and lower halves of the src2 operand The values in src1 and src2 are treated as signed packed 16 bit data and the results are written in signed packed 16 bit format into dst For each pair of signed packed 16 bit values found in the src1 and src2 the sum between the 16 bit value from src1 and the 16 bit value from src2 is ca...

Page 126: ...rc1 lsb16 src2 lsb16 dst else nop Pipeline Stage E1 Read src1 src2 Written dst Unit in use S Instruction Type Single cycle Delay Slots 0 See Also ADD ADDU SUB2 Example ADD2 S1X A1 B1 A2 Before instruction 1 cycle after instruction A1 0021 37E1h 33 14305 A1 0021 37E1h A2 xxxx xxxxh A2 03BB 1C99h 955 7321 B1 039A E4B8h 922 58552 B1 039A E4B8h Pipeline ...

Page 127: ...dst uint xuint uint L1 L2 111 1011 src1 src2 dst scst5 xuint uint L1 L2 111 1010 Opcode S unit 31 29 28 27 23 22 18 17 13 12 11 6 5 4 3 2 1 0 creg z dst src2 src1 x op 1 1 0 0 s p 3 1 5 5 5 1 6 1 1 Opcode map field used For operand type Unit Opfield src1 src2 dst uint xuint uint S1 S2 01 1111 src1 src2 dst scst5 xuint uint S1 S2 01 1110 Description Perrforms a bitwise AND operation between src1 an...

Page 128: ...gle cycle Delay Slots 0 See Also OR XOR Example 1 AND L1X A1 B1 A2 Before instruction 1 cycle after instruction A1 F7A1 302Ah A1 F7A1 302Ah A2 xxxx xxxxh A2 02A0 2020h B1 02B6 E724h B1 02B6 E724h Example 2 AND L1 15 A1 A3 Before instruction 1 cycle after instruction A1 32E4 6936h A1 32E4 6936h A3 xxxx xxxxh A3 0000 0006h Pipeline ...

Page 129: ...for cst21 by the following formula cst21 label PCE1 2 If two branches are in the same execute packet and both are taken behavior is undefined Two conditional branches can be in the same execute packet if one branch uses a displacement and the other uses a register IRP or NRP As long as only one branch has a true condition the code executes in a well defined way Execution if cond cst21 2 PCE1 PFC e...

Page 130: ...A3 0000 0008 ADD L2 B1 B2 B3 0000 000C LOOP MPY M1X A3 B3 A4 0000 0010 SUB D1 A5 A6 A6 0000 0014 MPY M1 A3 A6 A5 0000 0018 MPY M1 A6 A7 A8 0000 001C SHR S1 A4 15 A4 0000 0020 ADD D1 A4 A6 A4 Table 3 13 Program Counter Values for Example Branch Using a Displacement Cycle Program Counter Value Action Cycle 0 0000 0000h Branch command executes target code fetched Cycle 1 0000 0004h Cycle 2 0000 000Ch...

Page 131: ...same execute packet and are both taken behavior is undefined Two conditional branches can be in the same execute packet if one branch uses a displacement and the other uses a register IRP or NRP As long as only one branch has a true condition the code executes in a well defined way Execution if cond src2 PFC else nop Notes 1 This instruction executes on S2 only PFC is program fetch counter 2 The e...

Page 132: ...1000 0000 B S2 B10 1000 0004 ADD L1 A1 A2 A3 1000 0008 ADD L2 B1 B2 B3 1000 000C MPY M1X A3 B3 A4 1000 0010 SUB D1 A5 A6 A6 1000 0014 MPY M1 A3 A6 A5 1000 0018 MPY M1 A6 A7 A8 1000 001C SHR S1 A4 15 A4 1000 0020 ADD D1 A4 A6 A4 Table 3 14 Program Counter Values for Example Branch Using a Register Cycle Program Counter Value Action Cycle 0 1000 0000h Branch command executes target code fetched Cycl...

Page 133: ...wo branches are in the same execute packet and are both taken behavior is undefined Two conditional branches can be in the same execute packet if one branch uses a displacement and the other uses a register IRP or NRP As long as only one branch has a true condition the code executes in a well defined way Execution if cond IRP PFC else nop Notes 1 This instruction executes on S2 only PFC is the pro...

Page 134: ...that an interrupt occurred at PC 0000 1000 IRP 0000 1000 0000 0020 B S2 IRP 0000 0024 ADD S1 A0 A2 A1 0000 0028 MPY M1 A1 A0 A1 0000 002C NOP 0000 0030 SHR S1 A1 15 A1 0000 0034 ADD L1 A1 A2 A1 0000 0038 ADD L2 B1 B2 B3 Table 3 15 Program Counter Values for B IRP Instruction Cycle Program Counter Value Action Cycle 0 0000 0020 Branch command executes target code fetched Cycle 1 0000 0024 Cycle 2 0...

Page 135: ...in the same execute packet and are both taken behavior is undefined Two conditional branches can be in the same execute packet if one branch uses a displacement and the other uses a register IRP or NRP As long as only one branch has a true condition the code executes in a well defined way Execution if cond NRP PFC else nop Notes 1 This instruction executes on S2 only PFC is program fetch counter 2...

Page 136: ...an interrupt occurred at PC 0000 1000 NRP 0000 1000 0000 0020 B S2 NRP 0000 0024 ADD S1 A0 A2 A1 0000 0028 MPY M1 A1 A0 A1 0000 002C NOP 0000 0030 SHR S1 A1 15 A1 0000 0034 ADD L1 A1 A2 A1 0000 0038 ADD L2 B1 B2 B3 Table 3 16 Program Counter Values for B NRP Instruction Cycle Program Counter Value Action Cycle 0 0000 0020 Branch command executes target code fetched Cycle 1 0000 0024 Cycle 2 0000 0...

Page 137: ...rm 31 29 28 27 23 22 18 17 13 12 8 7 6 5 4 3 2 1 0 creg z dst src2 csta cstb 1 0 0 0 1 0 s p 3 1 5 5 5 5 1 1 Opcode map field used For operand type Unit src2 csta cstb dst uint ucst5 ucst5 uint S1 S2 Opcode Register form 31 29 28 27 23 22 18 17 13 12 11 6 5 4 3 2 1 0 creg z dst src2 src1 x 1 1 1 0 1 1 1 0 0 0 s p 3 1 5 5 5 1 1 1 Opcode map field used For operand type Unit src2 src1 dst xuint uint ...

Page 138: ...below csta is 15 and cstb is 23 Only the ten LSBs are valid for the register version of the instruction If any of the 22 MSBs are non zero the result is invalid src2 dst 0 x x x x x x x x x x x x x x x x x x x x x x x 1 1 1 1 1 0 0 0 0 x x x x x x x x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 csta cstb 31 30 ...

Page 139: ...1 A1 4 19 A2 Before instruction 1 cycle after instruction A1 07A4 3F2Ah A1 07A4 3F2Ah A2 xxxx xxxxh A2 07A0 000Ah Example 2 CLR S2 B1 B3 B2 Before instruction 1 cycle after instruction B1 03B6 E7D5h B1 03B6 E7D5h B2 xxxx xxxxh B2 03B0 0001h B3 0000 0052h B3 0000 0052h ...

Page 140: ... creg z dst src2 src1 x op 1 1 0 s p 3 1 5 5 5 1 7 1 1 Opcode map field used For operand type Unit Opfield src1 src2 dst sint xsint uint L1 L2 101 0011 src1 src2 dst scst5 xsint uint L1 L2 101 0010 src1 src2 dst xsint slong uint L1 L2 101 0001 src1 src2 dst scst5 slong uint L1 L2 101 0000 Description Compares src1 to src2 If src1 equals src2 then 1 is written to dst otherwise 0 is written to dst E...

Page 141: ...cycle after instruction A1 0000 04B8h 1208 A1 0000 04B8h A2 xxxx xxxxh A2 0000 0000h false B1 0000 04B7h 1207 B1 0000 04B7h Example 2 CMPEQ L1 Ch A1 A2 Before instruction 1 cycle after instruction A1 0000 000Ch 12 A1 0000 000Ch A2 xxxx xxxxh A2 0000 0001h true Example 3 CMPEQ L2X A1 B3 B2 B1 Before instruction 1 cycle after instruction A1 F23A 3789h A1 F23A 3789h B1 xxxx xxxxh B1 0000 0001h true B...

Page 142: ... 5 5 1 1 1 Opcode map field used For operand type Unit src1 src2 dst dp xdp sint S1 S2 Description Compares src1 to src2 If src1 equals src2 then 1 is written to dst otherwise 0 is written to dst Execution if cond if src1 src2 1 dst else 0 dst else nop Special cases of inputs Input FAUCR Bits src1 src2 Output UNORD INVAL NaN don t care 0 1 0 don t care NaN 0 1 0 NaN NaN 0 1 0 denormalized 0 1 0 0 ...

Page 143: ...bits when appropriate Pipeline Stage E1 E2 Read src1_l src2_l src1_h src2_h Written dst Unit in use S S Instruction Type DP compare Delay Slots 1 Functional Unit Latency 2 See Also CMPEQ CMPEQSP CMPGTDP CMPLTDP Example CMPEQDP S1 A1 A0 A3 A2 A4 Before instruction 2 cycles after instruction A1 A0 4021 3333h 3333 3333h 8 6 A1 A0 4021 3333h 3333 3333h 8 6 A3 A2 C004 0000h 0000 0000h 2 5 A3 A2 C004 00...

Page 144: ... 5 5 1 1 1 Opcode map field used For operand type Unit src1 src2 dst sp xsp sint S1 S2 Description Compares src1 to src2 If src1 equals src2 then 1 is written to dst otherwise 0 is written to dst Execution if cond if src1 src2 1 dst else 0 dst else nop Special cases of inputs Input FAUCR Bits src1 src2 Output UNORD INVAL NaN don t care 0 1 0 don t care NaN 0 1 0 NaN NaN 0 1 0 denormalized 0 1 0 0 ...

Page 145: ...ing table are set except for the NaNn and DENn bits when appropriate Pipeline Stage E1 Read src1 src2 Written dst Unit in use S Instruction Type Single cycle Delay Slots 0 Functional Unit Latency 1 See Also CMPEQ CMPEQDP CMPGTSP CMPLTSP Example CMPEQSP S1 A1 A2 A3 Before instruction 1 cycle after instruction A1 C020 0000h 2 5 A1 C020 0000h 2 5 A2 4109 999Ah 8 6 A2 4109 999Ah 8 6 A3 xxxx xxxxh A3 0...

Page 146: ...ibility C62x C64x C67x and C67x CPU Opcode 31 29 28 27 23 22 18 17 13 12 11 5 4 3 2 1 0 creg z dst src2 src1 x op 1 1 0 s p 3 1 5 5 5 1 7 1 1 Opcode map field used For operand type Unit Opfield src1 src2 dst sint xsint uint L1 L2 100 0111 src1 src2 dst scst5 xsint uint L1 L2 100 0110 src1 src2 dst xsint slong uint L1 L2 100 0101 src1 src2 dst scst5 slong uint L1 L2 100 0100 ...

Page 147: ...with the second instruction using the conventional operand types for src1 and src2 Similarly the CMPGT instruction allows a cross path operand to be used as src2 If src1 is a cross path operand as in CMPGT L1x B4 A5 A0 Then to implement this operation the assembler converts this instruction to CMPLT L1x A5 B4 A0 In both of these operations the listing file lst will have the first implementa tion a...

Page 148: ...T L1X A1 B1 A2 Before instruction 1 cycle after instruction A1 FFFF FE91h 367 A1 FFFF FE91h A2 xxxx xxxxh A2 0000 0001h true B1 FFFF FDC4h 572 B1 FFFF FDC4h Example 3 CMPGT L1 8 A1 A2 Before instruction 1 cycle after instruction A1 0000 0023h 35 A1 0000 0023h A2 xxxx xxxxh A2 0000 0000h false Example 4 CMPGT L1X A1 B1 A2 Before instruction 1 cycle after instruction A1 0000 00EBh 235 A1 0000 00EBh ...

Page 149: ... 5 5 1 1 1 Opcode map field used For operand type Unit src1 src2 dst dp xdp sint S1 S2 Description Compares src1 to src2 If src1 is greater than src2 then 1 is written to dst otherwise 0 is written to dst Execution if cond if src1 src2 1 dst else 0 dst else nop Special cases of inputs Input FAUCR Bits src1 src2 Output UNORD INVAL NaN don t care 0 1 1 don t care NaN 0 1 1 NaN NaN 0 1 1 denormalized...

Page 150: ...age E1 E2 Read src1_l src2_l src1_h src2_h Written dst Unit in use S S Instruction Type DP compare Delay Slots 1 Functional Unit Latency 2 See Also CMPEQDP CMPGT CMPGTSP CMPGTU CMPLTDP Example CMPGTDP S1 A1 A0 A3 A2 A4 Before instruction 2 cycles after instruction A1 A0 4021 3333h 3333 3333h 8 6 A1 A0 4021 3333h 3333 3333h 8 6 A3 A2 c004 0000h 0000 0000h 2 5 A3 A2 c004 0000h 0000 0000h 2 5 A4 XXXX...

Page 151: ...5 5 1 1 1 Opcode map field used For operand type Unit src1 src2 dst sp xsp sint S1 S2 Description Compares src1 to src2 If src1 is greater than src2 then 1 is written to dst otherwise 0 is written to dst Execution if cond if src1 src2 1 dst else 0 dst else nop Special cases of inputs Input FAUCR Fields src1 src2 Output UNORD INVAL NaN don t care 0 1 1 don t care NaN 0 1 1 NaN NaN 0 1 1 denormalize...

Page 152: ...DENn bits when appropriate Pipeline Stage E1 Read src1 src2 Written dst Unit in use S Instruction Type Single cycle Delay Slots 0 Functional Unit Latency 1 See Also CMPEQSP CMPGT CMPGTDP CMPGTU CMPLTSP Example CMPGTSP S1X A1 B2 A3 Before instruction 1 cycle after instruction A1 C020 0000h 2 5 A1 C020 0000h 2 5 B2 4109 999Ah 8 6 B2 4109 999Ah 8 6 A3 XXXX XXXXh A3 0000 0000h false Pipeline ...

Page 153: ...rand type Unit Opfield src1 src2 dst uint xuint uint L1 L2 100 1111 src1 src2 dst ucst4 xuint uint L1 L2 100 1110 src1 src2 dst xuint ulong uint L1 L2 100 1101 src1 src2 dst ucst4 ulong uint L1 L2 100 1100 Description Performs an unsigned comparison of src1 to src2 If src1 is greater than src2 then a 1 is written to dst otherwise a 0 is written to dst Only the four LSBs are valid in the 5 bit dst ...

Page 154: ...1 0000 0128h 296 A1 0000 0128h A2 FFFF FFDEh 4294967262 A2 FFFF FFDEh A3 xxxx xxxxh A3 0000 0000h false Unsigned 32 bit integer Example 2 CMPGTU L1 0Ah A1 A2 Before instruction 1 cycle after instruction A1 0000 0005h 5 A1 0000 0005h A2 xxxx xxxxh A2 0000 0001h true Unsigned 32 bit integer Example 3 CMPGTU L1 0Eh A3 A2 A4 Before instruction 1 cycle after instruction A3 A2 0000 0000h 0000 000Ah 10 A...

Page 155: ...lity C62x C64x C67x and C67x CPU Opcode 31 29 28 27 23 22 18 17 13 12 11 5 4 3 2 1 0 creg z dst src2 src1 x op 1 1 0 s p 3 1 5 5 5 1 7 1 1 Opcode map field used For operand type Unit Opfield src1 src2 dst sint xsint uint L1 L2 101 0111 src1 src2 dst scst5 xsint uint L1 L2 101 0110 src1 src2 dst xsint slong uint L1 L2 101 0101 src1 src2 dst scst5 slong uint L1 L2 101 0100 ...

Page 156: ...the second instruction using the conventional operand types for src1 and src2 Similarly the CMPLT instruction allows a cross path operand to be used as src2 If src1 is a cross path operand as in CMPLT L1x B4 A5 A0 Then to implement this operation the assembler converts this instruction to CMPGT L1x A5 B4 A0 In both of these operations the listing file lst will have the first implementa tion and th...

Page 157: ...7E2h A2 0000 0F6Bh 3947 A2 0000 0F6Bh A3 xxxx xxxxh A3 0000 0001h true Example 2 CMPLT L1 A1 A2 A3 Before instruction 1 cycle after instruction A1 FFFF FED6h 298 A1 FFFF FED6h A2 0000 000Ch 12 A2 0000 000Ch A3 xxxx xxxxh A3 0000 0001h true Example 3 CMPLT L1 9 A1 A2 Before instruction 1 cycle after instruction A1 0000 0005h 5 A1 0000 0005h A2 xxxx xxxxh A2 0000 0000h false ...

Page 158: ... 5 1 1 1 Opcode map field used For operand type Unit src1 src2 dst dp xdp sint S1 S2 Description Compares src1 to src2 If src1 is less than src2 then 1 is written to dst other wise 0 is written to dst Execution if cond if src1 src2 1 dst else 0 dst else nop Special cases of inputs Input FAUCR Bits src1 src2 Output UNORD INVAL NaN don t care 0 1 1 don t care NaN 0 1 1 NaN NaN 0 1 1 denormalized 0 0...

Page 159: ...2 Read src1_l src2_l src1_h src2_h Written dst Unit in use S S Instruction Type DP compare Delay Slots 1 Functional Unit Latency 2 See Also CMPEQDP CMPGTDP CMPLT CMPLTSP CMPLTU Example CMPLTDP S1X A1 A0 B3 B2 A4 Before instruction 2 cycles after instruction A1 A0 4021 3333h 3333 3333h 8 6 A1 A0 4021 3333h 4021 3333h 8 6 B3 B2 c004 0000h 0000 0000h 2 5 B3 B2 c004 0000h 0000 0000h 2 5 A4 xxxx xxxxh ...

Page 160: ... 5 1 1 1 Opcode map field used For operand type Unit src1 src2 dst sp xsp sint S1 S2 Description Compares src1 to src2 If src1 is less than src2 then 1 is written to dst other wise 0 is written to dst Execution if cond if src1 src2 1 dst else 0 dst else nop Special cases of inputs Input FAUCR Bits src1 src2 Output UNORD INVAL NaN don t care 0 1 1 don t care NaN 0 1 1 NaN NaN 0 1 1 denormalized 0 0...

Page 161: ...n bits when appropriate Pipeline Stage E1 Read src1 src2 Written dst Unit in use S Instruction Type Single cycle Delay Slots 0 Functional Unit Latency 1 See Also CMPEQSP CMPGTSP CMPLT CMPLTDP CMPLTU Example CMPLTSP S1 A1 A2 A3 Before instruction 1 cycle after instruction A1 C020 0000h 2 5 A1 C020 0000h 2 5 A2 4109 999Ah 8 6 A2 4109 999Ah 8 6 A3 xxxx xxxxh A3 0000 0001h true Pipeline ...

Page 162: ... src2 src1 x op 1 1 0 s p 3 1 5 5 5 1 7 1 1 Opcode map field used For operand type Unit Opfield src1 src2 dst uint xuint uint L1 L2 101 1111 src1 src2 dst ucst4 xuint uint L1 L2 101 1110 src1 src2 dst xuint ulong uint L1 L2 101 1101 src1 src2 dst ucst4 ulong uint L1 L2 101 1100 Description Performs an unsigned comparison of src1 to src2 If src1 is less than src2 then 1 is written to dst otherwise ...

Page 163: ...2 FFFF F35Eh 4294964062 A2 FFFF F35Eh A3 xxxx xxxxh A3 0000 0001h true Unsigned 32 bit integer Example 2 CMPLTU L1 14 A1 A2 Before instruction 1 cycle after instruction A1 0000 000Fh 15 A1 0000 000Fh A2 xxxx xxxxh A2 0000 0001h true Unsigned 32 bit integer Example 3 CMPLTU L1 A1 A5 A4 A2 Before instruction 1 cycle after instruction A1 003B 8260h 3900000 A1 003B 8260h A2 xxxx xxxxh A2 0000 0000h fa...

Page 164: ...rc2 is converted to an integer and placed in dst The operand is read in one cycle by using the src2 port for the 32 MSBs and the src1 port for the 32 LSBs Execution if cond int src2 dst else nop Notes 1 If src2 is NaN the maximum signed integer 7FFF FFFFh or 8000 0000h is placed in dst and the INVAL bit is set 2 If src2 is signed infinity or if overflow occurs the maximum signed integer 7FFF FFFFh...

Page 165: ...4 Read src2_l src2_h Written dst Unit in use L Instruction Type 4 cycle Delay Slots 3 Functional Unit Latency 1 See Also DPSP DPTRUNC INTDP SPINT Example DPINT L1 A1 A0 A4 Before instruction 4 cycles after instruction A1 A0 4021 3333h 3333 3333h 8 6 A1 A0 4021 3333h 3333 3333h 8 6 A4 xxxx xxxxh A4 0000 0009h 9 Pipeline ...

Page 166: ...operand is read in one cycle by using the src2 port for the 32 MSBs and the src1 port for the 32 LSBs Execution if cond sp src2 dst else nop Notes 1 If rounding is performed the INEX bit is set 2 If src2 is SNaN NaN_out is placed in dst and the INVAL and NAN2 bits are set 3 If src2 is QNaN NaN_out is placed in dst and the NAN2 bit is set 4 If src2 is a signed denormalized number signed 0 is placed...

Page 167: ...ber Underflow Output Rounding Mode Result Sign Nearest Even Zero Infinity Infinity 0 0 SFPN 0 0 0 0 SFPN Pipeline Stage E1 E2 E3 E4 Read src2_l src2_h Written dst Unit in use L Instruction Type 4 cycle Delay Slots 3 Functional Unit Latency 1 See Also DPINT DPTRUNC INTSP SPDP Example DPSP L1 A1 A0 A4 Before instruction 4 cycles after instruction A1 A0 4021 3333h 3333 3333h 8 6 A1 A0 4021 3333h 4021...

Page 168: ...s instruction operates like DPINT except that the rounding modes in the FADCR are ignored round toward zero truncate is always used The 64 bit operand is read in one cycle by using the src2 port for the 32 MSBs and the src1 port for the 32 LSBs Execution if cond int src2 dst else nop Notes 1 If src2 is NaN the maximum signed integer 7FFF FFFFh or 8000 0000h is placed in dst and the INVAL bit is se...

Page 169: ... E1 E2 E3 E4 Read src2_l src2_h Written dst Unit in use L Instruction Type 4 cycle Delay Slots 3 Functional Unit Latency 1 See Also DPINT DPSP SPTRUNC Example DPTRUNC L1 A1 A0 A4 Before instruction 4 cycles after instruction A1 A0 4021 3333h 3333 3333h 8 6 A1 A0 4021 3333h 3333 3333h 8 6 A4 xxxx xxxxh A4 0000 0008h 8 Pipeline ...

Page 170: ...Opcode Constant form 31 29 28 27 23 22 18 17 13 12 8 7 6 5 4 3 2 1 0 creg z dst src2 csta cstb 0 1 0 0 1 0 s p 3 1 5 5 5 5 1 1 Opcode map field used For operand type Unit src2 csta cstb dst sint ucst5 ucst5 sint S1 S2 Opcode Register form 31 29 28 27 23 22 18 17 13 12 11 6 5 4 3 2 1 0 creg z dst src2 src1 x 1 0 1 1 1 1 1 0 0 0 s p 3 1 5 5 5 1 1 1 Opcode map field used For operand type Unit src2 sr...

Page 171: ...re valid for the register version of the instruction If any of the 22 MSBs are non zero the result is invalid csta x cstb csta src2 dst x x x x x x x x 1 1 0 1 x x x x x x x x x x x x x 0 1 0 x 1 0 1 1 0 1 0 0 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 x x x 0 0 0 0 0 1 1 1 1 1 0 0 0 x x x x x x x x 0 0 0 0 0 0 0 0 Shifts left by 12 to produce Then shifts right by 23 to produce 1 2 3 31 3...

Page 172: ... Slots 0 See Also EXTU Example 1 EXT S1 A1 10 19 A2 Before instruction 1 cycle after instruction A1 07A4 3F2Ah A1 07A4 3F2Ah A2 xxxx xxxxh A2 FFFF F21Fh Example 2 EXT S1 A1 A2 A3 Before instruction 1 cycle after instruction A1 03B6 E7D5h A1 03B6 E7D5h A2 0000 0073h A2 0000 0073h A3 xxxx xxxxh A3 0000 03B6h ...

Page 173: ... width and offset form 31 29 28 27 23 22 18 17 13 12 8 7 6 5 4 3 2 1 0 creg z dst src2 csta cstb 0 0 0 0 1 0 s p 3 1 5 5 5 5 1 1 Opcode map field used For operand type Unit src2 csta cstb dst uint ucst5 ucst5 uint S1 S2 Opcode Register width and offset form 31 29 28 27 23 22 18 17 13 12 11 6 5 4 3 2 1 0 creg z dst src2 src1 x 1 0 1 0 1 1 1 0 0 0 s p 3 1 5 5 5 1 1 1 Opcode map field used For operan...

Page 174: ...or the register version of the instruction If any of the 22 MSBs are non zero the result is invalid 0 1 0 1 0 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x csta cstb cst a x x x x x x x x 1 1 0 1 x x x x x x x x x x x x x 0 1 0 x 1 0 src2 dst x x x 0 0 0 0 0 1 1 1 1 1 0 0 0 x x x x x x x x 0 0 0 0 0 0 0 0 Shifts left by 12 to produce Then shifts right by 23 to produce 1 2 3 31 30 29 28 2...

Page 175: ... Slots 0 See Also EXT Example 1 EXTU S1 A1 10 19 A2 Before instruction 1 cycle after instruction A1 07A4 3F2Ah A1 07A4 3F2Ah A2 xxxx xxxxh A2 0000 121Fh Example 2 EXTU S1 A1 A2 A3 Before instruction 1 cycle after instruction A1 03B6 E7D5h A1 03B6 E7D5h A2 0000 0156h A2 0000 0156h A3 xxxx xxxxh A3 0000 036Eh ...

Page 176: ...ne Compatibility C62x C64x C67x and C67x CPU Opcode 31 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 s p 14 1 1 Description Performs an infinite multicycle NOP that terminates upon servicing an interrupt or a branch occurs due to an IDLE instruction being in the delay slots of a branch Instruction Type NOP Delay Slots 0 ...

Page 177: ...scription The signed integer value in src2 is converted to a double precision value and placed in dst Execution if cond dp src2 dst else nop You cannot set configuration bits with this instruction Pipeline Stage E1 E2 E3 E4 E5 Read src2 Written dst_l dst_h Unit in use L If dst is used as the source for the ADDDP CMPEQDP CMPLTDP CMPGTDP MPYDP or SUBDP instruction the number of delay slots can be re...

Page 178: ...sion Floating Point Value 3 118 Instruction Set SPRU733 Example INTDP L1x B4 A1 A0 Before instruction 5 cycles after instruction B4 1965 1127h 426053927 B4 1965 1127h 426053927 A1 A0 xxxx xxxxh xxxx xxxxh A1 A0 41B9 6511h 2700 0000h 4 2605393 E08 ...

Page 179: ... L2 Description The unsigned integer value in src2 is converted to a double precision value and placed in dst Execution if cond dp src2 dst else nop You cannot set configuration bits with this instruction Pipeline Stage E1 E2 E3 E4 E5 Read src2 Written dst_l dst_h Unit in use L If dst is used as the source for the ADDDP CMPEQDP CMPLTDP CMPGTDP MPYDP or SUBDP instruction the number of delay slots c...

Page 180: ...sion Floating Point Value 3 120 Instruction Set SPRU733 Example INTDPU L1 A4 A1 A0 Before instruction 5 cycles after instruction A4 FFFF FFDEh 4294967262 A4 FFFF FFDEh 4294967262 A1 A0 xxxx xxxxh xxxx xxxxh A1 A0 41EF FFFFh FBC0 0000h 4 2949673 E09 ...

Page 181: ... type Unit src2 dst xsint sp L1 L2 Description The signed integer value in src2 is converted to single precision value and placed in dst Execution if cond sp src2 dst else nop The only configuration bit that can be set is the INEX bit and only if the mantissa is rounded Pipeline Stage E1 E2 E3 E4 Read src2 Written dst Unit in use L Instruction Type 4 cycle Delay Slots 3 Functional Unit Latency 1 S...

Page 182: ...d type Unit src2 dst xuint sp L1 L2 Description The unsigned integer value in src2 is converted to single precision value and placed in dst Execution if cond sp src2 dst else nop The only configuration bit that can be set is the INEX bit and only if the mantissa is rounded Pipeline Stage E1 E2 E3 E4 Read src2 Written dst Unit in use L Instruction Type 4 cycle Delay Slots 3 Functional Unit Latency ...

Page 183: ...her a register offsetR or a 5 bit unsigned constant ucst5 If an offset is not given the assembler assigns an offset of zero offsetR and baseR must be in the same register file and on the same side as the D unit used The y bit in the opcode determines the D unit and register file used y 0 selects the D1 unit and baseR and offsetR from the A register file and y 1 selects the D2 unit and baseR and of...

Page 184: ... and s 1 indicates dst will be loaded in the B register file The r bit should be cleared to 0 Increments and decrements default to 1 and offsets default to 0 when no bracketed register or constant is specified Loads that do no modification to the baseR can use the syntax R Square brackets indicate that the ucst5 offset is left shifted by 0 Parentheses can be used to set a nonscaled constant offset...

Page 185: ...et LDB U 3 125 Instruction Set SPRU733 Example LDB D1 A5 4 A7 Before LDB 1 cycle after LDB 5 cycles after LDB A5 0000 0204h A5 0000 0204h A5 0000 0204h A7 1951 1970h A7 1951 1970h A7 FFFF FFE1h AMR 0000 0000h AMR 0000 0000h AMR 0000 0000h mem 200h E1h mem 200h E1h mem 200h E1h ...

Page 186: ...cst15 is scaled by a left shift of 0 bits After scaling ucst15 is added to baseR Subtraction is not supported The result of the calculation is the address sent to memory The addressing arithmetic is always performed in linear mode For LDB U the values are loaded into the 8 LSBs of dst For LDB the upper 24 bits of dst values are sign extended for LDBU the upper 24 bits of dst are zero filled The s ...

Page 187: ... Stage E1 E2 E3 E4 E5 Read B14 B15 Written dst Unit in use D2 Instruction Type Load Delay Slots 4 See Also LDH LDW Example LDB D2 B14 36 B1 Before LDB 1 cycle after LDB B1 XXXX XXXXh B1 XXXX XXXXh B14 0000 0100h B14 0000 0100h mem 124 127h 4E7A FF12h mem 124 127h 4E7A FF12h mem 124h 12h mem 124h 12h 5 cycles after LDB B1 0000 0012h B14 0000 0100h mem 124 127h 4E7A FF12h mem 124h 12h Pipeline ...

Page 188: ...s the D unit used The ybit in the opcode determines the D unit and the regis ter file used y 0 selects the D1 unit and the baseR and offsetR from the A register file and y 1 selects the D2 unit and baseR and offsetR from the B register file The s bit determines the register file into which the dst is loaded s 0 indicates that dst is in the A register file and s 1 indicates that dst is in the B reg...

Page 189: ...loating point value 64 bits a pair of single precision floating point words 32 bits or a pair of 32 bit integers The least significant 32 bits are loaded into the even numbered register and the most significant 32 bits containing the sign bit and exponent are loaded into the next register which is always odd numbered register The register pair syntax places the odd register first followed by a col...

Page 190: ...33h 3333 3333h B10 0000 0010h 16 B10 0000 0010h 16 mem 18h 3333 3333h 4021 3333h 8 6 mem 18h 3333 3333h 4021 3333h 8 6 Little endian mode Example 2 LDDW D1 A10 1 A1 A0 Before instruction 1 cycle after instruction A1 A0 xxxx xxxxh xxxx xxxxh A1 A0 xxxx xxxxh xxxx xxxxh A10 0000 0010h 16 A10 0000 0018h 24 mem 18h 4021 3333h 3333 3333h 8 6 mem 18h 4021 3333h 3333 3333h 8 6 5 cycles after instruction ...

Page 191: ... is either a register offsetR or a 5 bit unsigned constant ucst5 If an offset is not given the assembler assigns an offset of zero offsetR and baseR must be in the same register file and on the same side as the D unit used The y bit in the opcode determines the D unit and register file used y 0 selects the D1 unit and baseR and offsetR from the A register file and y 1 selects the D2 unit and baseR...

Page 192: ...ed in the B register file The r bit should be cleared to 0 Increments and decrements default to 1 and offsets default to 0 when no bracketed register or constant is specified Loads that do no modification to the baseR can use the syntax R Square brackets indicate that the ucst5 offset is left shifted by 1 Parentheses can be used to set a nonscaled constant offset You must type either brackets or p...

Page 193: ...ction Set SPRU733 Example LDH D1 A4 A1 A8 Before LDH 1 cycle after LDH 5 cycles after LDH A1 0000 0002h A1 0000 0002h A1 0000 0002h A4 0000 0020h A4 0000 0024h A4 0000 0024h A8 1103 51FFh A8 1103 51FFh A8 FFFF A21Fh AMR 0000 0000h AMR 0000 0000h AMR 0000 0000h mem 24h A21Fh mem 24h A21Fh mem 24h A21Fh ...

Page 194: ... in magnitude This instruc tion operates only on the D2 unit The offset ucst15 is scaled by a left shift of 1 bit After scaling ucst15 is added to baseR Subtraction is not supported The result of the calculation is the address sent to memory The addressing arithmetic is always performed in linear mode For LDH U the values are loaded into the 16 LSBs of dst For LDH the upper 16 bits of dst are sign...

Page 195: ... Offset Mnemonic op Field Load Data Type SIze Left Shift of Offset LDH 1 0 0 Load halfword 16 1 bit LDHU 0 0 0 Load halfword unsigned 16 1 bit Execution if cond mem dst else nop Note This instruction executes only on the B side D2 Pipeline Stage E1 E2 E3 E4 E5 Read B14 B15 Written dst Unit in use D2 Instruction Type Load Delay Slots 4 See Also LDB LDW Pipeline ...

Page 196: ...e D unit and register file used y 0 selects the D1 unit and baseR and offsetR from the A register file and y 1 selects the D2 unit and baseR and offsetR from the B register file offsetR ucst5 is scaled by a left shift of 2 bits After scaling offsetR ucst5 is added to or subtracted from baseR For the preincrement predecrement positive offset and negative offset address generator options the result ...

Page 197: ...e LDW unit baseR 12 dst represents an offset of 12 bytes whereas LDW unit baseR 12 dst represents an offset of 12 words or 48 bytes You must type either brackets or parentheses around the specified offset if you use the optional offset parameter Word addresses must be aligned on word two LSBs are 0 boundaries Execution if cond mem dst else nop Pipeline Stage E1 E2 E3 E4 E5 Read baseR offsetR Writt...

Page 198: ...6 Before LDW 1 cycle after LDW 5 cycles after LDW A4 0000 0100h A4 0000 0104h A4 0000 0104h A6 1234 4321h A6 1234 4321h A6 0798 F25Ah AMR 0000 0000h AMR 0000 0000h AMR 0000 0000h mem 100h 0798 F25Ah mem 100h 0798 F25Ah mem 100h 0798 F25Ah mem 104h 1970 19F3h mem 104h 1970 19F3h mem 104h 1970 19F3h Example 3 LDW D1 A4 1 A6 Before LDW 1 cycle after LDW 5 cycles after LDW A4 0000 0100h A4 0000 0104h ...

Page 199: ...g ucst15 is added to baseR Subtraction is not supported The result of the calculation is the address sent to memory The addressing arithmetic is always performed in linear mode For LDW the entire 32 bits fills dst dst can be in either register file The s bit determines which file dst will be loaded into s 0 indicates dst will be loaded in the A register file and s 1 indicates dst will be loaded in...

Page 200: ...d From Memory With a 15 Bit Unsigned Constant Offset 3 140 Instruction Set SPRU733 Pipeline Stage E1 E2 E3 E4 E5 Read B14 B15 Written dst Unit in use D2 Instruction Type Load Delay Slots 4 See Also LDB LDH Pipeline ...

Page 201: ...to the left of the first 1 or 0 when searching for a 1 or 0 respectively is placed in dst The following diagram illustrates the operation of LMBD for several cases 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 x 0 1 x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x 0 0 0 x x x 0 1 x x x x x x x x x x x x x x x x x When searching for 1 in src2 LMBD returns 4 ...

Page 202: ...t if src10 1 lmb1 src2 dst else nop Pipeline Stage E1 Read src1 src2 Written dst Unit in use L Instruction Type Single cycle Delay Slots 0 Example LMBD L1 A1 A2 A3 Before instruction 1 cycle after instruction A1 0000 0001h A1 0000 0001h A2 009E 3A81h A2 009E 3A81h A3 xxxx xxxxh A3 0000 0008h Pipeline ...

Page 203: ...p 3 1 5 5 5 1 5 1 1 Opcode map field used For operand type Unit Opfield src1 src2 dst slsb16 xslsb16 sint M1 M2 11001 src1 src2 dst scst5 xslsb16 sint M1 M2 11000 Description The src1 operand is multiplied by the src2 operand The result is placed in dst The source operands are signed by default Execution if cond lsb16 src1 lsb16 src2 dst else nop Pipeline Stage E1 E2 Read src1 src2 Written dst Uni...

Page 204: ...ruction 2 cycles after instruction A1 0000 0123h 291 A1 0000 0123h A2 01E0 FA81h 1407 A2 01E0 FA81h A3 xxxx xxxxh A3 FFF9 C0A3 409437 Signed 16 LSB integer Example 2 MPY M1 13 A1 A2 Before instruction 2 cycles after instruction A1 3497 FFF3h 13 A1 3497 FFF3h A2 xxxx xxxxh A2 FFFF FF57h 163 Signed 16 LSB integer ...

Page 205: ...a signed NaN_out If either source is SNaN the INVAL bit is set also The sign of NaN_out is the exclusive OR of the input signs 2 Signed infinity multiplied by signed infinity or a normalized number other than signed 0 returns signed infinity Signed infinity multiplied by signed 0 returns a signed NaN_out and sets the INVAL bit 3 If one or both sources are signed 0 the result is signed 0 unless the...

Page 206: ...tion the number of delay slots can be reduced by one because these instructions read the lower word of the DP source one cycle before the upper word of the DP source Instruction Type MPYDP Delay Slots 9 Functional Unit Latency 4 See Also MPY MPYSP Example MPYDP M1 A1 A0 A3 A2 A5 A4 Before instruction 10 cycles after instruction A1 A0 4021 3333h 3333 3333h 8 6 A1 A0 4021 3333h 4021 3333h 8 6 A3 A2 ...

Page 207: ...rc2 src1 x 0 0 0 0 1 0 0 0 0 0 s p 3 1 5 5 5 1 1 1 Opcode map field used For operand type Unit src1 src2 dst smsb16 xsmsb16 sint M1 M2 Description The src1 operand is multiplied by the src2 operand The result is placed in dst The source operands are signed by default Execution if cond msb16 src1 msb16 src2 dst else nop Pipeline Stage E1 E2 Read src1 src2 Written dst Unit in use M Instruction Type ...

Page 208: ...Signed 16 MSB 3 148 Instruction Set SPRU733 Example MPYH M1 A1 A2 A3 Before instruction 2 cycles after instruction A1 0023 0000h 35 A1 0023 0000h A2 FFA7 1234h 89 A2 FFA7 1234h A3 xxxx xxxxh A3 FFFF F3D5h 3115 Signed 16 MSB integer ...

Page 209: ...rc2 src1 x 0 1 0 0 1 0 0 0 0 0 s p 3 1 5 5 5 1 1 1 Opcode map field used For operand type Unit src1 src2 dst smsb16 xslsb16 sint M1 M2 Description The src1 operand is multiplied by the src2 operand The result is placed in dst The source operands are signed by default Execution if cond msb16 src1 lsb16 src2 dst else nop Pipeline Stage E1 E2 Read src1 src2 Written dst Unit in use M Instruction Type ...

Page 210: ...B 3 150 Instruction Set SPRU733 Example MPYHL M1 A1 A2 A3 Before instruction 2 cycles after instruction A1 008A 003Eh 138 A1 008A 003Eh A2 21FF 00A7h 167 A2 21FF 00A7h A3 xxxx xxxxh A3 0000 5A06h 23046 Signed 16 MSB integer Signed 16 LSB integer ...

Page 211: ... z dst src2 src1 x 0 1 1 1 1 0 0 0 0 0 s p 3 1 5 5 5 1 1 1 Opcode map field used For operand type Unit src1 src2 dst umsb16 xulsb16 uint M1 M2 Description The src1 operand is multiplied by the src2 operand The result is placed in dst The source operands are unsigned by default Execution if cond msb16 src1 lsb16 src2 dst else nop Pipeline Stage E1 E2 Read src1 src2 Written dst Unit in use M Instruc...

Page 212: ... p 3 1 5 5 5 1 1 1 Opcode map field used For operand type Unit src1 src2 dst smsb16 xulsb16 sint M1 M2 Description The signed operand src1 is multiplied by the unsigned operand src2 The result is placed in dst The S is needed in the mnemonic to specify a signed operand when both signed and unsigned operands are used Execution if cond msb16 src1 lsb16 src2 dst else nop Pipeline Stage E1 E2 Read src...

Page 213: ...tion The signed operand src1 is multiplied by the unsigned operand src2 The result is placed in dst The S is needed in the mnemonic to specify a signed operand when both signed and unsigned operands are used Execution if cond msb16 src1 msb16 src2 dst else nop Pipeline Stage E1 E2 Read src1 src2 Written dst Unit in use M Instruction Type Multiply 16 16 Delay Slots 1 See Also MPYH MPYHU MPYHUS Exam...

Page 214: ...c2 dst umsb16 xumsb16 uint M1 M2 Description The src1 operand is multiplied by the src2 operand The result is placed in dst The source operands are unsigned by default Execution if cond msb16 src1 msb16 src2 dst else nop Pipeline Stage E1 E2 Read src1 src2 Written dst Unit in use M Instruction Type Multiply 16 16 Delay Slots 1 See Also MPYH MPYHSU MPYHUS Example MPYHU M1 A1 A2 A3 Before instructio...

Page 215: ... p 3 1 5 5 5 1 1 1 Opcode map field used For operand type Unit src1 src2 dst umsb16 xslsb16 sint M1 M2 Description The unsigned operand src1 is multiplied by the signed operand src2 The result is placed in dst The S is needed in the mnemonic to specify a signed operand when both signed and unsigned operands are used Execution if cond msb16 src1 lsb16 src2 dst else nop Pipeline Stage E1 E2 Read src...

Page 216: ... p 3 1 5 5 5 1 1 1 Opcode map field used For operand type Unit src1 src2 dst umsb16 xsmsb16 sint M1 M2 Description The unsigned operand src1 is multiplied by the signed operand src2 The result is placed in dst The S is needed in the mnemonic to specify a signed operand when both signed and unsigned operands are used Execution if cond msb16 src1 msb16 src2 dst else nop Pipeline Stage E1 E2 Read src...

Page 217: ...0 0 0 0 s p 3 1 5 5 5 1 5 1 1 Opcode map field used For operand type Unit Opfield src1 src2 dst sint xsint sint M1 M2 00100 src1 src2 dst cst5 xsint sint M1 M2 00110 Description The src1 operand is multiplied by the src2 operand The lower 32 bits of the result are placed in dst Execution if cond lsb32 src1 src2 dst else nop Pipeline Stage E1 E2 E3 E4 E5 E6 E7 E8 E9 Read src1 src2 src1 src2 src1 sr...

Page 218: ...truction Set SPRU733 Functional Unit Latency 4 See Also MPYID Example MPYI M1X A1 B2 A3 Before instruction 9 cycles after instruction A1 0034 5678h 3430008 A1 0034 5678h 3430008 B2 0011 2765h 1124197 B2 0011 2765h 1124197 A3 xxxx xxxxh A3 CBCA 6558h 875928232 ...

Page 219: ...p field used For operand type Unit Opfield src1 src2 dst sint xsint sdint M1 M2 01000 src1 src2 dst cst5 xsint sdint M1 M2 01100 Description The src1 operand is multiplied by the src2 operand The 64 bit result is placed in the dst register pair Execution if cond lsb32 src1 src2 dst_l msb32 src1 src2 dst_h else nop Pipeline Stage E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 Read src1 src2 src1 src2 src1 src2 src...

Page 220: ...733 Functional Unit Latency 4 See Also MPYI Example MPYID M1 A1 A2 A5 A4 Before instruction 10 cycles after instruction A1 0034 5678h 3430008 A1 0034 5678h 3430008 A2 0011 2765h 1124197 A2 0011 2765h 1124197 A5 A4 xxxx xxxxh xxxx xxxxh A5 A4 0000 0381h CBCA 6558h 3856004703576 ...

Page 221: ...rc2 src1 x 1 0 0 0 1 0 0 0 0 0 s p 3 1 5 5 5 1 1 1 Opcode map field used For operand type Unit src1 src2 dst slsb16 xsmsb16 sint M1 M2 Description The src1 operand is multiplied by the src2 operand The result is placed in dst The source operands are signed by default Execution if cond lsb16 src1 msb16 src2 dst else nop Pipeline Stage E1 E2 Read src1 src2 Written dst Unit in use M Instruction Type ...

Page 222: ...MSB 3 162 Instruction Set SPRU733 Example MPYLH M1 A1 A2 A3 Before instruction 2 cycles after instruction A1 0900 000Eh 14 A1 0900 000Eh A2 0029 00A7h 41 A2 0029 00A7h A3 xxxx xxxxh A3 0000 023Eh 574 Signed 16 LSB integer Signed 16 MSB integer ...

Page 223: ... z dst src2 src1 x 1 0 1 1 1 0 0 0 0 0 s p 3 1 5 5 5 1 1 1 Opcode map field used For operand type Unit src1 src2 dst ulsb16 xumsb16 uint M1 M2 Description The src1 operand is multiplied by the src2 operand The result is placed in dst The source operands are unsigned by default Execution if cond lsb16 src1 msb16 src2 dst else nop Pipeline Stage E1 E2 Read src1 src2 Written dst Unit in use M Instruc...

Page 224: ... p 3 1 5 5 5 1 1 1 Opcode map field used For operand type Unit src1 src2 dst slsb16 xumsb16 sint M1 M2 Description The signed operand src1 is multiplied by the unsigned operand src2 The result is placed in dst The S is needed in the mnemonic to specify a signed operand when both signed and unsigned operands are used Execution if cond lsb16 src1 msb16 src2 dst else nop Pipeline Stage E1 E2 Read src...

Page 225: ... p 3 1 5 5 5 1 1 1 Opcode map field used For operand type Unit src1 src2 dst ulsb16 xsmsb16 sint M1 M2 Description The unsigned operand src1 is multiplied by the signed operand src2 The result is placed in dst The S is needed in the mnemonic to specify a signed operand when both signed and unsigned operands are used Execution if cond lsb16 src1 msb16 src2 dst else nop Pipeline Stage E1 E2 Read src...

Page 226: ...a signed NaN_out If either source is SNaN the INVAL bit is set also The sign of NaN_out is the exclusive OR of the input signs 2 Signed infinity multiplied by signed infinity or a normalized number other than signed 0 returns signed infinity Signed infinity multiplied by signed 0 returns a signed NaN_out and sets the INVAL bit 3 If one or both sources are signed 0 the result is signed 0 unless the...

Page 227: ...ction the number of delay slots can be reduced by one because these instructions read the lower word of the DP source one cycle before the upper word of the DP source Instruction Type 4 cycle Delay Slots 3 Functional Unit Latency 1 See Also MPY MPYDP MPYSP2DP Example MPYSP M1X A1 B2 A3 Before instruction 4 cycles after instruction A1 C020 0000h 2 5 A1 C020 0000h 2 5 B2 4109 999Ah 8 6 B2 4109 999Ah...

Page 228: ...lse nop Notes 1 If one source is SNaN or QNaN the result is a signed NaN_out If either source is SNaN the INVAL bit is set also The sign of NaN_out is the exclusive OR of the input signs 2 Signed infinity multiplied by signed infinity or a normalized number other than signed 0 returns signed infinity Signed infinity multiplied by signed 0 returns a signed NaN_out and sets the INVAL bit 3 If one or...

Page 229: ... is written out one cycle earlier than the high half If dst is used as the source for the ADDDP CMPEQDP CMPLTDP CMPGTDP MPYDP MPYSPDP MPYSP2DP or SUBDP instruction the number of delay slots can be reduced by one because these instructions read the lower word of the DP source one cycle before the upper word of the DP source Instruction Type MPYSPDP Delay Slots 6 Functional Unit Latency 3 See Also M...

Page 230: ...p Notes 1 If one source is SNaN or QNaN the result is a signed NaN_out If either source is SNaN the INVAL bit is set also The sign of NaN_out is the exclusive OR of the input signs 2 Signed infinity multiplied by signed infinity or a normalized number other than signed 0 returns signed infinity Signed infinity multiplied by signed 0 returns a signed NaN_out and sets the INVAL bit 3 If one or both ...

Page 231: ...lt is written out one cycle earlier than the high half If dst is used as the source for the ADDDP CMPEQDP CMPLTDP CMPGTDP MPYDP MPYSPDP MPYSP2DP or SUBDP instruction the number of delay slots can be reduced by one because these instructions read the lower word of the DP source one cycle before the upper word of the DP source Instruction Type 5 cycle Delay Slots 4 Functional Unit Latency 2 See Also...

Page 232: ...pcode map field used For operand type Unit Opfield src1 src2 dst slsb16 xulsb16 sint M1 M2 11011 src1 src2 dst scst5 xulsb16 sint M1 M2 11110 Description The signed operand src1 is multiplied by the unsigned operand src2 The result is placed in dst The S is needed in the mnemonic to specify a signed operand when both signed and unsigned operands are used Execution if cond lsb16 src1 lsb16 src2 dst...

Page 233: ...d 16 LSB MPYSU 3 173 Instruction Set SPRU733 See Also MPY MPYU MPYUS Example MPYSU M1 13 A1 A2 Before instruction 2 cycles after instruction A1 3497 FFF3h 65523 A1 3497 FFF3h A2 xxxx xxxxh A2 000C FF57h 851779 Unsigned 16 LSB integer ...

Page 234: ... z dst src2 src1 x 1 1 1 1 1 0 0 0 0 0 s p 3 1 5 5 5 1 1 1 Opcode map field used For operand type Unit src1 src2 dst ulsb16 xulsb16 uint M1 M2 Description The src1 operand is multiplied by the src2 operand The result is placed in dst The source operands are unsigned by default Execution if cond lsb16 src1 lsb16 src2 dst else nop Pipeline Stage E1 E2 Read src1 src2 Written dst Unit in use M Instruc...

Page 235: ...16 LSB MPYU 3 175 Instruction Set SPRU733 Example MPYU M1 A1 A2 A3 Before instruction 2 cycles after instruction A1 0000 0123h 291 A1 0000 0123h A2 0F12 FA81h 64129 A2 0F12 FA81h A3 xxxx xxxxh A3 011C C0A3 18661539 Unsigned 16 LSB integer ...

Page 236: ... p 3 1 5 5 5 1 1 1 Opcode map field used For operand type Unit src1 src2 dst ulsb16 xslsb16 sint M1 M2 Description The unsigned operand src1 is multiplied by the signed operand src2 The result is placed in dst The S is needed in the mnemonic to specify a signed operand when both signed and unsigned operands are used Execution if cond lsb16 src1 lsb16 src2 dst else nop Pipeline Stage E1 E2 Read src...

Page 237: ...3 177 Instruction Set SPRU733 Example MPYUS M1 A1 A2 A3 Before instruction 2 cycles after instruction A1 1234 FFA1h 65441 A1 1234 FFA1h A2 1234 FFA1h 95 A2 1234 FFA1h A3 xxxx xxxxh A3 FFA1 2341h 6216895 Signed 16 LSB integer Unsigned 16 LSB integer ...

Page 238: ...27 23 22 18 17 13 12 11 5 4 3 2 1 0 creg z dst src2 0 0 0 0 0 x op 1 1 0 s p 3 1 5 5 1 7 1 1 Opcode map field used For operand type Unit Opfield src2 dst xsint sint L1 L2 000 0010 src2 dst slong slong L1 L2 010 0000 Opcode S unit 31 29 28 27 23 22 18 17 13 12 11 6 5 4 3 2 1 0 creg z dst src2 0 0 0 0 0 x 0 0 0 1 1 0 1 0 0 0 s p 3 1 5 5 1 1 1 Opcode map field used For operand type Unit src2 dst xsin...

Page 239: ... 0 0 0 1 0 0 1 0 1 0 0 0 0 s p 3 1 5 5 1 1 Opcode map field used For operand type Unit src2 dst sint sint D1 D2 Description The MV pseudo operation moves a value from one register to another The assembler uses the operation ADD unit 0 src2 dst to perform this task Execution if cond 0 src2 dst else nop Instruction Type Single cycle Delay Slots 0 ...

Page 240: ...00 1111 Description The src2 register is moved from the control register file to the register file Valid values for src2 are any register listed in the control register file Register addresses for accessing the control registers are in Table 3 21 page 3 182 Operands when moving from the register file to the control file Opcode map field used For operand type Unit Opfield src2 dst xuint uint S2 00 ...

Page 241: ...line Stage E1 Read src2 Written dst Unit in use S2 Instruction Type Single cycle Any write to the ISR or ICR by the MVC instruction effectively has one delay slot because the results cannot be read by the MVC instruction in the IFR until two cycles after the write to the ISR or ICR Delay Slots 0 Example MVC S2 B1 AMR Before instruction 1 cycle after instruction B1 F009 0001h B1 F009 0001h AMR 0000...

Page 242: ... W FAUCR Floating point auxiliary configuration 10011 R W FMCR Floating point multiplier configuration 10100 R W ICR Interrupt clear register 00011 W IER Interrupt enable register 00100 R W IFR Interrupt flag register 00010 R IRP Interrupt return pointer 00110 R W ISR Interrupt set register 00010 W ISTP Interrupt service table pointer 00101 R W NRP Nonmaskable interrupt return pointer 00111 R W PC...

Page 243: ...S1 S2 Description The 16 bit signed constant cst is sign extended and placed in dst In most cases the C6000 assembler and linker issue a warning or an error when a constant is outside the range supported by the instruction In the case of MVK S a warning is issued whenever the constant is outside the signed 16 bit range 32768 to 32767 or FFFF 8000h to 0000 7FFFh For example MVK S1 0x00008000X A0 wi...

Page 244: ...n Set SPRU733 Instruction Type Single cycle Delay Slots 0 See Also MVKH MVKL MVKLH Example 1 MVK L2 5 B8 Before instruction 1 cycle after instruction B8 xxxx xxxxh B8 FFFF FFFBh Example 2 MVK D2 14 B8 Before instruction 1 cycle after instruction B8 xxxx xxxxh B8 0000 000Eh ...

Page 245: ...pe Unit cst16 dst uscst16 sint S1 S2 Description The 16 bit constant cst16 is loaded into the upper 16 bits of dst The 16 LSBs of dst are unchanged For the MVKH instruction the assembler encodes the 16 MSBs of a 32 bit constant into the cst16 field of the opcode For theMVKLH instruction the assembler encodes the 16 LSBs of a constant into the cst16 field of the opcode Execution For the MVKLH instr...

Page 246: ...a warning for any constant over 16 bits To load 32 bit constants such as 1234 5678h use the following pair of instructions MVKL 0x12345678 MVKH 0x12345678 If you are loading the address of a label use MVKL label MVKH label Example 1 MVKH S1 0A329123h A1 Before instruction 1 cycle after instruction A1 0000 7634h A1 0A32 7634h Example 2 MVKLH S1 7A8h A1 Before instruction 1 cycle after instruction A...

Page 247: ...nds the 16 bit constant cst16 and places it in dst The MVKL instruction is equivalent to the MVK instruction page 3 183 except that the MVKL instruction disables the constant range checking normally performed by the assembler linker This allows the MVKL instruction to be paired with the MVKH instruction page 3 185 to generate 32 bit constants To load 32 bit constants such as 1234 ABCDh use the fol...

Page 248: ...ge E1 Read Written dst Unit in use S Instruction Type Single cycle Delay Slots 0 See Also MVK MVKH MVKLH Example 1 MVKL S1 5678h A8 Before instruction 1 cycle after instruction A8 xxxx xxxxh A8 0000 5678h Example 2 MVKL S1 0C678h A8 Before instruction 1 cycle after instruction A8 xxxx xxxxh A8 FFFF C678h Pipeline ...

Page 249: ...pe Unit src2 dst xsint sint S1 S2 Opcode L unit 31 29 28 27 23 22 18 17 13 12 11 5 4 3 2 1 0 creg z dst src2 0 0 0 0 0 x op 1 1 0 s p 3 1 5 5 1 7 1 1 Opcode map field used For operand type Unit Opfield src2 dst xsint sint L1 L2 000 0110 src2 dst slong slong L1 L2 010 0100 Description The NEG pseudo operation negates src2 and places the result in dst The assembler uses SUB unit 0 src2 dst to perfor...

Page 250: ...ycles no operation is performed The maximum value for count is 9 NOP with no operand is treated like NOP 1 with src encoded as 0000 A multicycle NOP will not finish if a branch is completed first For example if a branch is initiated on cycle n and a NOP 5 instruction is initiated on cycle n 3 the branch is complete on cycle n 6 and the NOP is executed only from cycle n 3 to cycle n 5 A single cycl...

Page 251: ...e NOP 1 cycle after NOP No operation executes 1 cycle after MVK A1 1234 5678h A1 1234 5678h A1 0000 0125h Example 2 MVK S1 1 A1 MVKLH S1 0 A1 NOP 5 ADD L1 A1 A2 A1 Before NOP 5 1 cycle after ADD instruction 6 cycles after NOP 5 A1 0000 0001h A1 0000 0004h A2 0000 0003h A2 0000 0003h ...

Page 252: ...1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 x 0 1 x x x x x x x x x x x x x x x x x x x x x x x x x x x x x In this case NORM returns 3 In this case NORM returns 30 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 In this case NORM returns 0 In this case NORM returns...

Page 253: ...en dst Unit in use L Instruction Type Single cycle Delay Slots 0 Example 1 NORM L1 A1 A2 Before instruction 1 cycle after instruction A1 02A3 469Fh A1 02A3 469Fh A2 xxxx xxxxh A2 0000 0005h 5 Example 2 NORM L1 A1 A2 Before instruction 1 cycle after instruction A1 FFFF F25Ah A1 FFFF F25Ah A2 xxxx xxxxh A2 0000 0013h 19 Pipeline ...

Page 254: ...erand type Unit src2 dst xuint uint L1 L2 Opcode S unit 31 29 28 27 23 22 18 17 13 12 11 6 5 4 3 2 1 0 creg z dst src2 1 1 1 1 1 x 0 0 1 0 1 0 1 0 0 0 s p 3 1 5 5 5 1 1 1 Opcode map field used For operand type Unit src2 dst xuint uint S1 S2 Description The NOT pseudo operation performs a bitwise NOT on the src2 operand and places the result in dst The assembler uses XOR unit 1 src2 dst to perform ...

Page 255: ...it Opfield src1 src2 dst uint xuint uint L1 L2 111 1111 src1 src2 dst scst5 xuint uint L1 L2 111 1110 Opcode S unit 31 29 28 27 23 22 18 17 13 12 11 6 5 4 3 2 1 0 creg z dst src2 src1 x op 1 0 0 0 s p 3 1 5 5 5 1 6 1 1 Opcode map field used For operand type Unit Opfield src1 src2 dst uint xuint uint S1 S2 01 1011 src1 src2 dst scst5 xuint uint S1 S2 01 1010 Description Performs a bitwise OR operat...

Page 256: ...S Instruction Type Single cycle Delay Slots 0 See Also AND XOR Example 1 OR S1 A3 A4 A5 Before instruction 1 cycle after instruction A3 08A3 A49Fh A3 08A3 A49Fh A4 00FF 375Ah A4 00FF 375Ah A5 xxxx xxxxh A5 08FF B7DFh Example 2 OR L2 12 B2 B8 Before instruction 1 cycle after instruction B2 0000 3A41h B2 0000 3A41h B8 xxxx xxxxh B8 FFFF FFF5h Pipeline ...

Page 257: ... the src1 port for the 32 LSBs and the src2 port for the 32 MSBs The RCPDP instruction provides the correct exponent and the mantissa is accurate to the eighth binary position therefore mantissa error is less than 2 8 This estimate can be used as a seed value for an algorithm to compute the reciprocal to greater accuracy The Newton Rhapson algorithm can further extend the mantissa s precision x n ...

Page 258: ...rflows signed 0 is placed in dst and the INEX and UNDER bits are set Underflow occurs when 21022 src2 infinity Pipeline Stage E1 E2 Read src2_l src2_h Written dst_l dst_h Unit in use S If dst is used as the source for the ADDDP CMPEQDP CMPLTDP CMPGTDP MPYDP or SUBDP instruction the number of delay slots can be reduced by one because these instructions read the lower word of the DP source one cycle...

Page 259: ...on value of src2 is placed in dst The RCPSP instruction provides the correct exponent and the mantissa is accurate to the eighth binary position therefore mantissa error is less than 2 8 This estimate can be used as a seed value for an algorithm to compute the reciprocal to greater accuracy The Newton Rhapson algorithm can further extend the mantissa s precision x n 1 x n 2 v x n where v the numbe...

Page 260: ...et 4 If src2 is signed 0 signed infinity is placed in dst and the DIV0 and INFO bits are set 5 If src2 is signed infinity signed 0 is placed in dst 6 If the result underflows signed 0 is placed in dst and the INEX and UNDER bits are set Underflow occurs when 2126 src2 infinity Pipeline Stage E1 Read src2 Written dst Unit in use S Instruction Type Single cycle Delay Slots 0 Functional Unit Latency ...

Page 261: ... the src1 port for the 32 LSBs and the src2 port for the 32 MSBs The RSQRDP instruction provides the correct exponent and the mantissa is accurate to the eighth binary position therefore mantissa error is less than 2 8 This estimate can be used as a seed value for an algorithm to compute the reciprocal square root to greater accuracy The Newton Rhapson algorithm can further extend the mantissa s p...

Page 262: ...proximation cannot be used to calculate the square root of 0 because infinity multiplied by 0 is invalid 6 If src2 is positive infinity positive 0 is placed in dst Pipeline Stage E1 E2 Read src2_l src2_h Written dst_l dst_h Unit in use S If dst is used as the source for the ADDDP CMPEQDP CMPLTDP CMPGTDP MPYDP or SUBDP instruction the number of delay slots can be reduced by one because these instru...

Page 263: ...ion value of src2 is placed in dst The RSQRSP instruction provides the correct exponent and the mantissa is accurate to the eighth binary position therefore mantissa error is less than 2 8 This estimate can be used as a seed value for an algorithm to compute the reciprocal square root to greater accuracy The Newton Rhapson algorithm can further extend the mantissa s precision x n 1 x n 1 5 v 2 x n...

Page 264: ...d 0 signed infinity is placed in dst and the DIV0 and INFO bits are set The Newton Rhapson approximation cannot be used to calculate the square root of 0 because infinity multiplied by 0 is invalid 6 If src2 is positive infinity positive 0 is placed in dst Pipeline Stage E1 Read src2 Written dst Unit in use S Instruction Type Single cycle Delay Slots 0 Functional Unit Latency 1 See Also RCPSP RSQR...

Page 265: ...2 011 0001 src1 src2 dst scst5 xsint sint L1 L2 001 0010 src1 src2 dst scst5 slong slong L1 L2 011 0000 Description src1 is added to src2 and saturated if an overflow occurs according to the following rules 1 If the dst is an int and src1 src2 231 1 then the result is 231 1 2 If the dst is an int and src1 src2 231 then the result is 231 3 If the dst is a long and src1 src2 239 1 then the result is...

Page 266: ...4995 A1 5A2E 51A3h A1 5A2E 51A3h A2 012A 3FA2h 19546018 A2 012A 3FA2h A2 012A 3FA2h A3 xxxx xxxxh A3 5B58 9145h 1532531013 A3 5B58 9145h CSR 0001 0100h CSR 0001 0100h CSR 0001 0100h Not saturated Example 2 SADD L1 A1 A2 A3 Before instruction 1 cycle after instruction 2 cycles after instruction A1 4367 71F2h 1130852850 A1 4367 71F2h A1 4367 71F2h A2 5A2E 51A3h 1512984995 A2 5A2E 51A3h A2 5A2E 51A3h...

Page 267: ... A5 A4 0000 0000h 7C83 39B1h 1922644401 A5 A4 0000 0000h 7C83 39B1h A7 A6 xxxx xxxxh xxxx xxxxh A7 A6 0000 0000h 8DAD 7953h 2376956243 B2 112A 3FA2h 287981474 B2 112A 3FA2h CSR 0001 0100h CSR 0001 0100h 2 cycles after instruction A5 A4 0000 0000h 7C83 39B1h A7 A6 0000 0000h 83C3 7953h B2 112A 3FA2h CSR 0001 0100h Not saturated Signed 40 bit long integer ...

Page 268: ...eld used For operand type Unit src2 dst slong sint L1 L2 Description A 40 bit src2 value is converted to a 32 bit value If the value in src2 is greater than what can be represented in 32 bits src2 is saturated The result is placed in dst If a saturate occurs the SAT bit in the control status register CSR is set one cycle after dst is written Execution if cond if src2 231 1 231 1 dst else if src2 2...

Page 269: ...Example 2 SAT L2 B1 B0 B5 Before instruction 1 cycle after instruction 2 cycles after instruction B1 B0 0000 0000h A190 7321h B1 B0 0000 0000h A190 7321h B1 B0 0000 0000h A190 7321h B5 xxxx xxxxh B5 7FFF FFFFh B5 7FFF FFFFh CSR 0001 0100h CSR 0001 0100h CSR 0001 0300h Saturated Example 3 SAT L2 B1 B0 B5 Before instruction 1 cycle after instruction 2 cycles after instruction B1 B0 0000 00FFh A190 7...

Page 270: ... 31 29 28 27 23 22 18 17 13 12 8 7 6 5 4 3 2 1 0 creg z dst src2 csta cstb 1 0 0 0 1 0 s p 3 1 5 5 5 5 1 1 Opcode map field used For operand type Unit src2 csta cstb dst uint ucst5 ucst5 uint S1 S2 Opcode Register form 31 29 28 27 23 22 18 17 13 12 11 6 5 4 3 2 1 0 creg z dst src2 src1 x 1 1 1 0 1 1 1 0 0 0 s p 3 1 5 5 5 1 1 1 Opcode map field used For operand type Unit src2 src1 dst xuint uint ui...

Page 271: ... example below csta is 15 and cstb is 23 Only the ten LSBs are valid for the register version of the instruction If any of the 22 MSBs are non zero the result is invalid src2 dst 0 x x x x x x x x x x x x x x x x x x x x x x x 1 1 1 1 1 0 0 0 x x x x x x x x x x x x x x x x x x x x x x x 1 1 1 1 1 1 1 1 1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 31 30 2...

Page 272: ... A0 7 21 A1 Before instruction 1 cycle after instruction A0 4B13 4A1Eh A0 4B13 4A1Eh A1 xxxx xxxxh A1 4B3F FF9Eh Example 2 SET S2 B0 B1 B2 Before instruction 1 cycle after instruction B0 9ED3 1A31h B0 9ED3 1A31h B1 0000 C197h B1 0000 C197h B2 xxxx xxxxh B2 9EFF FA31h ...

Page 273: ...01 src2 src1 dst xuint uint ulong S1 S2 01 0011 src2 src1 dst xsint ucst5 sint S1 S2 11 0010 src2 src1 dst slong ucst5 slong S1 S2 11 0000 src2 src1 dst xuint ucst5 ulong S1 S2 01 0010 Description The src2 operand is shifted to the left by the src1 operand The result is placed in dst When a register is used the six LSBs specify the shift amount and valid values are 0 40 When an immediate is used v...

Page 274: ...ction A0 29E3 D31Ch A0 29E3 D31Ch A1 xxxx xxxxh A1 9E3D 31C0h Example 2 SHL S2 B0 B1 B2 Before instruction 1 cycle after instruction B0 4197 51A5h B0 4197 51A5h B1 0000 0009h B1 0000 0009h B2 xxxx xxxxh B2 2EA3 4A00h Example 3 SHL S2 B1 B0 B2 B3 B2 Before instruction 1 cycle after instruction B1 B0 0000 0009h 4197 51A5h B1 B0 0000 0009h 4197 51A5h B2 0000 0022h B2 0000 0000h B3 B2 xxxx xxxxh xxxx ...

Page 275: ...1 dst slong uint slong S1 S2 11 0101 src2 src1 dst xsint ucst5 sint S1 S2 11 0110 src2 src1 dst slong ucst5 slong S1 S2 11 0100 Description The src2 operand is shifted to the right by the src1 operand The sign extended result is placed in dst When a register is used the six LSBs specify the shift amount and valid values are 0 40 When an immediate value is used valid shift amounts are 0 31 If 39 sr...

Page 276: ...uction A0 F123 63D1h A0 F123 63D1h A1 xxxx xxxxh A1 FFF1 2363h Example 2 SHR S2 B0 B1 B2 Before instruction 1 cycle after instruction B0 1492 5A41h B0 1492 5A41h B1 0000 0012h B1 0000 0012h B2 xxxx xxxxh B2 0000 0524h Example 3 SHR S2 B1 B0 B2 B3 B2 Before instruction 1 cycle after instruction B1 B0 0000 0012h 1492 5A41h B1 B0 0000 0012h 1492 5A41h B2 0000 0019h B2 0000 090Ah B3 B2 xxxx xxxxh xxxx...

Page 277: ... dst ulong uint ulong S1 S2 10 0101 src2 src1 dst xuint ucst5 uint S1 S2 10 0110 src2 src1 dst ulong ucst5 ulong S1 S2 10 0100 Description The src2 operand is shifted to the right by the src1 operand The zero extended result is placed in dst When a register is used the six LSBs specify the shift amount and valid values are 0 40 When an immediate value is used valid shift amounts are 0 31 If 39 src...

Page 278: ...3 Pipeline Stage E1 Read src1 src2 Written dst Unit in use S Instruction Type Single cycle Delay Slots 0 See Also SHL SHR Example SHRU S1 A0 8 A1 Before instruction 1 cycle after instruction A0 F123 63D1h A0 F123 63D1h A1 xxxx xxxxh A1 00F1 2363h Pipeline ...

Page 279: ...rand type Unit src1 src2 dst slsb16 xslsb16 sint M1 M2 Description The src1 operand is multiplied by the src2 operand The result is left shifted by 1 and placed in dst If the left shifted result is 8000 0000h then the result is saturated to 7FFF FFFFh If a saturate occurs the SAT bit in CSR is set one cycle after dst is written The source operands are signed by default Execution if cond if src1 sr...

Page 280: ...ation 3 220 Instruction Set SPRU733 Example SMPY M1 A1 A2 A3 Before instruction 2 cycle after instruction A1 0000 0123h 291 A1 0000 0123h A2 01E0 FA81h 1407 A2 01E0 FA81h A3 xxxx xxxxh A3 FFF3 8146h 818874 CSR 0001 0100h CSR 0001 0100h Not saturated Signed 16 LSB integer ...

Page 281: ...erand type Unit src1 src2 dst smsb16 xsmsb16 sint M1 M2 Description The src1 operand is multiplied by the src2 operand The result is left shifted by 1 and placed in dst If the left shifted result is 8000 0000h then the result is saturated to 7FFF FFFFh If a saturation occurs the SAT bit in CSR is set one cycle after dst is written The source operands are signed by default Execution if cond if src1...

Page 282: ... map field used For operand type Unit src1 src2 dst smsb16 xslsb16 sint M1 M2 Description The src1 operand is multiplied by the src2 operand The result is left shifted by 1 and placed in dst If the left shifted result is 8000 0000h then the result is saturated to 7FFF FFFFh If a saturation occurs the SAT bit in CSR is set one cycle after dst is written Execution if cond if src1 src2 1 8000 0000h s...

Page 283: ... Instruction Set SPRU733 Example SMPYHL M1 A1 A2 A3 Before instruction 2 cycles after instruction A1 008A 0000h 138 A1 008A 0000h A2 0000 00A7h 167 A2 0000 00A7h A3 xxxx xxxxh A3 0000 B40Ch 46092 CSR 0001 0100h CSR 0001 0100h Not saturated Signed 16 MSB integer Signed 16 LSB integer ...

Page 284: ... map field used For operand type Unit src1 src2 dst slsb16 xsmsb16 sint M1 M2 Description The src1 operand is multiplied by the src2 operand The result is left shifted by 1 and placed in dst If the left shifted result is 8000 0000h then the result is saturated to 7FFF FFFFh If a saturation occurs the SAT bit in CSR is set one cycle after dst is written Execution if cond if src1 src2 1 8000 0000h s...

Page 285: ...nstruction Set SPRU733 Example SMPYLH M1 A1 A2 A3 Before instruction 2 cycles after instruction A1 0000 8000h 32768 A1 0000 8000h A2 8000 0000h 32768 A2 8000 0000h A3 xxxx xxxxh A3 7FFF FFFFh 2147483647 CSR 0001 0100h CSR 0001 0300h Saturated Signed 16 MSB integer Signed 16 LSB integer ...

Page 286: ...1 0 1 0 0 0 s p 3 1 5 5 1 1 1 Opcode map field used For operand type Unit src2 dst xsp dp S1 S2 Description The single precision value in src2 is converted to a double precision value and placed in dst Execution if cond dp src2 dst else nop Notes 1 If src2 is SNaN NaN_out is placed in dst and the INVAL and NAN2 bits are set 2 If src2 is QNaN NaN_out is placed in dst and the NAN2 bit is set 3 If sr...

Page 287: ... or SUBDP instruction the number of delay slots can be reduced by one because these instructions read the lower word of the DP source one cycle before the upper word of the DP source Instruction Type 2 cycle DP Delay Slots 1 Functional Unit Latency 1 See Also DPSP INTDP SPINT SPTRUNC Example SPDP S1X B2 A1 A0 Before instruction 2 cycles after instruction B2 4109 999Ah 8 6 B2 4109 999Ah 8 6 A1 A0 x...

Page 288: ...nt L1 L2 Description The single precision value in src2 is converted to an integer and placed in dst Execution if cond int src2 dst else nop Notes 1 If src2 is NaN the maximum signed integer 7FFF FFFFh or 8000 0000h is placed in dst and the INVAL bit is set 2 If src2 is signed infinity or if overflow occurs the maximum signed integer 7FFF FFFFh or 8000 0000h is placed in dst and the INEX and OVER ...

Page 289: ...ne Stage E1 E2 E3 E4 Read src2 Written dst Unit in use L Instruction Type 4 cycle Delay Slots 3 Functional Unit Latency 1 See Also DPINT INTSP SPDP SPTRUNC Example SPINT L1 A1 A2 Before instruction 4 cycles after instruction A1 4109 9999Ah 8 6 A1 4109 999Ah 8 6 A2 xxxx xxxxh A2 0000 0009h 9 Pipeline ...

Page 290: ... src2 is converted to an integer and placed in dst This instruction operates like SPINT except that the rounding modes in the FADCR are ignored and round toward zero truncate is always used Execution if cond int src2 dst else nop Notes 1 If src2 is NaN the maximum signed integer 7FFF FFFFh or 8000 0000h is placed in dst and the INVAL bit is set 2 If src2 is signed infinity or if overflow occurs th...

Page 291: ...U733 Pipeline Stage E1 E2 E3 E4 Read src2 Written dst Unit in use L Instruction Type 4 cycle Delay Slots 3 Functional Unit Latency 1 See Also DPTRUNC SPDP SPINT Example SPTRUNC L1X B1 A2 Before instruction 4 cycles after instruction B1 4109 9999Ah 8 6 B1 4109 999Ah 8 6 A2 xxxx xxxxh A2 0000 0008h 8 Pipeline ...

Page 292: ...0 0010 Description The src2 operand is shifted to the left by the src1 operand The result is placed in dst When a register is used to specify the shift the five least significant bits specify the shift amount Valid values are 0 through 31 and the result of the shift is invalid if the shift amount is greater than 31 The result of the shift is saturated to 32 bits If a saturate occurs the SAT bit in...

Page 293: ...cycles after instruction A0 02E3 031Ch A0 02E3 031Ch A0 02E3 031Ch A1 xxxx xxxxh A1 0B8C 0C70h A1 0B8C 0C70h CSR 0001 0100h CSR 0001 0100h CSR 0001 0100h Not saturated Example 2 SSHL S1 A0 A1 A2 Before instruction 1 cycle after instruction 2 cycles after instruction A0 4719 1925h A0 4719 1925h A0 4719 1925h A1 0000 0006h A1 0000 0006h A1 0000 0006h A2 xxxx xxxxh A2 7FFF FFFFh A2 7FFF FFFFh CSR 000...

Page 294: ...sint L1 L2 001 1111 src1 src2 dst scst5 xsint sint L1 L2 000 1110 src1 src2 dst scst5 slong slong L1 L2 010 1100 Description src2 is subtracted from src1 and is saturated to the result size according to the following rules 1 If the result is an int and src1 src2 231 1 then the result is 231 1 2 If the result is an int and src1 src2 231 then the result is 231 3 If the result is a long and src1 src2...

Page 295: ...995 B1 5A2E 51A3h B1 5A2E 51A3h B2 802A 3FA2h 2144714846 B2 802A 3FA2h B2 802A 3FA2h B3 xxxx xxxxh B3 7FFF FFFFh 2147483647 B3 7FFF FFFFh CSR 0001 0100h CSR 0001 0100h CSR 0001 0300h Saturated Example 2 SSUB L1 A0 A1 A2 Before instruction 1 cycle after instruction 2 cycles after instruction A0 4367 71F2h 1130852850 A0 4367 71F2h A0 4367 71F2h A1 5A2E 51A3h 1512984995 A1 5A2E 51A3h A1 5A2E 51A3h A2...

Page 296: ...ter file used y 0 selects the D1 unit and baseR and offsetR from the A register file and y 1 selects the D2 unit and baseR and offsetR from the B register file offsetR ucst5 is scaled by a left shift of 0 bits After scaling offsetR ucst5 is added to or subtracted from baseR For the preincrement predecrement positive offset and negative offset address generator options the result of the calculation...

Page 297: ...et a nonscaled constant offset You must type either brackets or parentheses around the specified offset if you use the optional offset parameter Execution if cond src mem else nop Pipeline Stage E1 Read baseR offsetR src Written baseR Unit in use D2 Instruction Type Store Delay Slots 0 For more information on delay slots for a store see Chapter 4 See Also STH STW Example STB D1 A1 A10 Before instr...

Page 298: ...itude This instruction executes only on the D2 unit The offset ucst15 is scaled by a left shift of 0 bits After scaling ucst15 is added to baseR The result of the calculation is the address that is sent to memory The addressing arithmetic is always performed in linear mode For STB the 8 LSBs of the src register are stored src can be in either register file The s bit determines which file src is re...

Page 299: ...4 B15 src Written Unit in use D2 Instruction Type Store Delay Slots 0 See Also STH STW Example STB D2 B1 B14 40 Before instruction 1 cycle after instruction 3 cycles after instruction B1 1234 5678h B1 1234 5678h B1 1234 5678h B14 0000 1000h B14 0000 1000h B14 0000 1000h mem 1028h 42h mem 1028h 42h mem 1028h 78h Pipeline ...

Page 300: ... register file used y 0 selects the D1 unit and baseR and offsetR from the A register file and y 1 selects the D2 unit and baseR and offsetR from the B register file offsetR ucst5 is scaled by a left shift of 1 bit After scaling offsetR ucst5 is added to or subtracted from baseR For the preincrement predecrement positive offset and negative offset address generator options the result of the calcul...

Page 301: ...st type either brackets or parentheses around the specified offset if you use the optional offset parameter Halfword addresses must be aligned on halfword LSB is 0 boundaries Execution if cond src mem else nop Pipeline Stage E1 Read baseR offsetR src Written baseR Unit in use D2 Instruction Type Store Delay Slots 0 For more information on delay slots for a store see Chapter 4 See Also STB STW Exam...

Page 302: ...Example 2 STH D1 A1 A10 A11 Before instruction 1 cycle after instruction 3 cycles after instruction A1 9A32 2634h A1 9A32 2634h A1 9A32 2634h A10 0000 0100h A10 0000 00F8h A10 0000 00F8h A11 0000 0004h A11 0000 0004h A11 0000 0004h mem F8h 0000h mem F8h 0000h mem F8h 0000h mem 100h 0000 mem 100h 0000h mem 100h 2634h ...

Page 303: ...utes only on the D2 unit The offset ucst15 is scaled by a left shift of 1 bit After scaling ucst15 is added to baseR The result of the calculation is the address that is sent to memory The addressing arithmetic is always performed in linear mode For STH the 16 LSBs of the src register are stored src can be in either register file The s bit determines which file src is read from s 0 indicates src i...

Page 304: ...e Halfword to Memory With a 15 Bit Unsigned Constant Offset 3 244 Instruction Set SPRU733 Pipeline Stage E1 Read B14 B15 src Written Unit in use D2 Instruction Type Store Delay Slots 0 See Also STB STW Pipeline ...

Page 305: ...ile used y 0 selects the D1 unit and baseR and offsetR from the A register file and y 1 selects the D2 unit and baseR and offsetR from the B register file offsetR ucst5 is scaled by a left shift of 2 bits After scaling offsetR ucst5 is added to or subtracted from baseR For the preincrement predecrement positive offset and negative offset address generator options the result of the calculation is t...

Page 306: ...set of 12 words or 48 bytes You must type either brackets or parentheses around the specified offset if you use the optional offset parameter Word addresses must be aligned on word two LSBs are 0 boundaries Execution if cond src mem else nop Pipeline Stage E1 Read baseR offsetR src Written baseR Unit in use D2 Instruction Type Store Delay Slots 0 For more information on delay slots for a store see...

Page 307: ...r scaling ucst15 is added to baseR The result of the calculation is the address that is sent to memory The addressing arithmetic is always performed in linear mode For STW the entire 32 bits of the src register are stored src can be in either register file The s bit determines which file src is read from s 0 indicates src is in the A register file and s 1 indicates src is in the B register file Sq...

Page 308: ...ore Word to Memory With a 15 Bit Unsigned Constant Offset 3 248 Instruction Set SPRU733 Pipeline Stage E1 Read B14 B15 src Written Unit in use D2 Instruction Type Store Delay Slots 0 See Also STB STH Pipeline ...

Page 309: ...67x CPU Opcode L unit 31 29 28 27 23 22 18 17 13 12 11 5 4 3 2 1 0 creg z dst src2 src1 x op 1 1 0 s p 3 1 5 5 5 1 7 1 1 Opcode map field used For operand type Unit Opfield src1 src2 dst sint xsint sint L1 L2 000 0111 src1 src2 dst xsint sint sint L1 L2 001 0111 src1 src2 dst sint xsint slong L1 L2 010 0111 src1 src2 dst xsint sint slong L1 L2 011 0111 src1 src2 dst scst5 xsint sint L1 L2 000 0110...

Page 310: ...t src2 src1 x op 1 0 0 0 s p 3 1 5 5 5 1 6 1 1 Opcode map field used For operand type Unit Opfield src1 src2 dst sint xsint sint S1 S2 01 0111 src1 src2 dst scst5 xsint sint S1 S2 01 0110 Description for L1 L2 and S1 S2 Opcodes src2 is subtracted from src1 The result is placed in dst Execution for L1 L2 and S1 S2 Opcodes if cond src1 src2 dst else nop ...

Page 311: ...rc2 The result is placed in dst Execution for D1 D2 Opcodes if cond src2 src1 dst else nop Note Subtraction with a signed constant on the L and S units allows either the first or the second operand to be the signed 5 bit constant SUB unit src1 scst5 dst is encoded as ADD unit scst5 src2 dst where the src1 register is now src2 and scst5 is now scst5 However the D unit provides only the second opera...

Page 312: ... Set SPRU733 Instruction Type Single cycle Delay Slots 0 See Also ADD SSUB SUBC SUBDP SUBSP SUBU SUB2 Example SUB L1 A1 A2 A3 Before instruction 1 cycle after instruction A1 0000 325Ah 12810 A1 0000 325Ah A2 FFFF FF12h 238 A2 FFFF FF12h A3 xxxx xxxxh A3 0000 3348h 13128 ...

Page 313: ...1 dst sint sint sint D1 D2 11 0001 src2 src1 dst sint ucst5 sint D1 D2 11 0011 Description src1 is subtracted from src2 using the byte addressing mode specified for src2 The subtraction defaults to linear mode However if src2 is one of A4 A7 or B4 B7 the mode can be changed to circular mode by writing the appropriate value to the AMR see section 2 7 3 page 2 10 The result is placed in dst Executio...

Page 314: ... 3 254 Instruction Set SPRU733 Example SUBAB D1 A5 A0 A5 Before instruction 1 cycle after instruction A0 0000 0004h A0 0000 0004h A5 0000 4000h A5 0000 400Ch AMR 0003 0004h AMR 0003 0004h BK0 3 size 16 A5 in circular addressing mode using BK0 ...

Page 315: ...int sint D1 D2 11 0101 src2 src1 dst sint ucst5 sint D1 D2 11 0111 Description src1 is subtracted from src2 using the halfword addressing mode specified for src2 The subtraction defaults to linear mode However if src2 is one of A4 A7 or B4 B7 the mode can be changed to circular mode by writing the appropri ate value to the AMR see section 2 7 3 page 2 10 src1 is left shifted by 1 The result is pla...

Page 316: ...t sint D1 D2 11 1001 src2 src1 dst sint ucst5 sint D1 D2 11 1011 Description src1 is subtracted from src2 using the word addressing mode specified for src2 The subtraction defaults to linear mode However if src2 is one of A4 A7 or B4 B7 the mode can be changed to circular mode by writing the appropri ate value to the AMR see section 2 7 3 page 2 10 src1 is left shifted by 2 The result is placed in...

Page 317: ...W 3 257 Instruction Set SPRU733 Example SUBAW D1 A5 2 A3 Before instruction 1 cycle after instruction A3 xxxx xxxxh A3 0000 0108h A5 0000 0100h A5 0000 0100h AMR 0003 0004h AMR 0003 0004h BK0 3 size 16 A5 in circular addressing mode using BK0 ...

Page 318: ...pcode map field used For operand type Unit src1 src2 dst uint xuint uint L1 L2 Description Subtract src2 from src1 If result is greater than or equal to 0 left shift result by 1 add 1 to it and place it in dst If result is less than 0 left shift src1 by 1 and place it in dst This step is commonly used in division Execution if cond if src1 src2 0 src1 src2 1 1 dst else src1 1 dst else nop Pipeline ...

Page 319: ...ample 1 SUBC L1 A0 A1 A0 Before instruction 1 cycle after instruction A0 0000 125Ah 4698 A0 0000 024B4h 9396 A1 0000 1F12h 7954 A1 0000 1F12h Example 2 SUBC L1 A0 A1 A0 Before instruction 1 cycle after instruction A0 0002 1A31h 137777 A0 0000 47E5h 18405 A1 0001 F63Fh 128575 A1 0001 F63Fh ...

Page 320: ...c1 src2 dst dp xdp dp L1 L2 001 1001 src1 src2 dst xdp dp dp L1 L2 001 1101 src1 src2 dst dp xdp dp S1 S2 111 0011 src1 src2 dst dp xdp dp S1 S2 111 0111 src2 src1 Note The assembly syntax allows a cross path operand to be used for either src1 or src2 The assembler selects between the two opcodes based on which source operand in the assembly instruction requires the cross path If src1 requires the...

Page 321: ...ult is signed infinity and the INFO bit is set 7 If overflow occurs the INEX and OVER bits are set and the results are set as follows LFPN is the largest floating point number Overflow Output Rounding Mode Result Sign Nearest Even Zero Infinity Infinity infinity LFPN infinity LFPN infinity LFPN LFPN infinity 8 If underflow occurs the INEX and UNDER bits are set and the results are set as follows S...

Page 322: ...e result is written out one cycle earlier than the high half If dst is used as the source for the ADDDP CMPEQDP CMPLTDP CMPGTDP MPYDP MPYSPDP MPYSP2DP or SUBDP instruction the number of delay slots can be reduced by one because these instructions read the lower word of the DP source one cycle before the upper word of the DP source Instruction Type ADDDP SUBDP Delay Slots 6 Functional Unit Latency ...

Page 323: ...c1 src2 dst sp xsp sp L1 L2 001 0001 src1 src2 dst xsp sp sp L1 L2 001 0101 src1 src2 dst sp xsp sp S1 S2 111 0001 src1 src2 dst sp xsp sp S1 S2 111 0101 src2 src1 Note The assembly syntax allows a cross path operand to be used for either src1 or src2 The assembler selects between the two opcodes based on which source operand in the assembly instruction requires the cross path If src1 requires the...

Page 324: ...ult is signed infinity and the INFO bit is set 7 If overflow occurs the INEX and OVER bits are set and the results are set as follows LFPN is the largest floating point number Overflow Output Rounding Mode Result Sign Nearest Even Zero Infinity Infinity infinity LFPN infinity LFPN infinity LFPN LFPN infinity 8 If underflow occurs the INEX and UNDER bits are set and the results are set as follows S...

Page 325: ... Read src1 src2 Written dst Unit in use L Instruction Type 4 cycle Delay Slots 3 Functional Unit Latency 1 See Also ADDSP SUB SUBDP SUBU Example SUBSP L1X A2 B1 A3 Before instruction 4 cycles after instruction A2 4109 999Ah A2 4109 999Ah 8 6 B1 C020 0000h B1 C020 0000h 2 5 A3 XXXX XXXXh A3 4131 999Ah 11 1 Pipeline ...

Page 326: ...3 2 1 0 creg z dst src2 src1 x op 1 1 0 s p 3 1 5 5 5 1 7 1 1 Opcode map field used For operand type Unit Opfield src1 src2 dst uint xuint ulong L1 L2 010 1111 src1 src2 dst xuint uint ulong L1 L2 011 1111 Description src2 is subtracted from src1 The result is placed in dst Execution if cond src1 src2 dst else nop Pipeline Stage E1 Read src1 src2 Written dst Unit in use L Instruction Type Single c...

Page 327: ...Set SPRU733 Example SUBU L1 A1 A2 A5 A4 Before instruction 1 cycle after instruction A1 0000 325Ah 12810 A1 0000 325Ah A2 FFFF FF12h 4294967058 A2 FFFF FF12h A5 A4 xxxx xxxxh xxxx xxxxh A5 A4 0000 00FFh 0000 3348h 4294954168 Unsigned 32 bit integer Signed 40 bit long integer ...

Page 328: ...field used For operand type Unit src1 src2 dst sint xsint sint S1 S2 Description The upper and lower halves of src2 are subtracted from the upper and lower halves of src1 and the result is placed in dst Any borrow from the lower half subtraction does not affect the upper half subtraction Specifically the upper half of src2 is subtracted from the upper half of src1 and placed in the upper half of d...

Page 329: ...y Slots 0 See Also ADD2 SSUB SUB SUBC SUBU Example 1 SUB2 S1 A3 A4 A5 Before instruction 1 cycle after instruction A3 1105 6E30h 4357 28208 A3 1105 6E30h 4357 28208 A4 1105 6980h 4357 27008 A4 1105 6980h 4357 27008 A5 xxxx xxxxh A5 0000 04B0h 0 1200 Example 2 SUB2 S2X B1 A0 B2 Before instruction 1 cycle after instruction A0 0021 3271h 33 12913 A0 0021 3271h B1 003A 1B48h 58 6984 B1 003A 1B48h B2 x...

Page 330: ...pe Unit Opfield src1 src2 dst uint xuint uint L1 L2 110 1111 src1 src2 dst scst5 xuint uint L1 L2 110 1110 Opcode S unit 31 29 28 27 23 22 18 17 13 12 11 6 5 4 3 2 1 0 creg z dst src2 src1 x op 1 0 0 0 s p 3 1 5 5 5 1 6 1 1 Opcode map field used For operand type Unit Opfield src1 src2 dst uint xuint uint S1 S2 00 1011 src1 src2 dst scst5 xuint uint S1 S2 00 1010 Description Performs a bitwise excl...

Page 331: ...L or S Instruction Type Single cycle Delay Slots 0 See Also AND OR Example 1 XOR S1 A3 A4 A5 Before instruction 1 cycle after instruction A3 0721 325Ah A3 0721 325Ah A4 0019 0F12h A4 0019 0F12h A5 xxxx xxxxh A5 0738 3D48h Example 2 XOR L2 B1 0dh B8 Before instruction 1 cycle after instruction B1 0000 1023h B1 0000 1023h B8 xxxx xxxxh B8 0000 102Eh Pipeline ...

Page 332: ... L1 L2 011 0111 dst sint D1 D2 01 0001 dst sint S1 S2 01 0111 Description The ZERO pseudo operation fills the dst register with 0s by subtracting the dst from itself and placing the result in the dst In the case where dst is sint the assembler uses the MVK unit 0 dst instruction In the case where dst is slong the assembler uses the SUB unit src1 src2 dst instruction Execution if cond dst dst dst e...

Page 333: ...tore addresses appear on the CPU boundary during the same pipeline phase eliminating read after write memory conflicts All instructions require the same number of pipeline phases for fetch and decode but require a varying number of execute phases This chapter contains a description of the number of execution phases for each type of instruction Finally the chapter contains performance consideration...

Page 334: ...PR Program fetch packet receive The C67x DSP uses a fetch packet FP of eight instructions All eight of the instructions proceed through fetch processing together through the PG PS PW and PR phases Figure 4 2 a shows the fetch phases in sequential order from left to right Figure 4 2 b is a functional diagram of the flow of instructions through the fetch phases During the PG phase the program addres...

Page 335: ... 2 Decode The decode phases of the pipeline are DP Instruction dispatch DC Instruction decode In the DP phase of the pipeline the fetch packets are split into execute pack ets Execute packets consist of one instruction or from two to eight parallel instructions During the DP phase the instructions in an execute packet are assigned to the appropriate functional units In the DC phase the the source ...

Page 336: ...cle The NOP instruction in the eighth slot of the FP is not dispatched to a functional unit because there is no execution associated with it The first two slots of the fetch packet shaded below represent an execute packet of two parallel instructions that were dispatched on the previous cycle This execute packet contains two MPY instructions that are now in decode DC one cycle before execution The...

Page 337: ...peline is described in section 4 2 Pipeline Execution of Instruction Types Figure 4 4 a shows the execute phases of the pipeline in sequential order from left to right Figure 4 4 b shows the portion of the functional block diagram in which execution occurs Figure 4 4 Execute Phases of the Pipeline E4 E3 E2 E1 E5 a b Register file A Register file B Data 2 Data 1 32 32 32 32 byte addressable Interna...

Page 338: ... code flowing through the pipeline Table 4 1 summarizes the pipeline phases and what happens in each phase Figure 4 6 Pipeline Operation One Execute Packet per Fetch Packet Clock cycle Fetch packet 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ÁÁÁÁ ÁÁÁÁ n PG PS PW PR DP DC E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 ÁÁÁÁ n 1 ÁÁ PG PS PW PR DP DC E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 ÁÁÁÁ ÁÁÁÁ n 2 ÁÁ ÁÁ ÁÁÁ ÁÁÁPG PS PW PR...

Page 339: ...onal units Execute Execute 1 E1 For all instruction types the conditions for the instructions are evaluated and operands are read For load and store instructions address generation is performed and address modifications are written to the register file For branch instructions branch fetch packet in PG phase is affected For single cycle instructions results are written to a register file For DP com...

Page 340: ... instruction the src1 and the upper 32 bits of src2 are read Multiply 2 cycle DP DP compare Execute 3 E3 Data memory accesses are performed Any multiply instruction that saturates results sets the SAT bit in the CSR if saturation occurs For MPYDP instruction the upper 32 bits of src1 and the lower 32 bits of src2 are read For MPYI and MPYID instructions the sources are read Store Execute 4 E4 For ...

Page 341: ...s of the result are written to a register file MPYDP MPYID This assumes that the conditions for the instructions are evaluated as true If the condition is evaluated as false the instruction does not write an y results or have any pipeline operation after E1 Figure 4 7 shows a functional block diagram of the pipeline stages The pipe line operation is based on CPU cycles A CPU cycle is the period du...

Page 342: ...K CMPLTSP ABSSP B ADDSP SUBSP SUB ZERO LDDW LDDW ABSSP CMPLTSP ADDSP MV LDDW B MPYSP SUBSP LDDW Register file A Register file B Data 2 Data 1 32 32 32 32 byte addressable Internal data memory Data address 2 Data address 1 9 8 7 6 5 4 3 2 1 0 16 16 16 16 Data memory interface control DC MPYSP ADDSP LDDW MPYSP 32 E1 L1 ADDSP S1 ABSSP D1 M1 MPYSP 0 1 3 5 4 2 6 8 7 10 12 11 9 14 15 13 0 1 2 3 4 5 6 7 ...

Page 343: ...2 B5 B13 B11 ABSSP S1 A12 A15 LDDW D1 A0 5 A7 A6 DC Phase ADDSP L1 A12 A11 A12 ADDSP L2 B10 B11 B12 MPYSP M1X A4 B6 A9 MPYSP M2X A7 B6 B9 CMPLTSP S1 A15 A8 A1 ABSSP S2 B12 B15 LOOP B2 LDDW D1 A0 2 A5 A4 DP and PS Phases B2 ZERO D2 B0 SUBSP L1 A12 A2 A12 ADDSP L2 B9 B12 B12 MPYSP M1X A5 B7 A10 MPYSP M2 B4 B7 B10 B0 B S1 LOOP B1 CMPLTSP S2 B15 B8 B1 B2 LDDW D1 A0 4 B5 B4 PR and PG Phases B0 SUB D2 B...

Page 344: ...ngle Cycle 16 y 16 Multiply Store Load Branch E1 Compute result and write to register Read operands and start computations Compute address Compute address Target code in PG E2 Compute result and write to register Send address and data to memory Send address to memory E3 Access memory Access memory E4 Send data back to CPU E5 Write data into register E6 E7 E8 E9 E10 Delay slots 0 1 0 4 5 Functional...

Page 345: ...ntinue computation Read upper sources finish computation and write results to register E3 Continue computation Continue computation E4 Complete computation and write results to register Continue computation and write lower results to register E5 Complete computation and write upper results to register E6 E7 E8 E9 E10 Delay slots 1 3 4 1 Functional unit latency 1 1 1 2 Notes 1 This table assumes th...

Page 346: ...ontinue computation E5 Continue computation Continue computation Continue computation Continue computation E6 Compute the lower results and write to register Continue computation Continue computation Continue computation E7 Compute the upper results and write to register Continue computation Continue computation Continue computation E8 Continue computation Continue computation Continue computation...

Page 347: ...ue computation Continue computation and write lower results to register E5 Continue computation Complete computa tion and write upper results to register E6 Continue computation and write lower results to register E7 Complete computa tion and write upper results to register E8 E9 E10 Delay slots 6 4 Functional unit latency 3 2 Notes 1 This table assumes that the condition for each instruction is e...

Page 348: ...le execution diagram The operands are read the operation is performed and the results are written to a register all during E1 Single cycle instructions have no delay slots Table 4 3 Single Cycle Instruction Execution Pipeline Stage E1 Read src1 src2 Written dst Unit in use L S M or D Figure 4 8 Single Cycle Instruction Phases PG PS PW PR DP DC E1 Figure 4 9 Single Cycle Instruction Execution Block...

Page 349: ...e pipeline for a multiply In the E1 phase the operands are read and the multiply begins In the E2 phase the multiply finishes and the result is written to the destination register Multiply instructions have one delay slot Table 4 4 16 16 Bit Multiply Instruction Execution Pipeline Stage E1 E2 Read src1 src2 Written dst Unit in use M Figure 4 10 Multiply Instruction Phases PG PS PW PR DP DC E1 E2 1...

Page 350: ...ess of the data to be stored is computed In the E2 phase the data and destination addresses are sent to data memory In the E3 phase a memory write is performed The address modification is performed in the E1 stage of the pipeline Even though stores finish their execution in the E3 phase of the pipeline they have no delay slots There is additional explanation of why stores have zero delay slots in ...

Page 351: ... a store to the same memory location these rules apply i cycle When a load is executed before a store the old value is loaded and the new value is stored i LDW i 1 STW When a store is executed before a load the new value is stored and the new value is loaded i STW i 1 LDW When the instructions are executed in parallel the old value is loaded first and then the new value is stored but both occur in...

Page 352: ... use Figure 4 15 shows the operations occurring in the pipeline phases for a load In the E1 phase the data address pointer is modified in its register In the E2 phase the data address is sent to data memory In the E3 phase a memory read at that address is performed Table 4 6 Load Instruction Execution Pipeline Stage E1 E2 E3 E4 E5 Read baseR offsetR Written baseR dst Unit in use D Figure 4 14 Load...

Page 353: ...ts Because pointer results are written to the register in E1 there are no delay slots associated with the address modification In the following code pointer results are written to the A4 register in the first execute phase of the pipeline and data is written to the A3 register in the fifth execute phase LDW D1 A4 A3 Because a store takes three execute phases to write a value to memory and a load t...

Page 354: ...tion execution block diagram If a branch is in the E1 phase of the pipeline in the S2 unit in the figure its branch target is in the fetch packet that is in PG during that same cycle shaded in the figure Because the branch target has to wait until it reaches the E1 phase to begin execution the branch takes five delay slots before the branch target code executes Table 4 7 Branch Instruction Executi...

Page 355: ... Block Diagram DP PR PW PS PG 32 32 32 32 32 32 32 32 256 NOP MV SMPYH SMPYH SHR SHR LDW LDW B LDW SUB LDW SMPY SMPYH SMPYH SMPYH SADD SHR SADD SHR STH SADD STH SADD B SUB SMPY SMPYH SADD SADD STH STH MVK B SADD SADD SMPY SMPYH DC LDW LDW E1 L1 S1 MVK D1 M1 SMPY S2 B D2 SMPYH M2 Fetch Decode Execute L2 ...

Page 356: ... the src1 and src2 ports respectively The lower 32 bits of the DP source are written on E1 and the upper 32 bits of the DP source are written on E2 The two cycle DP instructions are executed on the S units The status is written to the FAUCR on E1 Figure 4 18 shows the fetch decode and execute phases of the pipe line that the two cycle DP instructions use Table 4 8 Two Cycle DP Instruction Executio...

Page 357: ...PINT SPTRUNC SUBSP The sources are read on E1 and the results are written on E4 The four cycle instructions are executed on the M or L units The status is written to the FMCR or FADCR on E4 Figure 4 19 shows the fetch decode and execute phases of the pipeline that the four cycle instructions use Table 4 9 Four Cycle Instruction Execution Pipeline Stage E1 E2 E3 E4 Read src1 src2 Written dst Unit i...

Page 358: ...ritten on E4 and the upper 32 bits of the result are written on E5 The INTDP instruction is executed on the L unit The status is written to the FADCR on E4 Figure 4 20 shows the fetch decode and execute phases of the pipeline that the INTDP instruction uses Table 4 10 INTDP Instruction Execution Pipeline Stage E1 E2 E3 E4 E5 Read src2 Written dst_l dst_h Unit in use L Figure 4 20 INTDP Instruction...

Page 359: ...llowing instructions are DP compare instructions CMPEQDP CMPLTDP CMPGTDP The DP compare instructions are executed on the S unit The functional unit latency for DP compare instructions is 2 The status is written to the FAUCR on E2 Figure 4 21 shows the fetch decode and execute phases of the pipe line that the DP compare instruction uses Table 4 11 DP Compare Instruction Execution Pipeline Stage E1 ...

Page 360: ...e ADDDP SUBDP instructions are executed on the L unit The functional unit latency for ADDDP SUBDP instructions is 2 The status is written to the FADCR on E6 Figure 4 22 shows the fetch decode and execute phases of the pipeline that the ADDDP SUBDP instructions use Table 4 12 ADDDP SUBDP Instruction Execution Pipeline Stage E1 E2 E3 E4 E5 E6 E7 Read src1_l src2_l src1_h src2_h Written dst_l dst_h U...

Page 361: ...n on E9 The MPYI instruction is executed on the M unit The functional unit latency for the MPYI instruction is 4 Figure 4 23 shows the fetch decode and execute phases of the pipeline that the MPYI instruction uses Table 4 13 MPYI Instruction Execution Pipeline Stage E1 E2 E3 E4 E5 E6 E7 E8 E9 Read src1 src2 src1 src2 src1 src2 src1 src2 Written dst Unit in use M M M M Figure 4 23 MPYI Instruction ...

Page 362: ...ts of the result are written on E10 The MPYID instruction is executed on the M unit The functional unit latency for the MPYID instruction is 4 Figure 4 24 shows the fetch decode and execute phases of the pipeline that the MPYID instruction uses Table 4 14 MPYID Instruction Execution Pipeline Stage E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 Read src1 src2 src1 src2 src1 src2 src1 src2 Written dst_l dst_h Unit ...

Page 363: ... the result are written on E9 and the upper 32 bits of the result are written on E10 The MPYDP instruction is executed on the M unit The functional unit latency for the MPYDP instruction is 4 The status is written to the FMCR on E9 Figure 4 25 shows the fetch decode and execute phases of the pipeline that the MPYDP instruction uses Table 4 15 MPYDP Instruction Execution Pipeline Stage E1 E2 E3 E4 ...

Page 364: ...f the result are written on E6 and the upper 32 bits of the result are written on E7 The MPYSPDP instruction is executed on the M unit The functional unit latency for the MPYSPDP instruction is 3 Figure 4 26 shows the fetch decode and execute phases of the pipeline that the MPYSPDP instruction uses Table 4 16 MPYSPDP Instruction Execution Pipeline Stage E1 E2 E3 E4 E5 E6 E7 Read src1 src2_l src1 s...

Page 365: ...E2 E3 E4 E5 Read src1 src2 Written dst_l dst_h Unit in use M Figure 4 27 MPYSP2DP Instruction Phases PG PS PW PR DP DC E1 E2 E3 E4 E5 4 delay slots 4 3 Functional Unit Constraints If you want to optimize your instruction pipeline consider the instructions that are executed on each unit Sources and destinations are read and written differently for each instruction If you analyze these differences y...

Page 366: ...gle cycle RW Instruction Type Subsequent Same Unit Instruction Executable Single cycle DP compare 2 cycle DP ADDDP SUBDP ADDSP SUBSP Branch Instruction Type Same Side Different Unit Both Using Cross Path Executable Single cycle Load Store INTDP ADDDP SUBDP 16 16 multiply 4 cycle MPYI MPYID MPYDP Legend E1 phase of the single cycle instruction R Sources read for the instruction W Destinations writt...

Page 367: ...ction Type Same Side Different Unit Both Using Cross Path Executable Single cycle Xr Load Xr Store Xr INTDP Xr ADDDP SUBDP Xr 16 16 multiply Xr 4 cycle Xr MPYI Xr MPYID Xr MPYDP Xr Legend E1 phase of the single cycle instruction R Sources read for the instruction W Destinations written for the instruction Next instruction can enter E1 during cycle Xr Next instruction cannot enter E1 during cycle r...

Page 368: ... Instruction Executable Single cycle Xw DP compare 2 cycle DP Xw ADDDP SUBDP ADDSP SUBSP Branch Instruction Type Same Side Different Unit Both Using Cross Path Executable Single cycle Load Store INTDP ADDDP SUBDP 16 16 multiply 4 cycle MPYI MPYID MPYDP Legend E1 phase of the single cycle instruction R Sources read for the instruction W Destinations written for the instruction Next instruction can ...

Page 369: ... Execution Cycle 1 2 3 4 ADDSP SUBSP R W Instruction Type Subsequent Same Unit Instruction Executable Single cycle Xw 2 cycle DP Xw Xw DP compare Xw ADDDP SUBDP ADDSP SUBSP Branch Legend E1 phase of the single cycle instruction R Sources read for the instruction W Destinations written for the instruction Next instruction can enter E1 during cycle Xw Next instruction cannot enter E1 during cycle wr...

Page 370: ...w DP compare Xr Xw Xw ADDDP SUBDP Xr ADDSP SUBSP Xr Xw Xw Branch Xr Instruction Type Same Side Different Unit Both Using Cross Path Executable Single cycle Xr DP compare Xr 2 cycle DP Xr 4 cycle Xr Load Store Branch Xr 16 16 multiply Xr MPYI Xr MPYID Xr MPYDP Xr Legend E1 phase of the single cycle instruction R Sources read for the instruction W Destinations written for the instruction Next instru...

Page 371: ...Unit Instruction Executable Single cycle DP compare 2 cycle DP ADDDP SUBDP ADDSP SUBSP Branch Instruction Type Same Side Different Unit Both Using Cross Path Executable Single cycle Load Store INTDP ADDDP SUBDP 16 16 multiply 4 cycle MPYI MPYID MPYDP Legend E1 phase of the single cycle instruction R Sources read for the instruction Next instruction can enter E1 during cycle The branch on register ...

Page 372: ... Cycle 1 2 3 16 16 multiply R W Instruction Type Subsequent Same Unit Instruction Executable 16 16 multiply 4 cycle MPYI MPYID MPYDP Instruction Type Same Side Different Unit Both Using Cross Path Executable Single cycle Load Store DP compare 2 cycle DP Branch 4 cycle INTDP ADDDP SUBDP Legend E1 phase of the single cycle instruction R Sources read for the instruction W Destinations written for the...

Page 373: ...uent Same Unit Instruction Executable 16 16 multiply Xw 4 cycle MPYI MPYID MPYDP Instruction Type Same Side Different Unit Both Using Cross Path Executable Single cycle Load Store DP compare 2 cycle DP Branch 4 cycle INTDP ADDDP SUBDP Legend E1 phase of the single cycle instruction R Sources read for the instruction W Destinations written for the instruction Next instruction can enter E1 during cy...

Page 374: ...Xr Xu Xu Xu MPYSP2DP Xr Xr Xr Xw Xw Xu Instruction Type Same Side Different Unit Both Using Cross Path Executable Single cycle Xr Xr Xr Load Store DP compare Xr Xr Xr 2 cycle DP Xr Xr Xr Branch Xr Xr Xr 4 cycle Xr Xr Xr INTDP Xr Xr Xr ADDDP SUBDP Xr Xr Xr Legend E1 phase of the single cycle instruction R Sources read for the instruction W Destinations written for the instruction Next instruction c...

Page 375: ...r Xr Xr Xw Xu Xu MPYSP2DP Xr Xr Xr Xw Xw Xw Instruction Type Same Side Different Unit Both Using Cross Path Executable Single cycle Xr Xr Xr Load Store DP compare Xr Xr Xr 2 cycle DP Xr Xr Xr Branch Xr Xr Xr 4 cycle Xr Xr Xr INTDP Xr Xr Xr ADDDP SUBDP Xr Xr Xr Legend E1 phase of the single cycle instruction R Sources read for the instruction W Destinations written for the instruction Next instruct...

Page 376: ...PDP Xr Xr Xr Xw Xu Xu MPYSP2DP Xr Xr Xr Xw Xw Xw Instruction Type Same Side Different Unit Both Using Cross Path Executable Single cycle Xr Xr Xr Load Store DP compare Xr Xr Xr 2 cycle DP Xr Xr Xr Branch Xr Xr Xr 4 cycle Xr Xr Xr INTDP Xr Xr Xr ADDDP SUBDP Xr Xr Xr Legend E1 phase of the single cycle instruction R Sources read for the instruction W Destinations written for the instruction Next ins...

Page 377: ... 1 2 3 4 MPYSP R W Instruction Type Subsequent Same Unit Instruction Executable MPYSPDP MPYSP2DP Instruction Type Same Side Different Unit Both Using Cross Path Executable Single cycle Load Store DP compare 2 cycle DP Branch 4 cycle INTDP ADDDP SUBDP Legend E1 phase of the single cycle instruction R Sources read for the instruction W Destinations written for the instruction Next instruction can en...

Page 378: ...Xw MPYSPDP Xr Xu MPYSP2DP Xr Xw Xw Instruction Type Same Side Different Unit Both Using Cross Path Executable Single cycle Xr Load Xr Store Xr DP compare Xr 2 cycle DP Xr Branch Xr 4 cycle Xr INTDP Xr ADDDP SUBDP Xr Legend E1 phase of the single cycle instruction R Sources read for the instruction W Destinations written for the instruction Next instruction can enter E1 during cycle Xr Next instruc...

Page 379: ... Xu MPYSP2DP Xw Instruction Type Same Side Different Unit Both Using Cross Path Executable Single cycle Xr Load Xr Store Xr DP compare Xr 2 cycle DP Xr Branch Xr 4 cycle Xr INTDP Xr ADDDP SUBDP Xr Legend E1 phase of the single cycle instruction R Sources read for the instruction W Destinations written for the instruction Next instruction can enter E1 during cycle Xr Next instruction cannot enter E...

Page 380: ... 1 2 Single cycle RW Instruction Type Subsequent Same Unit Instruction Executable Single cycle 4 cycle INTDP ADDDP SUBDP Instruction Type Same Side Different Unit Both Using Cross Path Executable Single cycle DP compare 2 cycle DP 4 cycle Load Store Branch 16 16 multiply MPYI MPYID MPYDP Legend E1 phase of the single cycle instruction R Sources read for the instruction W Destinations written for t...

Page 381: ...me Unit Instruction Executable Single cycle Xw 4 cycle INTDP ADDDP SUBDP Instruction Type Same Side Different Unit Both Using Cross Path Executable Single cycle DP compare 2 cycle DP 4 cycle Load Store Branch 16 16 multiply MPYI MPYID MPYDP Legend E1 phase of the single cycle instruction R Sources read for the instruction W Destinations written for the instruction Next instruction can enter E1 dur...

Page 382: ...it Instruction Executable Single cycle Xw Xw 4 cycle Xw INTDP Xw ADDDP SUBDP Instruction Type Same Side Different Unit Both Using Cross Path Executable Single cycle DP compare 2 cycle DP 4 cycle Load Store Branch 16 16 multiply MPYI MPYID MPYDP Legend E1 phase of the single cycle instruction R Sources read for the instruction W Destinations written for the instruction Next instruction can enter E1...

Page 383: ...SUBDP Xr Instruction Type Same Side Different Unit Both Using Cross Path Executable Single cycle Xr DP compare Xr 2 cycle DP Xr 4 cycle Xr Load Store Branch Xr 16 16 multiply Xr MPYI Xr MPYID Xr MPYDP Xr Legend E1 phase of the single cycle instruction R Sources read for the instruction W Destinations written for the instruction Next instruction can enter E1 during cycle Xr Next instruction cannot ...

Page 384: ...e 1 2 3 4 5 6 Load RW W Instruction Type Subsequent Same Unit Instruction Executable Single cycle Load Store Instruction Type Same Side Different Unit Both Using Cross Path Executable 16 16 multiply MPYI MPYID MPYDP Single cycle DP compare 2 cycle DP Branch 4 cycle INTDP ADDDP SUBDP Legend E1 phase of the single cycle instruction R Sources read for the instruction W Destinations written for the in...

Page 385: ... RW Instruction Type Subsequent Same Unit Instruction Executable Single cycle Load Store Instruction Type Same Side Different Unit Both Using Cross Path Executable 16 16 multiply MPYI MPYID MPYDP Single cycle DP compare 2 cycle DP Branch 4 cycle INTDP ADDDP SUBDP Legend E1 phase of the single cycle instruction R Sources read for the instruction W Destinations written for the instruction Next instr...

Page 386: ...gle cycle RW Instruction Type Subsequent Same Unit Instruction Executable Single cycle Load Store Instruction Type Same Side Different Unit Both Using Cross Path Executable 16 16 multiply MPYI MPYID MPYDP Single cycle DP compare 2 cycle DP Branch 4 cycle INTDP ADDDP SUBDP Legend E1 phase of the single cycle instruction R Sources read for the instruction W Destinations written for the instruction N...

Page 387: ...tion Constraints Instruction Execution Cycle 1 2 3 4 5 6 LDDW RW W Instruction Type Subsequent Same Unit Instruction Executable Instruction with long result Xw Legend E1 phase of the single cycle instruction R Sources read for the instruction W Destinations written for the instruction Next instruction can enter E1 during cycle Xw Next instruction cannot enter E1 during cycle write constraint ...

Page 388: ...P Each type of instruction has a fixed number of execute cycles that determines when this instruction s operations are complete Section 4 4 2 covers the effect of including a multicycle NOP in an individual EP Finally the effect of the memory system on the operation of the pipeline is considered The access of program and data memory is discussed along with memory stalls 4 4 1 Pipeline Operation Wi...

Page 389: ... first fetch packet n goes through the program fetch phases during cycles 1 4 During these cycles a program fetch phase is started for each of the fetch packets that follow In cycle 5 the program dispatch DP phase the CPU scans the p bits and detects that there are three execute packets k through k 2 in fetch packet n This forces the pipeline to stall which allows the DP phase to start for execute...

Page 390: ...n an execute packet in parallel with other code The results of the LD ADD and MPY is available during the proper cycle for each instruction Hence NOP has no effect on the execute packet Figure 4 29 b shows the replacement of the single cycle NOP with a multi cycle NOP NOP 5 in the same execute packet The NOP 5 causes no opera tion to perform other than the operations from the instructions inside i...

Page 391: ...le NOPs EP7 Normal Cycle 11 10 9 8 7 6 5 4 3 2 1 Target E1 DC DP PR PW PS PG Branch E1 EP6 EP5 EP4 EP3 EP2 EP1 NOP5 ADD MPY LD EP without branch EP without branch B EP without branch EP without branch Branch will execute here Pipeline Phase Branch EP7 See Figure 4 29 b Delay slots of the branch In one case execute packet 1 EP1 does not have a branch The NOP 5 in EP6 forces the CPU to wait until cy...

Page 392: ...es use these pipeline phases PG PS PW PR DP E1 E2 E3 E4 E5 To understand the memory accesses compare data loads and instruction fetches dispatches The comparison is valid because data loads and program fetches operate on internal memories of the same speed on the C67x DSP and perform the same types of operations listed in Table 4 40 to accommodate those memories Table 4 40 shows the operation of p...

Page 393: ...l causes all of the pipeline phases to lengthen beyond a single clock cycle causing execution to take additional clock cycles to finish The results of the program execution are identical whether a stall occurs or not Figure 4 32 illustrates this point Figure 4 32 Program and Data Memory Stalls Clock cycle Fetch packet FP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 ÁÁÁ ÁÁÁ n PG PS PW PR DP DC E1 E2 ÉÉ É...

Page 394: ...cause each of these banks is single ported memory only one access to each bank is allowed per cycle Two accesses to a single bank in a given cycle result in a memory stall that halts all pipeline operation for one cycle while the second value is read from memory Two memory operations per cycle are allowed without any stall as long as they do not access the same bank Consider the code in Example 4 ...

Page 395: ...mily varies from device to device See the device specific data manual to determine the memory spaces in your device Figure 4 34 8 Bank Interleaved Memory With Two Memory Spaces Bank 7 Bank 6 Bank 5 Bank 4 Bank 3 Bank 2 Bank 1 1 M Bank 0 16N 16N 16N 16N 16N 16N 16N 16N 16N 16N 16N 16N 16N 16N 16N 16N 0 1 16 17 Bank 0 2 3 18 19 Bank 1 4 5 20 21 Bank 2 6 7 22 23 Bank 3 8 9 24 25 Bank 4 10 11 26 27 Ba...

Page 396: ...the method the CPU uses to detect automatically the presence of interrupts and divert program execution flow to your interrupt service code Finally the chapter describes the programming implications of interrupts Topic Page 5 1 Overview 5 2 5 2 Globally Enabling and Disabling Interrupts 5 11 5 3 Individual Interrupt Control 5 13 5 4 Interrupt Detection and Processing 5 16 5 5 Performance Considera...

Page 397: ...atus of the interrupt within the interrupt flag register IFR If the interrupt is properly enabled the CPU begins processing the interrupt and redirecting program flow to the interrupt service routine 5 1 1 Types of Interrupts and Signals Used There are three types of interrupts on the CPUs of the TMS320C6000 DSPs Reset Maskable Nonmaskable These three types are differentiated by their priorities a...

Page 398: ...SET Reset is the highest priority interrupt and is used to halt the CPU and return it to a known state The reset interrupt is unique in a number of ways RESET is an active low signal All other interrupts are active high signals RESET must be held low for 10 clock cycles before it goes high again to reinitialize the CPU properly The instruction execution in progress is aborted and all registers are...

Page 399: ...ble interrupts INT4 INT15 are disabled 5 1 1 3 Maskable Interrupts INT4 INT15 The CPUs of the C6000 DSPs have 12 interrupts that are maskable These have lower priority than the NMI and reset interrupts These interrupts can be associated with external devices on chip peripherals software control or not be available Assuming that a maskable interrupt does not occur during the delay slots of a branch...

Page 400: ...nterrupt has occurred and is being processed The IACK signal indicates that the CPU has begun processing an interrupt The INUMn signal INUM3 INUM0 indicates the number of the interrupt bit position in the IFR that is being processed For example INUM3 0 MSB INUM2 1 INUM1 1 INUM0 1 LSB Together these signals provide the 4 bit value 0111 indicating INT7 is being processed ...

Page 401: ...pt service routine may fit in an individual fetch packet The addresses and contents of the IST are shown in Figure 5 1 Because each fetch packet contains eight 32 bit instruction words or 32 bytes each address in the table is incremented by 32 bytes 20h from the one adjacent to it Figure 5 1 Interrupt Service Table 000h 020h 040h 060h 080h 0A0h 0C0h 0E0h 100h 120h 140h 160h 180h 1A0h 1C0h 1E0h Pro...

Page 402: ...ne Note If the NOP 5 was not in the routine the CPU would execute the next five execute packets that are associated with the next ISFP Figure 5 2 Interrupt Service Fetch Packet Instr3 Interrupt service table IST Instr2 Instr4 Instr5 Instr6 B IRP NOP 5 ISFP for INT6 000h 020h 040h 060h 080h 0A0h 0C0h 0E0h 100h 120h 140h 160h 180h 1A0h 1C0h 1E0h 0C0h 0C4h 0C8h 0CCh 0D0h 0D4h 0D8h 0DCh The interrupt ...

Page 403: ...at address 1234h Figure 5 3 Interrupt Service Table With Branch to Additional Interrupt Service Code Located Outside the IST IST RESET ISFP NMI ISFP Reserved Reserved INT4 ISFP INT5 ISFP INT6 ISFP INT7 ISFP INT8 ISFP INT9 ISFP INT10 ISFP INT11 ISFP INT12 ISFP INT13 ISFP INT14 ISFP INT15 ISFP Additional ISFP for INT4 1220h The interrupt service routine for INT4 includes this 7 instruction extension...

Page 404: ... INT10 ISFP INT11 ISFP INT12 ISFP INT13 ISFP INT14 ISFP INT15 ISFP 0 820h 840h 860h 880h 8A0h 8C0h 8E0h 900h 920h 940h 96h0 980h 9A0h 9C0h 9E0h Program memory 800h RESET ISFP 1 Copy the IST located between 0h and 200h to the memory location between 800h and A00h 2 Write 800h to ISTP MVK 800h A2 MVC A2 ISTP ISTP 800h 1000 0000 0000b RESET ISFP Assume IFR BBC0h 1011 1011 1100 0000b IER 1230h 0001 00...

Page 405: ...u to enable interrupts 2 17 IFR Interrupt flag register Shows the status of interrupts 2 18 IRP Interrupt return pointer register Contains the return address used on return from a maskable interrupt This return is accomplished via the B IRP instruction 2 19 ISR Interrupt set register Allows you to set flags in the IFR manually 2 20 ISTP Interrupt service table pointer register Pointer to the begin...

Page 406: ...ng begins This is necessary because interrupts are detected in parallel with instruction execution Typically the GIE bit is 1 when an interrupt is taken However if an interrupt is detected in parallel with an MVC instruction that clears the GIE bit the GIE bit may be cleared by the MVC instruction after the interrupt processing begins Because the PGIE bit records the state of the GIE bit after all...

Page 407: ...mple 5 2 Code Sequence to Disable Maskable Interrupts Globally MVC CSR B0 get CSR AND 2 B0 B0 get ready to clear GIE MVC B0 CSR clear GIE Example 5 3 Code Sequence to Enable Maskable Interrupts Globally MVC CSR B0 get CSR OR 1 B0 B0 get ready to set GIE MVC B0 CSR set GIE ...

Page 408: ...le the reset interrupt Bits IE4 IE15 can be written as 1 or 0 enabling or disabling the associated interrupt respectively The IER is shown in Figure 2 7 page 2 17 and described in Table 2 9 When NMIE 0 all nonreset interrupts are disabled preventing interruption of an NMI The NMIE bit is cleared at reset to prevent any interruption of process or initialization until you enable NMI After reset you ...

Page 409: ...ag to be cleared Writing a 0 to any bit of either ISR or ICR has no effect Incoming interrupts have prior ity and override any write to ICR You cannot set or clear any bit in ISR or ICR to affect NMI or reset The ISR is shown in Figure 2 10 page 2 20 and described in Table 2 11 The ICR is shown in Figure 2 6 page 2 16 and described in Table 2 8 Note Any write to the ISR or ICR by the MVC instructi...

Page 410: ...urn pointer that directs the CPU to the proper location to contin ue program execution after NMI processing A branch using the address in NRP B NRP in your interrupt service routine returns to the program flow when NMI servicing is complete Example 5 8 shows how to return from an NMI Example 5 8 Code to Return From NMI B NRP return sets NMIE NOP 5 delay slots 5 3 4 3 Returning From Maskable Interr...

Page 411: ...4 Two clock cycles after detection the interrupt s corresponding flag bit in the IFR is set cycle 6 In Figure 5 4 IFm is set during CPU cycle 6 You could attempt to clear IFm by using an MVC instruction to write a 1 to bit m of the ICR in execute packet n 3 during CPU cycle 4 However in this case the automated write by the interrupt detection logic takes precedence and IFm remains set Figure 5 4 a...

Page 412: ...DP DC DP PR PW DC DP PR 2 1 CPU cycle IFm 0 External INTm at pin 0 0 IACK INUM 0 E2 E1 DC E1 DC DP DP PR PW PS PR PW PS PG n n 1 n 2 n 3 n 4 n 5 n 6 DC DP PR PW PS PG Execute packet PR 12 11 PW PS 10 9 8 PG DP PW PR PS PG PR PS PW PS PG PG PW PS PG 7 6 5 4 3 PG n 7 n 9 n 8 n 10 n 11 2 1 ISFP CPU cycle 0 13 0 E10 13 DP E9 Cycles 6 14 Nonreset interrupt processing is disabled Annulled Instructions C...

Page 413: ...y any CPU state Annulling also forces an instruction to be annulled in future pipeline stages The address of the first annulled execute packet n 5 is loaded in NRP in the case of NMI or IRP for all other interrupts During cycle 7 IACK is asserted and the proper INUMn signals are asserted to indicate which interrupt is being processed The timings for these signals in Figure 5 4 represent only the s...

Page 414: ...e Figure 5 5 RESET Interrupt Detection and Processing Pipeline Operation Reset ISFP n 7 n 6 Pipeline flush E1 DC DP PR PW PS PG PG PS PW PR DP DC E1 n 5 n 4 n 3 n 2 n 1 n Execute packet INUM IACK IF0 RESET Clock cycle 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Cycles 15 21 Nonreset interrupt processing is disabled 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CPU cyc...

Page 415: ...1 During CPU cycles 15 through 21 of Figure 5 5 the following reset proces sing actions occur Processing of subsequent nonreset interrupts is disabled because the GIE and NMIE bits are cleared A branch to the address held in ISTP the pointer to the ISFP for INT0 is forced into the E1 phase of the pipeline during cycle 16 During cycle 16 IACK is asserted and the proper INUMn signals are asserted to...

Page 416: ...on the time required for inter rupt service and whether you reenable interrupts during processing thereby allowing nested interrupts Effectively only two occurrences of a specific interrupt can be recognized in two cycles 5 5 2 Pipeline Interaction Because the serial or parallel encoding of fetch packets does not affect the DC and subsequent phases of the pipeline no conflicts between code paralle...

Page 417: ... fewer delay slots than they actually have Example 5 10 shows a code fragment which stores two variables into A1 using multiple assignment Example 5 11 shows equivalent code using the single assignment programming method which stores the two variables into two different registers For example suppose that register A1 contains 0 and register A0 points to a memory location containing a value of 10 be...

Page 418: ...llowing initial steps in addition to its normal work of saving any registers including control registers that it modifies 1 The contents of IRP or NRP must be saved 2 The contents of the PGIE bit must be saved 3 The GIE bit must be set to 1 Prior to returning from the interrupt service routine the code must restore the registers saved above as follows 1 The GIE bit must be first cleared to 0 2 The...

Page 419: ... STW B0 B15 4 Save B0 allocate 4 words of stack STW B1 B15 1 Save B1 on stack MVC IRP B0 STW B0 B15 2 Save IRP on stack MVC CSR B0 STW B0 B15 3 Save CSR and thus PGIE on stack OR B0 1 B1 MVC B1 CSR Enable interrupts Interrupt service code goes here Interrupts may occur while this code executes MVC CSR B0 AND B0 2 B1 Disable interrupts MVC B1 CSR Set GIE to 0 LDW B15 3 B0 get saved value of CSR int...

Page 420: ...highest priority inter rupt from the ISTP to the register B2 The next instruction extracts the number of the interrupt which is used later to clear the interrupt The branch to the interrupt service routine comes next with a parallel instruction to set up the ICR word The last five instructions fill the delay slots of the branch First the 32 bit return address is stored in the B2 register and then ...

Page 421: ... for a branch using a displacement the MVKH instructions could be eliminated thus shortening the code sequence The trap is processed with the code located at the address pointed to by the label TRAP_HANDLER If the B0 or B1 registers are needed in the trap handler their contents must be stored to memory and restored before return ing The code shown in Example 5 16 should be included at the end of t...

Page 422: ...tructions for 32 bit integer multiply doubleword load and floating point operations Table A 1 lists the instructions that are common to the C62x C64x C67x and C67x DSPs Table A 1 Instruction Compatibility Between C62x C64x C67x and C67x DSPs Instruction Page C62x DSP C64x DSP C67x DSP C67x DSP ABS 3 38 ABSDP 3 40 ABSSP 3 42 ADD 3 44 ADDAB 3 48 ADDAD 3 50 ADDAH 3 52 ADDAW 3 54 ADDDP 3 56 ADDK 3 59 ...

Page 423: ...nstruction C67x DSP C67x DSP C64x DSP C62x DSP Page B displacement 3 69 B register 3 71 B IRP 3 73 B NRP 3 75 CLR 3 77 CMPEQ 3 80 CMPEQDP 3 82 CMPEQSP 3 84 CMPGT 3 86 CMPGTDP 3 89 CMPGTSP 3 91 CMPGTU 3 93 CMPLT 3 95 CMPLTDP 3 98 CMPLTSP 3 100 CMPLTU 3 102 DPINT 3 104 DPSP 3 106 DPTRUNC 3 108 EXT 3 110 EXTU 3 113 IDLE 3 116 INTDP 3 117 INTDPU 3 119 ...

Page 424: ...3 121 INTSPU 3 122 LDB memory 3 123 LDB memory 15 bit offset 3 126 LDBU memory 3 123 LDBU memory 15 bit offset 3 126 LDDW 3 128 LDH memory 3 131 LDH memory 15 bit offset 3 134 LDHU memory 3 131 LDHU memory 15 bit offset 3 134 LDW memory 3 136 LDW memory 15 bit offset 3 139 LMBD 3 141 MPY 3 143 MPYDP 3 145 MPYH 3 147 MPYHL 3 149 MPYHLU 3 151 MPYHSLU 3 152 MPYHSU 3 153 MPYHU 3 154 MPYHULS 3 155 MPYH...

Page 425: ...ued Instruction C67x DSP C67x DSP C64x DSP C62x DSP Page MPYI 3 157 MPYID 3 159 MPYLH 3 161 MPYLHU 3 163 MPYLSHU 3 164 MPYLUHS 3 165 MPYSP 3 166 MPYSPDP 3 168 MPYSP2DP 3 170 MPYSU 3 172 MPYU 3 174 MPYUS 3 176 MV 3 178 MVC 3 180 MVK 3 183 MVKH 3 185 MVKL 3 187 MVKLH 3 185 NEG 3 189 NOP 3 190 NORM 3 192 NOT 3 194 OR 3 195 RCPDP 3 197 RCPSP 3 199 ...

Page 426: ...67x DSP C64x DSP C62x DSP Page RSQRDP 3 201 RSQRSP 3 203 SADD 3 205 SAT 3 208 SET 3 210 SHL 3 213 SHR 3 215 SHRU 3 217 SMPY 3 219 SMPYH 3 221 SMPYHL 3 222 SMPYLH 3 224 SPDP 3 226 SPINT 3 228 SPTRUNC 3 230 SSHL 3 232 SSUB 3 234 STB memory 3 236 STB memory 15 bit offset 3 238 STH memory 3 240 STH memory 15 bit offset 3 243 STW memory 3 245 STW memory 15 bit offset 3 247 ...

Page 427: ...33 Table A 1 Instruction Compatibility Between C62x C64x C67x and C67x DSPs Continued Instruction C67x DSP C67x DSP C64x DSP C62x DSP Page SUB 3 249 SUBAB 3 253 SUBAH 3 255 SUBAW 3 256 SUBC 3 258 SUBDP 3 260 SUBSP 3 263 SUBU 3 266 SUB2 3 268 XOR 3 270 ZERO 3 272 ...

Page 428: ...l Unit Table B 1 lists the instructions that execute on each functional unit Table B 1 Functional Unit to Instruction Mapping Functional Unit Instruction L Unit M Unit S Unit D Unit ABS ABSDP ABSSP ADD ADDAB ADDAD ADDAH ADDAW ADDDP ADDK ADDSP ADDU ADD2 AND S2 only D2 only C67x DSP specific instruction Appendix B ...

Page 429: ... Functional Unit to Instruction Mapping Continued Instruction Functional Unit Instruction D Unit S Unit M Unit L Unit B displacement B register B IRP B NRP CLR CMPEQ CMPEQDP CMPEQSP CMPGT CMPGTDP CMPGTSP CMPGTU CMPLT CMPLTDP CMPLTSP CMPLTU DPINT DPSP DPTRUNC EXT EXTU IDLE S2 only D2 only C67x DSP specific instruction ...

Page 430: ...ruction Functional Unit Instruction D Unit S Unit M Unit L Unit INTDP INTDPU INTSP INTSPU LDB memory LDB memory 15 bit offset LDBU memory LDBU memory 15 bit offset LDDW LDH memory LDH memory 15 bit offset LDHU memory LDHU memory 15 bit offset LDW memory LDW memory 15 bit offset LMBD MPY MPYDP MPYH MPYHL MPYHLU MPYHSLU MPYHSU S2 only D2 only C67x DSP specific instruction ...

Page 431: ... Table B 1 Functional Unit to Instruction Mapping Continued Instruction Functional Unit Instruction D Unit S Unit M Unit L Unit MPYHU MPYHULS MPYHUS MPYI MPYID MPYLH MPYLHU MPYLSHU MPYLUHS MPYSP MPYSPDP MPYSP2DP MPYSU MPYU MPYUS MV MVC MVK MVKH MVKL MVKLH NEG NOP S2 only D2 only C67x DSP specific instruction ...

Page 432: ...733 Table B 1 Functional Unit to Instruction Mapping Continued Instruction Functional Unit Instruction D Unit S Unit M Unit L Unit NORM NOT OR RCPDP RCPSP RSQRDP RSQRSP SADD SAT SET SHL SHR SHRU SMPY SMPYH SMPYHL SMPYLH SPDP SPINT SPTRUNC SSHL SSUB STB memory S2 only D2 only C67x DSP specific instruction ...

Page 433: ... Functional Unit to Instruction Mapping Continued Instruction Functional Unit Instruction D Unit S Unit M Unit L Unit STB memory 15 bit offset STH memory STH memory 15 bit offset STW memory STW memory 15 bit offset SUB SUBAB SUBAH SUBAW SUBC SUBDP SUBSP SUBU SUB2 XOR ZERO S2 only D2 only C67x DSP specific instruction ...

Page 434: ...pcode Maps This appendix lists the instructions that execute in the D functional unit and illustrates the opcode maps for these instructions Topic Page C 1 Instructions Executing in the D Functional Unit C 2 C 2 Opcode Map Symbols and Meanings C 3 C 3 32 Bit Opcode Maps C 5 Appendix C ...

Page 435: ...ctions Executing in the D Functional Unit Instruction Instruction ADD LDW memory ADDAB LDW memory 15 bit offset ADDAD MV ADDAH STB memory ADDAW STB memory 15 bit offset LDB memory STH memory LDB memory 15 bit offset STH memory 15 bit offset LDBU memory STW memory LDBU memory 15 bit offset STW memory 15 bit offset LDDW SUB LDH memory SUBAB LDH memory 15 bit offset SUBAH LDHU memory SUBAW LDHU memor...

Page 436: ...ssing mode see Table C 3 offsetR register offset op opfield field within opcode that specifies a unique instruction p parallel execution 0 next instruction is not executed in parallel 1 next instruction is executed in parallel r LDDW instruction s side A or B for destination 0 side A 1 side B For compact instructions side of base ad dress ptr register 0 side A 1 side B src source For compact instr...

Page 437: ... 0 0 0 R ucst5 Negative offset 0 0 0 1 R ucst5 Positive offset 0 1 0 0 R offsetR Negative offset 0 1 0 1 R offsetR Positive offset 1 0 0 0 R ucst5 Predecrement 1 0 0 1 R ucst5 Preincrement 1 0 1 0 R ucst5 Postdecrement 1 0 1 1 R ucst5 Postincrement 1 1 0 0 R offsetR Predecrement 1 1 0 1 R offsetR Preincrement 1 1 1 0 R offsetR Postdecrement 1 1 1 1 R offsetR Postincrement ...

Page 438: ...op 1 0 0 0 0 s p 3 1 5 5 5 6 1 1 Figure C 2 Extended D Unit 1 or 2 Sources Instruction Format 31 29 28 27 23 22 18 17 13 12 11 10 9 6 5 4 3 2 1 0 creg z dst src2 src1 x 1 0 op 1 1 0 0 s p 3 1 5 5 5 1 4 1 1 Figure C 3 Load Store Basic Operations 31 29 28 27 23 22 18 17 13 12 9 8 7 6 4 3 2 1 0 creg z src dst baseR offsetR mode r y op 1 0 s p 3 1 5 5 5 4 1 1 3 1 1 Figure C 4 Load Store Long Immediate...

Page 439: ...pcode Maps This appendix lists the instructions that execute in the L functional unit and illustrates the opcode maps for these instructions Topic Page D 1 Instructions Executing in the L Functional Unit D 2 D 2 Opcode Map Symbols and Meanings D 3 D 3 32 Bit Opcode Maps D 4 Appendix D ...

Page 440: ...t Table D 1 lists the instructions that execute in the L functional unit Table D 1 Instructions Executing in the L Functional Unit Instruction Instruction ABS LMBD ADD MV ADDDP NEG ADDSP NORM ADDU NOT AND OR CMPEQ SADD CMPGT SAT CMPGTU SPINT CMPLT SPTRUNC CMPLTU SSUB DPINT SUB DPSP SUBC DPTRUNC SUBDP INTDP SUBSP INTDPU SUBU INTSP XOR INTSPU ZERO ...

Page 441: ...l Meaning creg 3 bit field specifying a conditional register dst destination op opfield field within opcode that specifies a unique instruction p parallel execution 0 next instruction is not executed in parallel 1 next instruction is executed in parallel s side A or B for destination 0 side A 1 side B src1 source 1 src2 source 2 x cross path for src2 0 do not use cross path 1 use cross path z test...

Page 442: ...truction Format 31 29 28 27 23 22 18 17 13 12 11 5 4 3 2 1 0 creg z dst src2 src1 x op 1 1 0 s p 3 1 5 5 5 1 7 1 1 Figure D 2 1 or 2 Sources Nonconditional Instruction Format 31 29 28 27 23 22 18 17 13 12 11 5 4 3 2 1 0 0 0 0 1 dst src2 src1 x op 1 1 0 s p 5 5 5 1 7 1 1 Figure D 3 Unary Instruction Format 31 29 28 27 23 22 18 17 13 12 11 5 4 3 2 1 0 creg z dst src2 op x 0 0 1 1 0 1 0 1 1 0 s p 3 1...

Page 443: ...pcode Maps This appendix lists the instructions that execute in the M functional unit and illustrates the opcode maps for these instructions Topic Page E 1 Instructions Executing in the M Functional Unit E 2 E 2 Opcode Map Symbols and Meanings E 3 E 3 32 Bit Opcode Maps E 4 Appendix E ...

Page 444: ...able E 1 lists the instructions that execute in the M functional unit Table E 1 Instructions Executing in the M Functional Unit Instruction Instruction MPY MPYLHU MPYDP MPYLSHU MPYH MPYLUHS MPYHL MPYSP MPYHLU MPYSPDP MPYHSLU MPYSP2DP MPYHSU MPYSU MPYHU MPYU MPYHULS MPYUS MPYHUS SMPY MPYI SMPYH MPYID SMPYHL MPYLH SMPYLH C67x DSP specific instruction ...

Page 445: ...l Meaning creg 3 bit field specifying a conditional register dst destination op opfield field within opcode that specifies a unique instruction p parallel execution 0 next instruction is not executed in parallel 1 next instruction is executed in parallel s side A or B for destination 0 side A 1 side B src1 source 1 src2 source 2 x cross path for src2 0 do not use cross path 1 use cross path z test...

Page 446: ...8 27 23 22 18 17 13 12 11 10 6 5 4 3 2 1 0 creg z dst src2 src1 x 0 op 1 1 0 0 s p 3 1 5 5 5 1 5 1 1 Figure E 2 Extended M Unit 1 or 2 Sources Nonconditional Instruction Format 31 29 28 27 23 22 18 17 13 12 11 10 6 5 4 3 2 1 0 0 0 0 1 dst src2 src1 x 0 op 1 1 0 0 s p 5 5 5 1 5 1 1 Figure E 3 Extended M Unit Unary Instruction Format 31 29 28 27 23 22 18 17 13 12 11 10 6 5 4 3 2 1 0 0 0 0 1 dst src2...

Page 447: ...pcode Maps This appendix lists the instructions that execute in the S functional unit and illustrates the opcode maps for these instructions Topic Page F 1 Instructions Executing in the S Functional Unit F 2 F 2 Opcode Map Symbols and Meanings F 3 F 3 32 Bit Opcode Maps F 4 Appendix F ...

Page 448: ... functional unit Table F 1 Instructions Executing in the S Functional Unit Instruction Instruction ABSDP MVKH ABSSP MVKL ADD MVKLH ADDDP NEG ADDK NOT ADDSP OR ADD2 RCPDP AND RCPSP B displacement RSQRDP B register RSQRSP B IRP SET B NRP SHL CLR SHR CMPEQDP SHRU CMPEQSP SPDP CMPGTDP SSHL CMPGTSP SUB CMPLTDP SUBDP CMPLTSP SUBSP EXT SUBU EXTU SUB2 MV XOR MVC ZERO MVK S2 only C67x DSP specific instruct...

Page 449: ...gister csta constant a cstb constant b cstn n bit constant field dst destination h MVK or MVKH MVKLH instruction 0 MVK 1 MVKH MVKLH op opfield field within opcode that specifies a unique instruction p parallel execution 0 next instruction is not executed in parallel 1 next instruction is executed in parallel s side A or B for destination 0 side A 1 side B src1 source 1 src2 source 2 x cross path f...

Page 450: ...ormat 31 29 28 27 23 22 18 17 13 12 11 10 9 6 5 4 3 2 1 0 creg z dst src2 src1 x 1 1 op 1 1 0 0 s p 3 1 5 5 5 1 4 1 1 Figure F 3 Extended S Unit 1 or 2 Sources Nonconditional Instruction Format 31 29 28 27 23 22 18 17 13 12 11 10 9 6 5 4 3 2 1 0 0 0 0 z dst src2 src1 x 1 1 op 1 1 0 0 s p 1 5 5 5 1 4 1 1 Figure F 4 Unary Instruction Format 31 29 28 27 23 22 18 17 13 12 11 5 4 3 2 1 0 creg z dst src...

Page 451: ...8 Branch with NOP Register Instruction Format 31 29 28 27 23 22 18 17 16 15 13 12 11 6 5 4 3 2 1 0 creg z 0 0 0 0 1 src2 0 0 src1 x 0 0 1 1 0 1 1 0 0 0 s p 3 1 5 3 1 1 1 Figure F 9 Branch Instruction Format 31 29 28 27 23 22 18 17 13 12 11 6 5 4 3 2 1 0 creg z 0 0 0 0 0 src2 0 0 0 0 0 x 0 0 1 1 0 1 1 0 0 0 s p 3 1 5 1 1 1 Figure F 10 MVK Instruction Format 31 29 28 27 23 22 7 6 5 4 3 2 1 0 creg z ...

Page 452: ...e instructions that execute in the D functional unit see Appendix C For a list of the instructions that execute in the L functional unit see Appendix D For a list of the instructions that execute in the M functional unit see Appendix E For a list of the instructions that execute in the S functional unit see Appendix F Topic Page G 1 Instructions Executing With No Unit Specified G 2 G 2 Opcode Map ...

Page 453: ... G 2 No Unit Specified Instructions Opcode Map Symbol Definitions Symbol Meaning creg 3 bit field specifying a conditional register csta constant a cstb constant b cstn n bit constant field iin bit n of the constant ii N3 3 bit field op opfield field within opcode that specifies a unique instruction p parallel execution 0 next instruction is not executed in parallel 1 next instruction is executed ...

Page 454: ...31 29 28 27 23 22 18 17 16 13 12 11 10 9 8 7 6 5 4 3 2 1 0 creg z cstb csta 1 op 0 0 0 0 0 0 0 0 0 0 0 s p 3 1 5 5 4 1 1 Figure G 2 NOP and IDLE Instruction Format 31 29 28 27 18 17 16 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 1 Reserved 0 0 op 0 0 0 0 0 0 0 0 0 0 0 s p 10 4 1 1 Figure G 3 Emulation Control Instruction Format 31 29 28 27 23 22 18 17 16 13 12 11 10 9 8 7 6 5 4 3 2 1 0 creg z Reserved 0...

Page 455: ...ord addressing mode ADDAD 3 50 using halfword addressing mode ADDAH 3 52 using word addressing mode ADDAW 3 54 with saturation two signed integers SADD 3 205 without saturation two signed integers ADD 3 44 two unsigned integers ADDU 3 63 ADD instruction 3 44 add instructions using circular addressing 3 32 using linear addressing 3 30 ADD2 instruction 3 65 ADDAB instruction 3 48 ADDAD instruction 3...

Page 456: ... 22 branching into the middle of an execute packet 3 18 performance considerations 5 21 to additional interrupt service routine 5 8 C circular addressing block size calculations 2 12 circular addressing mode add instructions 3 32 block size specification 3 31 load instructions 3 31 store instructions 3 31 subtract instructions 3 32 clear a bit field CLR 3 77 clear an individual interrupt 5 14 clea...

Page 457: ...SP instruction 4 37 branch instruction 4 39 DP compare instruction 4 35 single cycle instruction 4 34 SUBDP instruction 4 38 SUBSP instruction 4 37 on cross paths 3 21 on floating point instructions 3 26 on instructions using the same functional unit 3 20 on loads and stores 3 22 on long data 3 23 on register reads 3 24 on register writes 3 25 on the same functional unit writing in the same instru...

Page 458: ...xecute packet pipeline operation 4 56 execution notations 3 2 EXT instruction 3 110 extract and sign extend a bit field EXT 3 110 extract and zero extend a bit field EXTU 3 113 EXTU instruction 3 113 F FADCR 2 23 FAUCR 2 27 features TMS320C67x DSP 1 4 TMS320C67x DSP 1 4 fetch packet 3 16 fetch packet FP 5 7 fetch packets fully parallel 3 17 fully serial 3 17 partially serial 3 18 fetch pipeline ph...

Page 459: ...R 2 16 interrupt enable register IER 2 17 interrupt flag register IFR 2 18 interrupt return pointer register IRP 2 19 interrupt service fetch packet ISFP 5 7 interrupt service table IST 5 6 interrupt service table pointer ISTP overview 5 9 interrupt service table pointer register ISTP 2 21 interrupt set register ISR 2 20 interrupts clearing 5 14 control 5 13 control registers 5 10 detection and pr...

Page 460: ...0 store instructions 3 30 subtract instructions 3 30 LMBD instruction 3 141 load byte from memory with a 5 bit unsigned constant offset or register offset LDB and LDBU 3 123 from memory with a 15 bit unsigned constant offset LDB and LDBU 3 126 doubleword from memory with an unsigned constant offset or register offset LDDW 3 128 halfword from memory with a 5 bit unsigned constant offset or register...

Page 461: ...ruction 3 172 MPYU instruction 3 174 MPYUS instruction 3 176 multicycle NOP with no termination until interrupt IDLE 3 116 multicycle NOPs 4 58 multiply 32 bit by 32 bit into 32 bit result MPYI 3 157 into 64 bit result MPYID 3 159 floating point double precision MPYDP 3 145 single precision MPYSP 3 166 single precision by double precision MPYSPDP 3 168 single precision for double precision result ...

Page 462: ...IF bit 2 18 no operation NOP 3 190 NOP instruction 3 190 NORM instruction 3 192 normalize integer NORM 3 192 NOT instruction 3 194 notational conventions iii NRP 2 22 O opcode fields and meanings 3 7 opcode map D unit C 3 L unit D 3 M unit E 3 S unit F 3 32 bit D unit C 5 L unit D 4 M unit E 4 S unit F 4 no unit instructions G 3 no unit instructions G 2 symbols and meanings D unit C 3 L unit D 3 M...

Page 463: ...ion floating point RCPSP 3 199 square root double precision floating point RSQRDP 3 201 single precision floating point RSQRSP 3 203 register files cross paths 2 6 data address paths 2 7 general purpose 2 2 memory load and store paths 2 6 relationship to data paths 2 6 registers addresses for accessing 2 8 addressing mode register AMR 2 10 control register file 2 7 control register file extensions...

Page 464: ...uare root reciprocal approximation double precision floating point RSQRDP 3 201 single precision floating point RSQRSP 3 203 SSHL instruction 3 232 SSUB instruction 3 234 STB instruction 5 bit unsigned constant offset or register offset 3 236 15 bit unsigned constant offset 3 238 STH instruction 5 bit unsigned constant offset or register offset 3 240 15 bit unsigned constant offset 3 243 store byt...

Page 465: ...ed integers SUB 3 249 two unsigned integers SUBU 3 266 subtract instructions using circular addressing 3 32 using linear addressing 3 30 SUBU instruction 3 266 syntax fields and meanings 3 7 T TMS320 DSP family applications 1 3 overview 1 2 TMS320C6000 DSP family overview 1 2 TMS320C67x DSP architecture 1 7 block diagram 1 7 features 1 4 options 1 4 trademarks iv traps invoking a trap 5 26 returni...

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