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Texas Instruments TLK6002 User Manual Download Page 69

1p0V

DVDD

VDDRA

VREFT

2p5V

1p5/8V

Header

2p5V

www.ti.com

TLK6002EVM Board Layouts

Figure 55. Internal Power, Layer 16

69

SLLU132 – October 2010

TLK6002 Dual-Channel, 0.47-Gbps to 6.25-Gbps, Multi-Rate Transceiver

Evaluation Module

Submit Documentation Feedback

Copyright © 2010, Texas Instruments Incorporated

Summary of Contents for TLK6002

Page 1: ...ion of this equipment in other environments may cause interference with radio communications in which case users at their expense are required to take whatever measures may be required to correct this...

Page 2: ...ail LEDs Sheet 9 34 27 1p0V Power Regulator Sheet 10 35 28 1p2V Power Regulator Sheet 11 36 29 1p5V Power Regulator Sheet 12 37 30 1p8V Power Regulator Sheet 13 38 31 2p5V Power Regulator Sheet 14 39...

Page 3: ...om Signal Layer 18 70 List of Tables 1 Bill of Materials 54 2 TLK6002EVM Layer Construction 71 3 SLLU132 October 2010 TLK6002 Dual Channel 0 47 Gbps to 6 25 Gbps Multi Rate Transceiver Evaluation Modu...

Page 4: ...55 R162 U20 R158 R161 R139 R141 R142 R140 U16 R144 R143 R148 R145 R151 R153 JMP105 JMP104 JMP103 JMP102 U31 D5 D6 D7 D8 D16 D15 D14 D13 D12 D10 D11 D20 D22 D32 D34 D38 D37 D33 D31 D21 JMP15 SW1 D1 D2...

Page 5: ...board layout As the frequency of operation increases the board designer must take special care to ensure that the highest signal integrity is maintained To achieve this the board s impedance is contr...

Page 6: ...mbly shop and are adjustable using a resistor divider between the output and a feedback pin Each regulator has been set to provide the appropriate minimum nominal or maximum voltage per the data sheet...

Page 7: ...NOM or MAX pins The adjustment circuit consists of a several resistor dividers and some voltage window comparator circuits When the minimum voltage is selected 1 V is input to the comparator circuit...

Page 8: ...resistor has been installed at the voltage entrance point of each power plane and can be replaced with a ferrite bead of an appropriate value depending upon the desired data rate if desired See the P...

Page 9: ...de the base resistors have been given extra margin to allow the LEDs to light when the voltage on the plane is a little below the minimum limit of that supply in order to provide a LED indicator of po...

Page 10: ...en the voltage is great enough to cause current to flow through the LED drive circuit This LED configuration has been designed to be used when pushing the lower limits of the acceptable voltage range...

Page 11: ...SSA SIGNAL LATCH LEDS PULLUP RESISTORS ARE CONNECTED TO ALL CONTROL INPUT LINES REMOVING THE SHUNTS ON THE CONTROL BLOCK HEADERS WILL CAUSE THE PULLUP RESISTOR TO PULL THE LINE TO A LOGIC HIGH AND PLA...

Page 12: ...ti Rate Transceiver data sheet SLLSE34 for more detail REFCLK_B_SEL Reference Clock Select Channel B This input when low selects REFCLK_0_P N as the clock reference to Channel B SERDES macro When high...

Page 13: ...his pin is floating During register based power down 1 15 asserted high this pin is floating It is highly recommended that LOSA be brought to an easily accessible point on the application board header...

Page 14: ...B is placed in power down mode When de asserted Channel B operated normally After de assertion a software data path reset must be issued through the MDIO interface AMUXB SERDES Channel B Analog Testa...

Page 15: ...resistor to VDDO2 GPI1 General Purpose Input One This signal can be used to logically combine an external status condition with LOSA or LOSB if enabled in an MDIO register Note that if GPI1 is low LOS...

Page 16: ...running error free pushing the PRBS_PASS RESET button resets the latch circuit which consists of a J K flip flop and a red and green LED to indicate the state of the flip flop When the J K flip flop i...

Page 17: ...SSING SW4 PRBS_PASSA SIGNAL LATCH LEDS RESET BY PRESSING SW3 BLUE PRBS_PASS SIGNAL LEDS PRBS_PASS SIGNALS CAN BE OBSERVED WITH A SCOPE HERE ENABLE THE PRBS GENERATOR ANALYZER FUNCTION BY REMOVING THIS...

Page 18: ...registers are ignored Read transactions of invalid registers return a 0 The bidirectional MDIO pin must be externally pulled up to 1 5 V or 1 8 V VDDO with an appropriate resistor value as per the IE...

Page 19: ...In system applications where JTAG is not implemented this input signal can be left unconnected During pin based power down PD_TRXA_N and PD_TRXB_N asserted low this pin is not pulled up During regist...

Page 20: ...us resetting the TLK6002 device whenever the pushbutton RESET is pressed By placing a jumper on JMP15 the Manual Reset MR is tied hard to ground causing the TLK6002 to be held in a constant state of R...

Page 21: ...race lengths to themselves 0 5 mil Figure 13 Parallel Signal Header Block Diagram Parallel Loopback shown in Figure 14 can be easily implemented by placing jumpers on the RDx TDx pins of the header Fo...

Page 22: ...reference for a scope probe or coaxial cables The additional TDA B row and VDD pins allow a static pattern to be driven into the TDA B bus by placing jumpers across either the TDA and 1p5 8V pins for...

Page 23: ...2 5 V 3 3 V and 5 V have been provided to allow for minimal power circuitry on the peripheral board itself as well as the global reset signal which is connected to the TLK6002 Reset pin TI is develop...

Page 24: ...14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TLK6002 EVM 6519192 REV NA 1P5 8V TDA0 19 TDA0 19 RDA0 19 GND GND 1P5 8V TDB0 19 TDB0 19 RDB0 19 GND GND MDIO PRBSA...

Page 25: ...1P5V 1P8V 1P5V 1P8V 1P5V 1P8V 0P75V 0P9V VREFT VDDRB VDDRA 1P5 8V 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 19 18 17 16 15 14 13 12 11 10 9 8...

Page 26: ...SHEET 21 2P5V 3P3V AND 5V SUPPLY LEDS SHEET 22 DVDD SUPPLY LEDS SHEET 23 1P5 8V SUPPLY LEDS SHEET 24 VDDRA SUPPLY LEDS SHEET 25 VDDRB SUPPLY LEDS SHEET 26 VREFT SUPPLY LEDS SHEET 27 NO CONNECT PINS S...

Page 27: ...20 K6 DGND21 K14 DGND22 K17 DGND23 L2 DGND24 M7 DGND25 M9 DGND26 M11 DGND27 N2 DGND28 N4 DGND29 N7 DGND30 N8 DGND31 N10 DGND32 N11 DGND33 N12 DGND34 N15 DGND35 N17 DGND36 P7 DGND37 P8 DGND38 P9 DGND39...

Page 28: ...C1 1 E1 2 C2 3 B2 4 E2 5 B1 6 TLK60X2 U1 1 RESET V1 PRBS_EN R16 CLK_OUT_SEL T15 R8 4 99K R2 130 C258 1uF R10 DNI_4 99K R15 DNI_4 99K R442 1k U2 TPS3125J18 RST 1 GND 2 RST 3 VDD 5 MR 4 R527 4 99K GPI1...

Page 29: ...RXBN_SMP RXBP_SMP RXAN_SMP RXAP_SMP TXAP_SMP RXAP RXAN RXBP RXBN TXBP_SMP TXBN_SMP TXAN_SMP TXBP TXBN TXAP TXAN NOTE SMP CONNECTORS SHOULD BE PLACED ON THE BOTTOM SIDE OF THE BOARD AND THE NETS KEPT...

Page 30: ...OUTN_SMP CLKOUTP CLKOUTN REFCLK_SEL_PWR REFCLK_B_SEL REFCLK_A_SEL REFCLK1N REFCLK1P REFCLK0N REFCLK0P REFCLK0P_SMP REFCLK0N_SMP REFCLK1P_SMP REFCLK1N_SMP CLKOUTP_SMP 1P5 8V NOTE SMP CONNECTORS SHOULD...

Page 31: ...5K JMP45 Header 5x2 1 3 5 7 9 2 4 6 8 10 JMP35 Header 5x2 1 3 5 7 9 2 4 6 8 10 R418 DNI_1K R46 DNI_1 5K R532 DNI_0 R424 1K R420 DNI_1K R469 DNI_0 R456 1K R533 DNI_0 R423 1K R440 DNI_1K MDIO_CON MDC MD...

Page 32: ...48 54 60 JMP37A 1 7 13 19 25 31 37 43 49 55 2 8 14 20 26 32 38 44 50 56 JMP40A 1 7 13 19 25 31 37 43 49 55 2 8 14 20 26 32 38 44 50 56 TLK60X2 U1 9 RDB_19 D18 RDB_18 E17 RDB_17 B18 RDB_16 C17 RDB_15 F...

Page 33: ...PULLUP ENABLE 1 2 R430 DNI_0 JMP146 Header 4x1 1 R31 4 99K R428 DNI_0 R33 4 99K R26 4 99K TLK60X2 U1 4 TXCLK_A P1 TXCLK_B T18 R32 4 99K D42 HSMB C170 2 1 TXCLK_A TXCLK_B RXCLK_B RXCLK_A LOSA_FAIL_LED...

Page 34: ...4 99K U87 TPS3125J18 RST 1 GND 2 RST 3 VDD 5 MR 4 R510 4 99K R522 45 3K U88 ZXTD09N50DE6 C1 1 E1 2 C2 3 B2 4 E2 5 B1 6 U86C SN74LVC112A 2PRE 10 2J 11 2CLK 13 2K 12 2CLR 14 2Q 9 2Q 7 D49 RED 2 1 D3 RE...

Page 35: ...AX_ADJ REG_NOM_ADJ REG_MIN_ADJ 3 0V LOW HIGH HIGH 2 0V HIGH LOW HIGH 1 0V HIGH HIGH LOW REGULATOR OUTPUT 1 05V 1 0V 0 95V X X X X X X X X X X X X 1 05V 0 95V 1 0V MIN NOM MAX V_ADJ IF R125 IS INSTALLE...

Page 36: ...E NOT INSTALLED THE REGULATOR WILL DEFAULT TO THE TLK6002 MIN VALUE OF 1 14V IF NEITHER REG_ENABLE REG_MAX_ADJ NOR REG_NOM_ADJ IS ACTIVE LOW IF R108 R117 AND R118 ARE INSTALLED AND R108 IS NOT INSTALL...

Page 37: ...HE REGULATOR WILL DEFAULT TO THE TLK6002 MIN VALUE OF 1 4V IF NEITHER REG_ENABLE REG_MAX_ADJ NOR REG_NOM_ADJ IS ACTIVE LOW IF R75 R83 AND R84 ARE INSTALLED AND R74 IS NOT INSTALLED THE REGULATOR WILL...

Page 38: ...INSTALLED THE REGULATOR WILL DEFAULT TO THE TLK6002 MIN VALUE OF 1 7V IF NEITHER REG_ENABLE REG_MAX_ADJ NOR REG_NOM_ADJ IS ACTIVE LOW IF R92 R100 AND R101 ARE INSTALLED AND R91 IS NOT INSTALLED THE RE...

Page 39: ...E REGULATOR WILL DEFAULT TO THE TLK6002 MIN VALUE OF 2 37V IF NEITHER REG_ENABLE REG_MAX_ADJ NOR REG_NOM_ADJ IS ACTIVE LOW IF R58 R66 AND R67 ARE INSTALLED AND R57 IS NOT INSTALLED THE REGULATOR WILL...

Page 40: ...NSTALLED THE REGULATOR WILL DEFAULT TO THE TLK6002 MIN VALUE OF 3 135V IF NEITHER REG_ENABLE REG_MAX_ADJ NOR REG_NOM_ADJ IS ACTIVE LOW IF R366 R374 AND R375 ARE INSTALLED AND R365 IS NOT INSTALLED THE...

Page 41: ...M339A U20C 2 IN_N 4 2 IN_P 5 2 OUT 2 R149 100 R145 1 82K U17B CD4025B A 1 B 2 C 8 J 9 R156 10 0K V_ADJ_NOM_VREF_LOW V_ADJ_MAX V_ADJ_NOM_VREF_HIGH VADJ_ENABLE_VREF_HIGH VADJ_4V VADJ_ENABLE_VREF_LOW V_A...

Page 42: ...DJ REG_NOM_ADJ REG_MIN_ADJ HIGH R174 HIGH HIGH OFF OFF LOW ON OFF VOLTAGE REGULATOR MARGIN ADJUSTMENT CONTROL SIGNAL LED OPERATION TABLE REG_MAX_ADJ REG_NOM_ADJ REG_MIN_ADJ HIGH HIGH HIGH LOW HIGH HIG...

Page 43: ...mper 1 2 3 P24 RAPC722 SILK 5V SLEEVE 1 SHUNT 2 TIP 3 C126 0 1uf JMP70 3 Pin Berg Jumper 1 2 3 JMP58 3 Pin Berg Jumper 1 2 3 P5 GND 1 C153 100uF C187 1 0uf R179 0 C144 0 1uf P3 GND 1 C132 0 1uf C232 1...

Page 44: ...27 ZXTD09N50DE6 C1 1 E1 2 C2 3 B2 4 E2 5 B1 6 LM339A U25B 1 IN_P 7 1 IN_N 6 1 OUT 1 1P2V_VREF_HIGH 1P2V_VREF_LOW 1P2V_LED_IN 1P2V_LED_VF 1P0V_LED_VF 1P2V_LED_COL 1P0V_LED_COL 1P0V_LED_BASE 1P0V_VREF_H...

Page 45: ...T 14 LM339A U28A VCC 3 GND 12 R208 105K R205 49 9 JMP99 LED SELECT 1 2 3 R216 10 2K 1P5V_VREF_HIGH 1P5V_VREF_LOW 1P5V_LED_IN 1P5V_LED_VF 1P8V_LED_VF 1P5V_LED_COL 1P8V_LED_COL 1P8V_LED_BASE 1P8V_VREF_H...

Page 46: ...14 LM339A U28A VCC 3 GND 12 R208 105K R205 49 9 JMP99 LED SELECT 1 2 3 R216 10 2K 1P5V_VREF_HIGH 1P5V_VREF_LOW 1P5V_LED_IN 1P5V_LED_VF 1P8V_LED_VF 1P5V_LED_COL 1P8V_LED_COL 1P8V_LED_BASE 1P8V_VREF_HI...

Page 47: ...N_N 8 3 IN_P 9 3 OUT 14 D20 HSMB C170 2 1 C215 0 47uF R243 49 9 LM339A U37A VCC 3 GND 12 DVDD_LED_VF DVDD_LED_COL DVDD_LED_BASE DVDD_VREF_HIGH DVDD_VREF_LOW DVDD_LED_IN DVDD_LED_WINDOW_OUT DVDD_LED_PL...

Page 48: ...U40D 3 IN_N 8 3 IN_P 9 3 OUT 14 1P5V_1P5 8V_VREF_HIGH 1P5V_1P5 8V_VREF_LOW 1P5V_1P5 8V_LED_VF 1P8V_1P5 8V_LED_VF 1P8V_1P5 8V_LED_COL 1P5V_1P5 8V_LED_COL 1P8V_1P5 8V_LED_BASE 1P8V_1P5 8V_VREF_LOW 1P8V_...

Page 49: ...2 HSMB C170 2 1 JMP131 LED SELECT 1 2 3 1P5V_VDDRA_VREF_HIGH 1P5V_VDDRA_VREF_LOW 1P5V_VDDRA_LED_VF 1P5V_VDDRA_LED_BASE 1P8V_VDDRA_LED_VF 1P8V_VDDRA_LED_COL 1P5V_VDDRA_LED_COL 1P8V_VDDRA_LED_BASE 1P8V_...

Page 50: ...2K C222 0 47uF JMP133 LED ENABLE 1 2 3 1P5V_VDDRB_VREF_HIGH 1P5V_VDDRB_VREF_LOW 1P5V_VDDRB_LED_VF 1P5V_VDDRB_LED_BASE 1P8V_VDDRB_LED_VF 1P8V_VDDRB_LED_COL 1P5V_VDDRB_LED_COL 1P8V_VDDRB_LED_BASE 1P8V_...

Page 51: ...LED SELECT 1 2 3 D37 HSMB C170 2 1 0P75V_VREFT_VREF_HIGH 0P75V_VREFT_VREF_LOW 0P75V_VREFT_LED_VF 0P75V_VREFT_LED_BASE 0P9V_VREFT_LED_VF 0P9V_VREFT_LED_COL 0P75V_VREFT_LED_COL 0P9V_VREFT_LED_BASE 0P9V...

Page 52: ...C12 NC49 B12 TLK60X2 U1 26 NC0 A7 NC1 A9 NC2 A11 NC3 A12 NC4 C10 NC5 C13 NC6 H7 NC7 D8 NC8 D10 NC9 D11 NC10 D12 NC11 E8 NC12 E9 NC13 E10 NC14 E11 NC15 F8 NC16 F9 NC17 F10 NC18 F11 NC19 G8 NC20 G9 NC21...

Page 53: ...NOTE THREE PERIPHERAL PORTS ARE INCLUDED ON THIS BOARD TO ALLOW FOR OSCILLATOR CLOCK CIRCUITS OPTICAL MODULES AND ANY OTHER POSSIBLE MODULE THAT WOULD ALLOW FOR MORE AUTONOMOUS OPERATION AND TESTING...

Page 54: ...58 1 0mF 0603 CAP C1608X7R1C105K Tdk Corporation 14 6 C92 C99 C106 C113 C120 C240 1000pF 0603 CAP C0603COG500 102JNE Venkel 15 4 C84 C85 C256 C318 2 2mF 0603 CAP GRM188R71A225KE15D Murata Electronics...

Page 55: ...sumu Co Ltd 40 12 R56 R57 R73 R74 R90 R91 R107 0 0 Zero 0603 RES ERJ 3GEY0R00V Panasonic Ecg R108 R124 R125 R364 R365 41 17 R356 R423 R424 R425 R435 R436 1 00K 0603 RES RR0816P 102 B T5 Susumu Co Ltd...

Page 56: ...9 2 R369 R372 16 9K 0603 RES TNPW060316K9BEEA Vishay Dale 70 2 R128 R138 169 0603 RES TNPW0603169RBEEN Vishay Dale 71 4 R207 R256 R316 R328 17 4K 0603 RES RR0816P 1742 B T5 24C Susumu Co Ltd 72 2 R130...

Page 57: ...035K36BEEA Vishay Dale 99 1 R157 5 60K 0603 RES RG1608P 562 B T5 Susumu Co Ltd 100 1 R112 5 62K 0603 RES RG1608P 5621 B T5 Susumu Co Ltd 101 1 R129 5 90K 0603 RES RG1608P 5901 B T5 Susumu Co Ltd 102 2...

Page 58: ...U26 U29 U32 U38 U41 U56 U59 Precision Voltage SOT 23 REF2940AIDBZT Texas Instruments U65 Reference 128 3 U2 U87 U89 Voltage Supervisor SOT 23 5 TPS3125J18DBVR Texas Instruments with Manual Reset 129 1...

Page 59: ...39 JMP40 20 X 3 0 1x0 1 HTSW 150 08 G T Samtec 147 1 P24 Power Jack 2 1mm PJ 002AH Cui Inc 148 16 P1 P2 P3 P4 P5 P6 P7 P8 P9 P15 Banana Plug 4mm 108 0740 001 Emerson Network Power Co P16 P20 P23 P29 P...

Page 60: ...s www ti com 16 TLK6002EVM Board Layouts Figure 46 Top Signal Layer 1 60 TLK6002 Dual Channel 0 47 Gbps to 6 25 Gbps Multi Rate Transceiver SLLU132 October 2010 Evaluation Module Submit Documentation...

Page 61: ...uts Figure 47 Internal Ground Layers 2 4 6 8 10 61 SLLU132 October 2010 TLK6002 Dual Channel 0 47 Gbps to 6 25 Gbps Multi Rate Transceiver Evaluation Module Submit Documentation Feedback Copyright 201...

Page 62: ...Layouts www ti com Figure 48 Internal Power Layer 3 62 TLK6002 Dual Channel 0 47 Gbps to 6 25 Gbps Multi Rate Transceiver SLLU132 October 2010 Evaluation Module Submit Documentation Feedback Copyright...

Page 63: ...Layouts Figure 49 Internal Signal Layer 5 63 SLLU132 October 2010 TLK6002 Dual Channel 0 47 Gbps to 6 25 Gbps Multi Rate Transceiver Evaluation Module Submit Documentation Feedback Copyright 2010 Tex...

Page 64: ...ts www ti com Figure 50 Internal Signal Layer 7 64 TLK6002 Dual Channel 0 47 Gbps to 6 25 Gbps Multi Rate Transceiver SLLU132 October 2010 Evaluation Module Submit Documentation Feedback Copyright 201...

Page 65: ...VM Board Layouts Figure 51 Internal Power Layer 9 65 SLLU132 October 2010 TLK6002 Dual Channel 0 47 Gbps to 6 25 Gbps Multi Rate Transceiver Evaluation Module Submit Documentation Feedback Copyright 2...

Page 66: ...gure 52 Internal Ground and Power Layers 11 13 15 17 66 TLK6002 Dual Channel 0 47 Gbps to 6 25 Gbps Multi Rate Transceiver SLLU132 October 2010 Evaluation Module Submit Documentation Feedback Copyrigh...

Page 67: ...rd Layouts Figure 53 Internal Signal Layer 12 67 SLLU132 October 2010 TLK6002 Dual Channel 0 47 Gbps to 6 25 Gbps Multi Rate Transceiver Evaluation Module Submit Documentation Feedback Copyright 2010...

Page 68: ...www ti com Figure 54 Internal Signal Layer 14 68 TLK6002 Dual Channel 0 47 Gbps to 6 25 Gbps Multi Rate Transceiver SLLU132 October 2010 Evaluation Module Submit Documentation Feedback Copyright 2010...

Page 69: ...ti com TLK6002EVM Board Layouts Figure 55 Internal Power Layer 16 69 SLLU132 October 2010 TLK6002 Dual Channel 0 47 Gbps to 6 25 Gbps Multi Rate Transceiver Evaluation Module Submit Documentation Feed...

Page 70: ...w ti com Figure 56 Bottom Signal Layer 18 70 TLK6002 Dual Channel 0 47 Gbps to 6 25 Gbps Multi Rate Transceiver SLLU132 October 2010 Evaluation Module Submit Documentation Feedback Copyright 2010 Texa...

Page 71: ...4 1 0 035 L11_GND PLANE COPPER 1 2 595900 1 0 DIELECTRIC FR 4 7 0 4 1 0 035 L12_SIG CONDUCTOR COPPER 1 2 595900 1 0 6 0 50 337 DIELECTRIC FR 4 7 0 4 1 0 035 L13_GND PLANE COPPER 1 2 595900 1 0 DIELEC...

Page 72: ...ct This notice contains important safety information about temperatures and voltages For additional information on TI s environmental and or safety programs please contact the TI application engineer...

Page 73: ...h statements TI products are not authorized for use in safety critical applications such as life support where a failure of the TI product would reasonably be expected to cause severe personal injury...

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