Control and Output Status Signals
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PRTAD[4:1] selects the device port address. TLK6002 has two different PHY addresses (ports).
Selecting a unique PRTAD[4:1] per TLK6002 device allows 16 TLK6002 devices per MDIO bus.
Each channel can be accessed by setting the appropriate port address field within the serial
interface protocol transaction.
TLK6002 responds if the four MSBs of the inband PHY address field on MDIO protocol (PA[4:1])
matches PRTAD[4:1]. The LSB of PHY address field (PA[0]) determines which channel/port
within TLK6002 to respond to.
PRTAD[0] is not used functionally, but is present for device testability and compatibility with other
devices in the family of products.
Channel A responds to port address 0 within the block of two port addresses.
Channel B responds to port address 1 within the block of two port addresses.
PRTAD[0] must be grounded on the application board.
The PRTAD[3] pin in application mode must be biased with a pullup or pulldown resistor (or allow
for an isolation mechanism from the onboard driver) and not connected directly to a power or
ground plane. The application board allows the flexibility of easily reworking the PRTAD[3] signal
to a high level if the device debug is necessary (by including an uninstalled resistor to VDDO1).
REFCLK_A_SEL: Reference Clock Select Channel A. This input, when low, selects REFCLK_0_P/N as
the clock reference to Channel A SERDES macro. When high, REFCLK_1_P/N is selected as the clock
reference to Channel A SERDES macro. If software control is desired (register bit 0.1), this input signal
must be tied low. See Figure 4, “TLK6002 Reference Clock/Output Clock Architecture” of the TLK6002,
Dual-Channel 0.47Gbps to 6.25Gbps Multi-Rate Transceiver data sheet (
SLLSE34
) for more detail.
REFCLK_B_SEL: Reference Clock Select Channel B. This input, when low, selects REFCLK_0_P/N as
the clock reference to Channel B SERDES macro. When high, REFCLK_1_P/N is selected as the clock
reference to Channel B SERDES macro. If software control is desired (register bit 0.1), this input signal
must be tied low. See Figure 4, “TLK6002 Reference Clock/Output Clock Architecture” of the TLK6002
data sheet (
SLLSE34
) for more detail.
RATE_A[2:0]: Channel A Rate select pins. These pins put channel A into one of the four supported
(full/half/quarter/eighth) channel operation rates, enable software control, or enable Auto Rate Sense
(ARS):
000 – Full Rate mode
001 – Half Rate mode
010 – Quarter Rate mode
011 – Eighth Rate mode
100 – Software Selectable Rate
101 – Channel A Auto Rate Sense (ARS) Function Enabled.
Channel A SERDES settings are determined by Channel A ARS machine. CLK_OUT_P/N selected
by CLK_OUT_SEL. See Table 9 of the TLK6002 data sheet (
SLLSE34
) for additional details on
CLK_OUT_P/N.
110 – Channel A Auto Rate Sense (ARS) Function Enabled.
Channel A SERDES settings are determined by Channel A ARS machine. CLK_OUT_P/N is
not selected by CLK_OUT_SEL. Channel B may not be simultaneously configured with
RATE_B = 110 with respect to CLK_OUT_P/N, this setting has the highest priority. See Table
9 of the TLK6002 data sheet (
SLLSE34
) for additional details on CLK_OUT_P/N.
111 – Channel A Auto Rate Sense (ARS) Function Enabled – Slave Mode.
If Channel B ARS is enabled (Rate B = 101 or 110 only):
Channel A SERDES settings are determined by Channel B ARS machine. CLK_OUT_P/N is
not selected by CLK_OUT_SEL. See Table 9 of the TLK6002 data sheet (
SLLSE34
) for
additional details on CLK_OUT_P/N.
12
TLK6002 Dual-Channel, 0.47-Gbps to 6.25-Gbps, Multi-Rate Transceiver
SLLU132 – October 2010
Evaluation Module
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