![background image](http://html.mh-extra.com/html/texas-instruments/tida-050043/tida-050043_design-manual_1097054006.webp)
DAT[0-7]
CLK
CMD
VCCQ
10 k
Ÿ
SD2_DATA[0-7]
SD2_CLK
SD2_CMD
SD2_RESET#
RESET#
10
Ÿ
VCC
3V3
1V8
1V8
MTFC8GAKAJCN-4M IT
i.MX 6ULL
VSS
10
Ÿ
DS
NVCC_NAND
1V8
Note:
NVCC_NAND and VCCQ needs to be 1V8 for HS200
Mode. CLK/CMD/DATA lines impedance need to be 50
Ÿ
VSS
10 k
Ÿ
QSPIA_DATA0
QSPIA_DATA1
QSPIA_DATA2
QSPIA_SCLK
MT25QU256ABA1EW7-0SIT
i.MX 6ULL
NVCC_NAND
1V8
QSPIA_DATA3
QSPIA_SS0_B
DQ0
DQ1
W#/DQ2
C
VCC
1V8
HOLD#/DQ3
S#
VSS
1V8
10 k
Ÿ
VSS
System Overview
6
TIDUEW7 – May 2020
Copyright © 2020, Texas Instruments Incorporated
Integrated Power Supply Reference Design for NXP i.MX 6ULL
2.2.2.2
Quad SPI NOR Flash
The i.MX 6ULL processor has a Serial NOR Flash interface (QSPI). This design uses Micron’s
MT25QU256ABA1EW7-0SIT Serial NOR Flash memory with a density of 256 Mb (32 MB) supports a
clock frequency of 166 MHz for data through-put up to 90 MBps at DTR with an operating voltage of 1.7 V
to 2.0 V, and the interface diagram of this Flash IC with the processor is shown in
.
DESCRIPTION
MFG.
PART NUMBER
IC, NOR Flash, 32MB, 133MHz, SPI, 1.7-2V, W-PDFN-8
Micron
MT25QU256ABA1EW7-0SIT
Figure 3. QSPI NOR Flash Interface
2.2.2.3
eMMC iNAND
The i.MX 6ULL processor supports eMMC versions 4.4, 4.41, and 4.5. This design uses Micron's 8-GB
MTFC8GAKAJCN-4M IT, an eMMC version 5.0 memory device. The eMMC version 5.0 specification
indicates is backwards compatibility, allowing it to work correctly with the processor. The data transfer
speed used is HS200 mode with 1.8-V I/O voltage. The interface diagram of eMMC with the processor is
shown in
.
DESCRIPTION
MFG.
PART NUMBER
IC, eMMC 5.0, 8GB, x8bit, 52MHz, VFBGA-153
Micron
MTFC8GAKAJCN-4M IT
Figure 4. eMMC Interface